static void Edma3CCErrHandlerIsr(void)
{
volatile unsigned int pendingIrqs = 0;
unsigned int Cnt = 0;
unsigned int index = 1;
unsigned int regionNum = 0;
unsigned int evtqueNum = 0;
IntSystemStatusClear(SYS_INT_CCERRINT);
if((HWREG(SOC_EDMA30CC_0_REGS + EDMA3CC_EMR) != 0 )
|| (HWREG(SOC_EDMA30CC_0_REGS + EDMA3CC_QEMR) != 0)
|| (HWREG(SOC_EDMA30CC_0_REGS + EDMA3CC_CCERR) != 0))
{
/* Loop for EDMA3CC_ERR_HANDLER_RETRY_COUNT number of time, breaks
when no pending interrupt is found. */
while ((Cnt < EDMA3CC_ERR_HANDLER_RETRY_COUNT) && (index != 0))
{
index = 0;
pendingIrqs = HWREG(SOC_EDMA30CC_0_REGS + EDMA3CC_EMR);
while (pendingIrqs)
{
/*Process all the pending interrupts.*/
if((pendingIrqs & 1)==TRUE)
{
/* Write to EMCR to clear the corresponding EMR bits.*/
HWREG(SOC_EDMA30CC_0_REGS + EDMA3CC_EMCR) = (1<<index);
/*Clear any SER*/
HWREG(SOC_EDMA30CC_0_REGS + EDMA3CC_S_SECR(regionNum)) = (1<<index);
}
++index;
pendingIrqs >>= 1;
}
index = 0;
pendingIrqs = HWREG(SOC_EDMA30CC_0_REGS + EDMA3CC_QEMR);
while (pendingIrqs)
{
/*Process all the pending interrupts.*/
if((pendingIrqs & 1)==TRUE)
{
/* Here write to QEMCR to clear the corresponding QEMR bits.*/
HWREG(SOC_EDMA30CC_0_REGS + EDMA3CC_QEMCR) = (1<<index);
/*Clear any QSER*/
HWREG(SOC_EDMA30CC_0_REGS + EDMA3CC_S_QSECR(0)) = (1<<index);
}
++index;
pendingIrqs >>= 1;
}
index = 0;
pendingIrqs = HWREG(SOC_EDMA30CC_0_REGS + EDMA3CC_CCERR);
if(pendingIrqs != 0)
{
/* Process all the pending CC error interrupts. */
/* Queue threshold error for different event queues.*/
for (evtqueNum = 0; evtqueNum < EDMA3_0_NUM_EVTQUE; evtqueNum++)
{
if((pendingIrqs & (1 << evtqueNum)) != 0)
{
/* Clear the error interrupt. */
HWREG(SOC_EDMA30CC_0_REGS + EDMA3CC_CCERRCLR) = (1 << evtqueNum);
}
}
/* Transfer completion code error. */
if ((pendingIrqs & (1 << EDMA3CC_CCERR_TCCERR_SHIFT)) != 0)
{
HWREG(SOC_EDMA30CC_0_REGS + EDMA3CC_CCERRCLR) = \
(0x01 << EDMA3CC_CCERR_TCCERR_SHIFT);
}
++index;
}
Cnt++;
}
}
}
void
EDMA30CCErrIsr(intptr_t unused) {
syslog(LOG_ERROR, "%s(): EDMA3_0_CC0_ERRINT", __FUNCTION__);
const unsigned int baseAdd = SOC_EDMA30CC_0_REGS;
volatile unsigned int pendingIrqs = 0;
unsigned int regionNum = 0;
unsigned int evtqueNum = 0;
unsigned int index = 1;
// unsigned int Cnt = 0;
if((HWREG(baseAdd + EDMA3CC_EMR) != 0 ) || \
(HWREG(baseAdd + EDMA3CC_QEMR) != 0) || \
(HWREG(baseAdd + EDMA3CC_CCERR) != 0))
{
/* Loop for EDMA3CC_ERR_HANDLER_RETRY_COUNT number of time, breaks
when no pending interrupt is found */
// while ((Cnt < EDMA3CC_ERR_HANDLER_RETRY_COUNT) && (index != 0u))
// {
index = 0u;
pendingIrqs = HWREG(baseAdd + EDMA3CC_EMR);
while (pendingIrqs)
{
/*Process all the pending interrupts*/
if((pendingIrqs & 1u)==TRUE)
{
syslog(LOG_ERROR, "EDMA3 Error. EDMA3CC_EMR channel %d", index);
// EDMA3CCPaRAMEntry param;
// EDMA3GetPaRAM(baseAdd, index, ¶m);
// syslog(LOG_ERROR, "PaRAM.aCnt: %d", param.aCnt);
// syslog(LOG_ERROR, "PaRAM.bCnt: %d", param.bCnt);
// syslog(LOG_ERROR, "PaRAM.bCntReload: %d", param.bCntReload);
// syslog(LOG_ERROR, "PaRAM.cCnt: %d", param.cCnt);
// syslog(LOG_ERROR, "PaRAM.destAddr: 0x%x", param.destAddr);
// syslog(LOG_ERROR, "PaRAM.destBIdx: %d", param.destBIdx);
// syslog(LOG_ERROR, "PaRAM.destCIdx: %d", param.destCIdx);
// syslog(LOG_ERROR, "PaRAM.linkAddr: 0x%x", param.linkAddr);
// syslog(LOG_ERROR, "PaRAM.opt: 0x%x", param.opt);
// syslog(LOG_ERROR, "PaRAM.srcAddr: 0x%x", param.srcAddr);
// syslog(LOG_ERROR, "PaRAM.srcBIdx: %d", param.srcBIdx);
// syslog(LOG_ERROR, "PaRAM.srcCIdx: %d", param.srcCIdx);
/* Write to EMCR to clear the corresponding EMR bits.*/
HWREG(baseAdd + EDMA3CC_EMCR) = (1u<<index);
/*Clear any SER*/
HWREG(baseAdd + EDMA3CC_S_SECR(regionNum)) = (1u<<index);
}
++index;
pendingIrqs >>= 1u;
}
index = 0u;
pendingIrqs = HWREG(baseAdd + EDMA3CC_QEMR);
while (pendingIrqs)
{
/*Process all the pending interrupts*/
if((pendingIrqs & 1u)==TRUE)
{
syslog(LOG_ERROR, "EDMA3 Error. EDMA3CC_QEMR");
/* Here write to QEMCR to clear the corresponding QEMR bits*/
HWREG(baseAdd + EDMA3CC_QEMCR) = (1u<<index);
/*Clear any QSER*/
HWREG(baseAdd + EDMA3CC_S_QSECR(0)) = (1u<<index);
}
++index;
pendingIrqs >>= 1u;
}
index = 0u;
pendingIrqs = HWREG(baseAdd + EDMA3CC_CCERR);
if (pendingIrqs != 0u)
{
/* Process all the pending CC error interrupts. */
/* Queue threshold error for different event queues.*/
for (evtqueNum = 0u; evtqueNum < EDMA3_0_NUM_EVTQUE; evtqueNum++)
{
if((pendingIrqs & (1u << evtqueNum)) != 0u)
{
syslog(LOG_ERROR, "EDMA3 Error. EDMA3CC_CCERRCLR");
/* Clear the error interrupt. */
HWREG(baseAdd + EDMA3CC_CCERRCLR) = (1u << evtqueNum);
}
}
/* Transfer completion code error. */
if ((pendingIrqs & (1 << EDMA3CC_CCERR_TCCERR_SHIFT)) != 0u)
{
syslog(LOG_ERROR, "EDMA3 Error. EDMA3CC_CCERR_TCCERR_SHIFT");
HWREG(baseAdd + EDMA3CC_CCERRCLR) = \
(0x01u << EDMA3CC_CCERR_TCCERR_SHIFT);
}
++index;
}
// Cnt++;
// }
} else {
