Beispiel #1
0
/* Initialize the hardware */
void low_level_MAC_init(void)
{
  uint32_t i;
  uint8_t macaddr[NETIF_MAX_HWADDR_LEN];

  /* set MAC hardware address */
  macaddr[0] =  MAC_ADDR0;
  macaddr[1] =  MAC_ADDR1;
  macaddr[2] =  MAC_ADDR2;
  macaddr[3] =  MAC_ADDR3;
  macaddr[4] =  MAC_ADDR4;
  macaddr[5] =  MAC_ADDR5;

  /* initialize MAC address in ethernet MAC */ 
  ETH_MACAddressConfig(ETH_MAC_Address0, macaddr); 

  /* Initialize Tx Descriptors list: Chain Mode */
  ETH_DMATxDescChainInit(DMATxDscrTab, &Tx_Buff[0][0], ETH_TXBUFNB);
  /* Initialize Rx Descriptors list: Chain Mode  */
  ETH_DMARxDescChainInit(DMARxDscrTab, &Rx_Buff[0][0], ETH_RXBUFNB);

  /* Enable Ethernet Rx interrrupt */
  for(i=0; i<ETH_RXBUFNB; i++)
  {
    ETH_DMARxDescReceiveITConfig(&DMARxDscrTab[i], ENABLE);
  }

#ifdef CHECKSUM_BY_HARDWARE
  /* Enable the checksum insertion for the Tx frames */
  for(i=0; i<ETH_TXBUFNB; i++)
  {
    ETH_DMATxDescChecksumInsertionConfig(&DMATxDscrTab[i], ETH_DMATxDesc_ChecksumTCPUDPICMPFull);
  }
#endif
}
/*************************************************************************
 * Function Name: eth_macdma_it_config
 * Parameters:
 * Return:
 *
 * Description: configuration of MAC/DMA Controller
 *
 *************************************************************************/
static int eth_macdma_it_config(void){
   //
   int i=0;
   /* Initialize Tx Descriptors list: Chain Mode */
   ETH_DMATxDescChainInit(DMATxDscrTab, &Tx_Buff[0][0], ETH_TXBUFNB);
   /* Initialize Rx Descriptors list: Chain Mode  */
   ETH_DMARxDescChainInit(DMARxDscrTab, &Rx_Buff[0][0], ETH_RXBUFNB);
   
   /* Enable Ethernet Rx/Tx interrrupt */
   { 
      for(i=0; i<ETH_RXBUFNB; i++)
      {
         ETH_DMARxDescReceiveITConfig(&DMARxDscrTab[i], ENABLE);
      }
      
      for(i=0; i<ETH_TXBUFNB; i++)
      {
        ETH_DMATxDescTransmitITConfig(&DMATxDscrTab[i], ENABLE);
      }
   }
   #ifdef CHECKSUM_BY_HARDWARE
	/* Enable the checksum insertion for the Tx frames */
	{
		for(i=0; i<ETH_TXBUFNB; i++)
		{
		  ETH_DMATxDescChecksumInsertionConfig(&DMATxDscrTab[i], ETH_DMATxDesc_ChecksumTCPUDPICMPFull);
		}
	} 
	#endif
   //
   eth_nvic_configuration();
   /* Enable the Ethernet Rx Interrupt */
   ETH_DMAITConfig(ETH_DMA_IT_NIS | ETH_DMA_IT_R | ETH_DMA_IT_T, ENABLE);
   return 0;
}
Beispiel #3
0
/**
 * In this function, the hardware should be initialized.
 * Called from ethernetif_init().
 *
 * @param netif the already initialized lwip network interface structure
 *        for this ethernetif
 */
static void
low_level_init(struct netif *netif)
{
  SYS_ARCH_DECL_PROTECT(sr);
    
  /* set MAC hardware address length */
  netif->hwaddr_len = ETHARP_HWADDR_LEN;

  /* set MAC hardware address */
  netif->hwaddr[0] =  MACaddr[0];
  netif->hwaddr[1] =  MACaddr[1];
  netif->hwaddr[2] =  MACaddr[2];
  netif->hwaddr[3] =  MACaddr[3];
  netif->hwaddr[4] =  MACaddr[4];
  netif->hwaddr[5] =  MACaddr[5];

  /* maximum transfer unit */
  netif->mtu = 1500;

  /* device capabilities */
  /* don't set NETIF_FLAG_ETHARP if this device is not an ethernet one */
  netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | NETIF_FLAG_LINK_UP;

  SYS_ARCH_PROTECT(sr);
  
  /* Initialize Tx Descriptors list: Chain Mode */
  ETH_DMATxDescChainInit(DMATxDscrTab, &Tx_Buff[0][0], ETH_TXBUFNB);
  /* Initialize Rx Descriptors list: Chain Mode  */
  ETH_DMARxDescChainInit(DMARxDscrTab, &Rx_Buff[0][0], ETH_RXBUFNB);

/*----------added by Wang Mengyin 2010-07-20----------------------------------*/  
  // install Ethernet Interrupt Handlers
  // enable Ethernet Interrupt in NVIC and set up ISR
  BSP_IntVectSet(BSP_INT_ID_ETH, LwIP_Pkt_Handle);
  BSP_IntEn(BSP_INT_ID_ETH);
  
  /* Enable Ethernet Rx interrrupt */
  { int i;
    for(i=0; i<ETH_RXBUFNB; i++)
    {
      ETH_DMARxDescReceiveITConfig(&DMARxDscrTab[i], ENABLE);
    }
  }

#ifdef CHECKSUM_BY_HARDWARE
  /* Enable the checksum insertion for the Tx frames */
  { int i;
    for(i=0; i<ETH_TXBUFNB; i++)
    {
      ETH_DMATxDescChecksumInsertionConfig(&DMATxDscrTab[i], ETH_DMATxDesc_ChecksumTCPUDPICMPFull);
    }
  }
#endif

  SYS_ARCH_UNPROTECT(sr);
  
  /* Enable MAC and DMA transmission and reception */
  ETH_Start();

}
Beispiel #4
0
void net_init()
{
	int i;
  uint8_t mac_addr[6];

	mac_addr[0] = MAC_ADDR0;
	mac_addr[1] = MAC_ADDR1;
	mac_addr[2] = MAC_ADDR2;
	mac_addr[3] = MAC_ADDR3;
	mac_addr[4] = MAC_ADDR4;
	mac_addr[5] = MAC_ADDR5;

	ETH_BSP_Config();

	ETH_MACAddressConfig(ETH_MAC_Address0, &mac_addr);

	ETH_DMATxDescChainInit(DMATxDscrTab, &Tx_Buff[0][0], ETH_TXBUFNB);
	ETH_DMARxDescChainInit(DMARxDscrTab, &Rx_Buff[0][0], ETH_RXBUFNB);

	for (i = 0; i < ETH_TXBUFNB; i++)
	{
		ETH_DMATxDescChecksumInsertionConfig(&DMATxDscrTab[i], ETH_DMATxDesc_ChecksumByPass);
	}

	ETH_Start();
}
Beispiel #5
0
unsigned long ENET_Configuration(void)
{
	unsigned long res=0;
	unsigned short tmp;

	RCC_AHBPeriphClockCmd(RCC_AHBPeriph_ETH_MAC | RCC_AHBPeriph_ETH_MAC_Tx |
	                        RCC_AHBPeriph_ETH_MAC_Rx, ENABLE);

	ETH_DeInit();
	get_mac(mac);
	ETH_MACAddressConfig(ETH_MAC_Address0, mac);
	GPIO_ETH_MediaInterfaceConfig(GPIO_ETH_MediaInterface_RMII);

	ETH_SoftwareReset();
	while(ETH_GetSoftwareResetStatus()==SET) vTaskDelayUntil( &ExLastExecutionTime, ( portTickType ) 1 / portTICK_RATE_MS );
	ETH_StructInit(&ETH_InitStructure);


	ETH_InitStructure.ETH_AutoNegotiation = ETH_AutoNegotiation_Enable;
	ETH_InitStructure.ETH_Watchdog = ETH_Watchdog_Disable;
	ETH_InitStructure.ETH_Jabber = ETH_Jabber_Disable;
	ETH_InitStructure.ETH_JumboFrame = ETH_JumboFrame_Disable;
	ETH_InitStructure.ETH_InterFrameGap = ETH_InterFrameGap_64Bit;
	ETH_InitStructure.ETH_CarrierSense = ETH_CarrierSense_Enable;
	ETH_InitStructure.ETH_Speed = ETH_Speed_10M;
	ETH_InitStructure.ETH_ReceiveOwn = ETH_ReceiveOwn_Disable;
	ETH_InitStructure.ETH_LoopbackMode = ETH_LoopbackMode_Disable;
	ETH_InitStructure.ETH_Mode = ETH_Mode_FullDuplex;
	ETH_InitStructure.ETH_RetryTransmission = ETH_RetryTransmission_Disable;
	ETH_InitStructure.ETH_AutomaticPadCRCStrip = ETH_AutomaticPadCRCStrip_Disable;
	ETH_InitStructure.ETH_BackOffLimit = ETH_BackOffLimit_10;
	ETH_InitStructure.ETH_DeferralCheck = ETH_DeferralCheck_Disable;
	ETH_InitStructure.ETH_ReceiveAll = ETH_ReceiveAll_Enable;
	ETH_InitStructure.ETH_PassControlFrames = ETH_PassControlFrames_ForwardPassedAddrFilter;
	ETH_InitStructure.ETH_BroadcastFramesReception = ETH_BroadcastFramesReception_Disable;
	ETH_InitStructure.ETH_DestinationAddrFilter = ETH_DestinationAddrFilter_Normal;
	ETH_InitStructure.ETH_PromiscuousMode = ETH_PromiscuousMode_Disable;
	ETH_InitStructure.ETH_MulticastFramesFilter = ETH_MulticastFramesFilter_Perfect;
	ETH_InitStructure.ETH_UnicastFramesFilter = ETH_UnicastFramesFilter_Perfect;
	ETH_InitStructure.ETH_RxDMABurstLength = ETH_RxDMABurstLength_32Beat;
	ETH_InitStructure.ETH_TxDMABurstLength = ETH_TxDMABurstLength_32Beat;
	ETH_InitStructure.ETH_FlushReceivedFrame = ETH_FlushReceivedFrame_Enable;
	ETH_InitStructure.ETH_SecondFrameOperate = ETH_SecondFrameOperate_Enable;
	ETH_InitStructure.ETH_FixedBurst = ETH_FixedBurst_Enable;
	res = ETH_Init(&ETH_InitStructure, PHY_ADDRESS);

	ETH_DMAITConfig(ETH_DMA_IT_NIS | ETH_DMA_IT_R | ETH_DMA_IT_T, ENABLE);
	for(tmp=0;tmp<ETH_RXBUFNB;tmp++) Rx_Buff[tmp] = (unsigned long)&ETH_RX[tmp][0];
	for(tmp=0;tmp<ETH_TXBUFNB;tmp++) Tx_Buff[tmp] = (unsigned long)&ETH_TX[tmp][0];
	ETH_DMATxDescChainInit(DMATxDscrTab, (unsigned char*)Tx_Buff, ETH_TXBUFNB);
	ETH_DMARxDescChainInit(DMARxDscrTab, (unsigned char*)Rx_Buff, ETH_RXBUFNB);
	for(tmp=0;tmp<ETH_RXBUFNB;tmp++){ETH_DMARxDescReceiveITConfig(DMARxDscrTab+tmp, ENABLE);}
	ETH_Start();
	ETH_ResumeDMAReception();
	return(res);
}
Beispiel #6
0
/**
 * In this function, the hardware should be initialized.
 * Called from ethernetif_init().
 *
 * @param netif the already initialized lwip network interface structure
 *        for this ethernetif
 */
static void
low_level_init(struct netif *netif)
{
  /* set MAC hardware address length */
  netif->hwaddr_len = ETHARP_HWADDR_LEN;

  /* set MAC hardware address */
  netif->hwaddr[0] =  MACaddr[0];
  netif->hwaddr[1] =  MACaddr[1];
  netif->hwaddr[2] =  MACaddr[2];
  netif->hwaddr[3] =  MACaddr[3];
  netif->hwaddr[4] =  MACaddr[4];
  netif->hwaddr[5] =  MACaddr[5];

  /* maximum transfer unit */
  netif->mtu = 1500;

  /* device capabilities */
  /* don't set NETIF_FLAG_ETHARP if this device is not an ethernet one */
  netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | NETIF_FLAG_LINK_UP;

  /* Initialize Tx Descriptors list: Chain Mode */
  ETH_DMATxDescChainInit(DMATxDscrTab, &Tx_Buff[0][0], ETH_TXBUFNB);
  /* Initialize Rx Descriptors list: Chain Mode  */
  ETH_DMARxDescChainInit(DMARxDscrTab, &Rx_Buff[0][0], ETH_RXBUFNB);

  /* Enable Ethernet Rx interrrupt */
  { int i;
    for(i=0; i<ETH_RXBUFNB; i++)
    {
      ETH_DMARxDescReceiveITConfig(&DMARxDscrTab[i], ENABLE);
    }
  }

#ifdef CHECKSUM_BY_HARDWARE
  /* Enable the checksum insertion for the Tx frames */
  { int i;
    for(i=0; i<ETH_TXBUFNB; i++)
    {
      ETH_DMATxDescChecksumInsertionConfig(&DMATxDscrTab[i], ETH_DMATxDesc_ChecksumTCPUDPICMPFull);
    }
  }
#endif

  /* Enable MAC and DMA transmission and reception */
  ETH_Start();

}
Beispiel #7
0
/**
 * In this function, the hardware should be initialized.
 * Called from ethernetif_init().
 *
 * @param netif the already initialized lwip network interface structure
 *        for this ethernetif
 */
static void low_level_init(struct netif *netif)
{
#ifdef CHECKSUM_BY_HARDWARE
  int i; 
#endif
  /* set MAC hardware address length */
  netif->hwaddr_len = ETHARP_HWADDR_LEN;

  /* set MAC hardware address */
  netif->hwaddr[0] =  MAC_ADDR0;
  netif->hwaddr[1] =  MAC_ADDR1;
  netif->hwaddr[2] =  MAC_ADDR2;
  netif->hwaddr[3] =  MAC_ADDR3;
  netif->hwaddr[4] =  MAC_ADDR4;
  netif->hwaddr[5] =  MAC_ADDR5;
  
  /* initialize MAC address in ethernet MAC */ 
  ETH_MACAddressConfig(ETH_MAC_Address0, netif->hwaddr); 

  /* maximum transfer unit */
  netif->mtu = 1500;

  /* device capabilities */
  /* don't set NETIF_FLAG_ETHARP if this device is not an ethernet one */
  netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | NETIF_FLAG_LINK_UP;
   /************************************************************************/
	 //DMATxDscrTab->ControlBufferSize = 100;
  /* Initialize Tx Descriptors list: Chain Mode */
  ETH_DMATxDescChainInit(DMATxDscrTab, &Tx_Buff[0][0], ETH_TXBUFNB);
  /* Initialize Rx Descriptors list: Chain Mode  */
  ETH_DMARxDescChainInit(DMARxDscrTab, &Rx_Buff[0][0], ETH_RXBUFNB);
  
#ifdef CHECKSUM_BY_HARDWARE
  /* Enable the TCP, UDP and ICMP checksum insertion for the Tx frames */
  for(i=0; i<ETH_TXBUFNB; i++)
    {
      ETH_DMATxDescChecksumInsertionConfig(&DMATxDscrTab[i], ETH_DMATxDesc_ChecksumTCPUDPICMPFull);
    }
#endif

   /* Note: TCP, UDP, ICMP checksum checking for received frame are enabled in DMA config */

  /* Enable MAC and DMA transmission and reception */
  ETH_Start();

}
Beispiel #8
0
/**
 * In this function, the hardware should be initialized.
 * Called from ethernetif_init().
 *
 * @param netif the already initialized lwip network interface structure
 *        for this ethernetif
 */
static void low_level_init(struct netif *netif)
{
  uint32_t i;
 
  /* set netif MAC hardware address length */
  netif->hwaddr_len = ETHARP_HWADDR_LEN;
	
  /* set netif MAC hardware address */
  netif->hwaddr[0] =  MAC_ADDR0;
  netif->hwaddr[1] =  MAC_ADDR1;
  netif->hwaddr[2] =  MAC_ADDR2;
  netif->hwaddr[3] =  MAC_ADDR3;
  netif->hwaddr[4] =  MAC_ADDR4;
  netif->hwaddr[5] =  MAC_ADDR5;
  
  /* set netif maximum transfer unit */
  netif->mtu = 1500;

  /* Accept broadcast address and ARP traffic */
  netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP;
  
  s_pxNetIf =netif;
 
  /* create binary semaphore used for informing ethernetif of frame reception */
  if (s_xSemaphore == NULL)
  {
    s_xSemaphore= xSemaphoreCreateCounting(20,0);
  }

  /* initialize MAC address in ethernet MAC */ 
  ETH_MACAddressConfig(ETH_MAC_Address0, netif->hwaddr); 
  
  /* Initialize Tx Descriptors list: Chain Mode */
  ETH_DMATxDescChainInit(DMATxDscrTab, &Tx_Buff[0][0], ETH_TXBUFNB);
  /* Initialize Rx Descriptors list: Chain Mode  */
  ETH_DMARxDescChainInit(DMARxDscrTab, &Rx_Buff[0][0], ETH_RXBUFNB);
  
  /* Enable Ethernet Rx interrrupt */
  { 
    for(i=0; i<ETH_RXBUFNB; i++)
    {
      ETH_DMARxDescReceiveITConfig(&DMARxDscrTab[i], ENABLE);
    }
  }

#ifdef CHECKSUM_BY_HARDWARE
  /* Enable the checksum insertion for the Tx frames */
  {
    for(i=0; i<ETH_TXBUFNB; i++)
    {
      ETH_DMATxDescChecksumInsertionConfig(&DMATxDscrTab[i], ETH_DMATxDesc_ChecksumTCPUDPICMPFull);
    }
  } 
#endif
  
  /* create the task that handles the ETH_MAC */
  //xTaskCreate(ethernetif_input, (signed char*) "Eth_if", netifINTERFACE_TASK_STACK_SIZE, NULL,
  //            netifINTERFACE_TASK_PRIORITY,NULL);
  
  /* Enable MAC and DMA transmission and reception */
  ETH_Start();   
}
Beispiel #9
0
    bool MacBase::initialise(const Parameters& params) {

      ETH_DMADESCTypeDef *txdesc;
      int i;

      // save parameters

      _params=params;

      // subscribe to send and notify events

      this->NetworkSendEventSender.insertSubscriber(NetworkSendEventSourceSlot::bind(this,&MacBase::onSend));

      // set our MAC address

      ETH_MACAddressConfig(ETH_MAC_Address0,const_cast<uint8_t *>(params.mac_address.macAddress));

      // initialise the receive descriptor chain

      _receiveDmaDescriptors.reset(new ETH_DMADESCTypeDef[params.mac_receiveBufferCount]);
      _receiveBuffers.reset(new uint8_t[params.mac_receiveBufferCount][ETH_MAX_PACKET_SIZE]);
      ETH_DMARxDescChainInit(&_receiveDmaDescriptors[0],&_receiveBuffers[0][0],params.mac_receiveBufferCount);

      // enable interrupts on all the receive buffers

      for(i=0;i<params.mac_receiveBufferCount;i++)
        ETH_DMARxDescReceiveITConfig(&_receiveDmaDescriptors[i],ENABLE);

      // initialise the transmit descriptor ring

      _transmitDmaDescriptors.reset(new ETH_DMADESCTypeDef[params.mac_transmitBufferCount]);
      _transmitNetBuffers.reset(new NetBuffer *[params.mac_transmitBufferCount]);
      txdesc=_transmitDmaDescriptors.get();

      // initialise the transmit ring buffer. the DMA descriptors are in contiguous memory blocks
      // and we make full use of the ability to transmit up to 2 blocks per descriptor

      for(i=0;i<params.mac_transmitBufferCount;i++) {

        txdesc->Status=ETH_DMATxDesc_IC;        // interrupt on complete
        txdesc->Buffer1Addr=0;                  // not yet, nothing to send
        txdesc->Buffer2NextDescAddr=0;          // not yet, nothing to send

        if(i==params.mac_transmitBufferCount-1)
          txdesc->Status|=ETH_DMATxDesc_TER;    // end of ring

        // clear out the NetBuffer pointer associated with this entry

        _transmitNetBuffers[i]=nullptr;

        // advance to next buffer

        txdesc++;
      }

      // set the base table address

      ETH->DMATDLAR=reinterpret_cast<uint32_t>(_transmitDmaDescriptors.get());

      // this is the next one to consider sending

      _transmitBufferIndex=0;
      return true;
    }
Beispiel #10
0
/**
 * In this function, the hardware should be initialized.
 * Called from ethernetif_init().
 *
 * @param netif the already initialized lwip network interface structure
 *        for this ethernetif
 */
static void low_level_init(struct netif *netif)
{
#ifdef CHECKSUM_BY_HARDWARE
  int i; 
#endif
  /* set MAC hardware address length */
  netif->hwaddr_len = ETHARP_HWADDR_LEN;
  /* set MAC hardware address */


#if defined(MAC_ADDR0) && defined(MAC_ADDR1) && defined(MAC_ADDR2) && defined(MAC_ADDR3) && defined(MAC_ADDR4) && defined(MAC_ADDR5)
  netif->hwaddr[0] =  MAC_ADDR0;
  netif->hwaddr[1] =  MAC_ADDR1;
  netif->hwaddr[2] =  MAC_ADDR2;
  netif->hwaddr[3] =  MAC_ADDR3;
  netif->hwaddr[4] =  MAC_ADDR4;
  netif->hwaddr[5] =  MAC_ADDR5;
#warning "User defined MAC is used for MAC address settings. Address is defined as in main.h file"

#endif

#if !defined(MAC_ADDR0) || !defined(MAC_ADDR1) || !defined(MAC_ADDR2) || !defined(MAC_ADDR3) || !defined(MAC_ADDR4) || !defined(MAC_ADDR5)
  netif->hwaddr[0] =  TM_ID_GetUnique8(0);
  netif->hwaddr[1] =  TM_ID_GetUnique8(1);
  netif->hwaddr[2] =  TM_ID_GetUnique8(2);
  netif->hwaddr[3] =  TM_ID_GetUnique8(3);
  netif->hwaddr[4] =  TM_ID_GetUnique8(4);
  netif->hwaddr[5] =  TM_ID_GetUnique8(5);
#warning "Custom MAC address not defined in main.h file. Using unique STM32F4 ID as MAC address"
#endif
  


/* define below may not be needed because we can set mac based on unique ID written in STM32F4 processor */
#ifdef CUSTOM_MAC
  // TODO: add checking for correct mac set, if no custom mac is set use default mac set in main.h
  TM_BKPSRAM_Init();
  netif->hwaddr[0] =  TM_BKPSRAM_Read8(1);
  netif->hwaddr[1] =  TM_BKPSRAM_Read8(2);
  netif->hwaddr[2] =  TM_BKPSRAM_Read8(3);
  netif->hwaddr[3] =  TM_ID_GetUnique32(0);
  netif->hwaddr[4] =  TM_ID_GetUnique32(1);
  netif->hwaddr[5] =  TM_ID_GetUnique32(2);
#endif
  
  
  /* initialize MAC address in ethernet MAC */ 
  ETH_MACAddressConfig(ETH_MAC_Address0, netif->hwaddr); 

  /* maximum transfer unit */
  netif->mtu = 1500;

  /* device capabilities */
  /* don't set NETIF_FLAG_ETHARP if this device is not an ethernet one */
  netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | NETIF_FLAG_LINK_UP;

  /* Initialize Tx Descriptors list: Chain Mode */
  ETH_DMATxDescChainInit(DMATxDscrTab, &Tx_Buff[0][0], ETH_TXBUFNB);
  /* Initialize Rx Descriptors list: Chain Mode  */
  ETH_DMARxDescChainInit(DMARxDscrTab, &Rx_Buff[0][0], ETH_RXBUFNB);
  
#ifdef CHECKSUM_BY_HARDWARE
  /* Enable the TCP, UDP and ICMP checksum insertion for the Tx frames */
  for(i=0; i<ETH_TXBUFNB; i++)
    {
      ETH_DMATxDescChecksumInsertionConfig(&DMATxDscrTab[i], ETH_DMATxDesc_ChecksumTCPUDPICMPFull);
    }
#endif

   /* Note: TCP, UDP, ICMP checksum checking for received frame are enabled in DMA config */

  /* Enable MAC and DMA transmission and reception */
  ETH_Start();

}
Beispiel #11
0
/* initialize the interface */
static rt_err_t rt_stm32_eth_init(rt_device_t dev)
{
	int i;

	/* MAC address configuration */
	ETH_MACAddressConfig(ETH_MAC_Address0, (u8*)&stm32_eth_device.dev_addr[0]);
	
	/* Initialize Tx Descriptors list: Chain Mode */
	ETH_DMATxDescChainInit(DMATxDscrTab, &Tx_Buff[0][0], ETH_TXBUFNB);
	/* Initialize Rx Descriptors list: Chain Mode  */
	ETH_DMARxDescChainInit(DMARxDscrTab, &Rx_Buff[0][0], ETH_RXBUFNB);

	 /* Enable Ethernet Rx interrrupt */
	{ 
		for(i=0; i<ETH_RXBUFNB; i++)
		{
		  ETH_DMARxDescReceiveITConfig(&DMARxDscrTab[i], ENABLE);
		}
	}
	
	#ifdef CHECKSUM_BY_HARDWARE
	/* Enable the checksum insertion for the Tx frames */
	{
		for(i=0; i<ETH_TXBUFNB; i++)
		{
		  ETH_DMATxDescChecksumInsertionConfig(&DMATxDscrTab[i], ETH_DMATxDesc_ChecksumTCPUDPICMPFull);
		}
	} 
	#endif

	{
		uint16_t tmp, i=10000;

		tmp = ETH_ReadPHYRegister(DP83848_PHY_ADDRESS, PHY_CR);
		ETH_WritePHYRegister(DP83848_PHY_ADDRESS, PHY_CDCTRL1, BIST_CONT_MODE );
		ETH_WritePHYRegister(DP83848_PHY_ADDRESS, PHY_CR, tmp | BIST_START );//BIST_START

		while(i--);

		//tmp =  ETH_ReadPHYRegister(DP83848_PHY_ADDRESS, PHY_CR);

		if( ETH_ReadPHYRegister(DP83848_PHY_ADDRESS, PHY_CR) & BIST_STATUS == BIST_STATUS )
		{
			rt_kprintf("BIST pass\n");
		}
		else
		{
			uint16_t ctrl;

			ctrl = ETH_ReadPHYRegister(DP83848_PHY_ADDRESS, PHY_CDCTRL1);
			rt_kprintf("BIST faild count =%d\n", BIST_ERROR_COUNT(ctrl) );
		}
		tmp &= ~BIST_START; //Stop BIST 
		ETH_WritePHYRegister(DP83848_PHY_ADDRESS, PHY_CR, tmp);


	} 

	/* Enable MAC and DMA transmission and reception */
	ETH_Start();

	//rt_kprintf("DMASR = 0x%X\n", ETH->DMASR );
//	rt_kprintf("ETH Init\n");

  return RT_EOK;
}