INT_CFG(DM365, INT_EDMA_TC3_ERR, 23, 1, 1, false)
INT_CFG(DM365, INT_PRTCSS, 10, 1, 1, false)
INT_CFG(DM365, INT_EMAC_RXTHRESH, 14, 1, 1, false)
INT_CFG(DM365, INT_EMAC_RXPULSE, 15, 1, 1, false)
INT_CFG(DM365, INT_EMAC_TXPULSE, 16, 1, 1, false)
INT_CFG(DM365, INT_EMAC_MISCPULSE, 17, 1, 1, false)
INT_CFG(DM365, INT_IMX0_ENABLE, 0, 1, 0, false)
INT_CFG(DM365, INT_IMX0_DISABLE, 0, 1, 1, false)
INT_CFG(DM365, INT_HDVICP_ENABLE, 0, 1, 1, false)
INT_CFG(DM365, INT_HDVICP_DISABLE, 0, 1, 0, false)
INT_CFG(DM365, INT_IMX1_ENABLE, 24, 1, 1, false)
INT_CFG(DM365, INT_IMX1_DISABLE, 24, 1, 0, false)
INT_CFG(DM365, INT_NSF_ENABLE, 25, 1, 1, false)
INT_CFG(DM365, INT_NSF_DISABLE, 25, 1, 0, false)
EVT_CFG(DM365, EVT2_ASP_TX, 0, 1, 0, false)
EVT_CFG(DM365, EVT3_ASP_RX, 1, 1, 0, false)
EVT_CFG(DM365, EVT2_VC_TX, 0, 1, 1, false)
EVT_CFG(DM365, EVT3_VC_RX, 1, 1, 1, false)
#endif
};
static u64 dm365_spi0_dma_mask = DMA_BIT_MASK(32);
static struct davinci_spi_platform_data dm365_spi0_pdata = {
.version = SPI_VERSION_1,
.num_chipselect = 2,
.dma_event_q = EVENTQ_3,
.prescaler_limit = 1,
};
MUX_CFG(DM355, MCBSP0_BDX, 3, 0, 1, 1, false) MUX_CFG(DM355, MCBSP0_X, 3, 1, 1, 1, false) MUX_CFG(DM355, MCBSP0_BFSX, 3, 2, 1, 1, false) MUX_CFG(DM355, MCBSP0_BDR, 3, 3, 1, 1, false) MUX_CFG(DM355, MCBSP0_R, 3, 4, 1, 1, false) MUX_CFG(DM355, MCBSP0_BFSR, 3, 5, 1, 1, false) MUX_CFG(DM355, SPI0_SDI, 4, 1, 1, 0, false) MUX_CFG(DM355, SPI0_SDENA0, 4, 0, 1, 0, false) MUX_CFG(DM355, SPI0_SDENA1, 3, 28, 1, 1, false) INT_CFG(DM355, INT_EDMA_CC, 2, 1, 1, false) INT_CFG(DM355, INT_EDMA_TC0_ERR, 3, 1, 1, false) INT_CFG(DM355, INT_EDMA_TC1_ERR, 4, 1, 1, false) EVT_CFG(DM355, EVT8_ASP1_TX, 0, 1, 0, false) EVT_CFG(DM355, EVT9_ASP1_RX, 1, 1, 0, false) EVT_CFG(DM355, EVT26_MMC0_RX, 2, 1, 0, false) MUX_CFG(DM355, VOUT_FIELD, 1, 18, 3, 1, false) MUX_CFG(DM355, VOUT_FIELD_G70, 1, 18, 3, 0, false) MUX_CFG(DM355, VOUT_HVSYNC, 1, 16, 1, 0, false) MUX_CFG(DM355, VOUT_COUTL_EN, 1, 0, 0xff, 0x55, false) MUX_CFG(DM355, VOUT_COUTH_EN, 1, 8, 0xff, 0x55, false) MUX_CFG(DM355, VIN_PCLK, 0, 14, 1, 1, false) MUX_CFG(DM355, VIN_CAM_WEN, 0, 13, 1, 1, false) MUX_CFG(DM355, VIN_CAM_VD, 0, 12, 1, 1, false) MUX_CFG(DM355, VIN_CAM_HD, 0, 11, 1, 1, false) MUX_CFG(DM355, VIN_YIN_EN, 0, 10, 1, 1, false) MUX_CFG(DM355, VIN_CINL_EN, 0, 0, 0xff, 0x55, false)
INT_CFG(DM365, INT_EDMA_TC3_ERR, 23, 1, 1, false)
INT_CFG(DM365, INT_PRTCSS, 10, 1, 1, false)
INT_CFG(DM365, INT_EMAC_RXTHRESH, 14, 1, 1, false)
INT_CFG(DM365, INT_EMAC_RXPULSE, 15, 1, 1, false)
INT_CFG(DM365, INT_EMAC_TXPULSE, 16, 1, 1, false)
INT_CFG(DM365, INT_EMAC_MISCPULSE, 17, 1, 1, false)
INT_CFG(DM365, INT_IMX0_ENABLE, 0, 1, 0, false)
INT_CFG(DM365, INT_IMX0_DISABLE, 0, 1, 1, false)
INT_CFG(DM365, INT_HDVICP_ENABLE, 0, 1, 1, false)
INT_CFG(DM365, INT_HDVICP_DISABLE, 0, 1, 0, false)
INT_CFG(DM365, INT_IMX1_ENABLE, 24, 1, 1, false)
INT_CFG(DM365, INT_IMX1_DISABLE, 24, 1, 0, false)
INT_CFG(DM365, INT_NSF_ENABLE, 25, 1, 1, false)
INT_CFG(DM365, INT_NSF_DISABLE, 25, 1, 0, false)
EVT_CFG(DM365, EVT2_ASP_TX, 0, 1, 0, false)
EVT_CFG(DM365, EVT3_ASP_RX, 1, 1, 0, false)
EVT_CFG(DM365, EVT2_VC_TX, 0, 1, 1, false)
EVT_CFG(DM365, EVT3_VC_RX, 1, 1, 1, false)
EVT_CFG(DM365, EVT18_SPI3_TX, 3, 1, 1, false)
EVT_CFG(DM365, EVT19_SPI3_RX, 4, 1, 1, false)
#endif
};
static u64 dm365_spi0_dma_mask = DMA_BIT_MASK(32);
static struct davinci_spi_platform_data dm365_spi0_pdata = {
.version = SPI_VERSION_1,
.num_chipselect = 2,
.clk_internal = 1,
.cs_hold = 1,