void change_all_power_base_to(unsigned int cluster)
{
	int i;
	int offset = 0;

	if (!soc_is_exynos5410() && !soc_is_exynos5420())
		return;

	if (soc_is_exynos5410())  {
		if (samsung_rev() < EXYNOS5410_REV_1_0) {
			if (cluster == 0)
				offset = 4;
		} else {
			if (cluster != 0)
				offset = 4;
		}
	} else {
		if (cluster)
			offset = 4;
	}

	for (i = 0; i < 4; i++) {
		cpu_boot_info[i].power_base =
			EXYNOS_ARM_CORE_CONFIGURATION(offset + i);
	}
}
Beispiel #2
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void exynos7420_cpu_down(unsigned int cpu_id)
{
	unsigned int phys_cpu = cpu_logical_map(cpu_id);
	unsigned int tmp, core, cluster;
	void __iomem *addr;

	core = MPIDR_AFFINITY_LEVEL(phys_cpu, 0);
	cluster = MPIDR_AFFINITY_LEVEL(phys_cpu, 1);

	addr = EXYNOS_ARM_CORE_CONFIGURATION(core + (4 * cluster));

	tmp = __raw_readl(addr);
	tmp &= ~(EXYNOS_CORE_PWR_EN);
	__raw_writel(tmp, addr);
}
Beispiel #3
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void exynos7420_secondary_up(unsigned int cpu_id)
{
	unsigned int phys_cpu = cpu_logical_map(cpu_id);
	unsigned int tmp, core, cluster;
	void __iomem *addr;

	core = MPIDR_AFFINITY_LEVEL(phys_cpu, 0);
	cluster = MPIDR_AFFINITY_LEVEL(phys_cpu, 1);

	addr = EXYNOS_ARM_CORE_CONFIGURATION(core + (4 * cluster));

	tmp = __raw_readl(addr);
	tmp |= EXYNOS_CORE_INIT_WAKEUP_FROM_LOWPWR | EXYNOS_CORE_PWR_EN;

	__raw_writel(tmp, addr);
}
Beispiel #4
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void __init platform_smp_prepare_cpus(unsigned int max_cpus)
{
	int i;

	if (soc_is_exynos4210() || soc_is_exynos4212() || soc_is_exynos4412())
		scu_enable(scu_base_addr());

	for (i = 1; i < max_cpus; i++) {
		int pwr_offset = 0;

#ifdef CONFIG_ARM_TRUSTZONE
		cpu_boot_info[i].boot_base = S5P_VA_SYSRAM_NS + 0x1C;
#else

		if (soc_is_exynos4210() &&
			(samsung_rev() >= EXYNOS4210_REV_1_1))
			cpu_boot_info[i].boot_base = EXYNOS_INFORM5;
		else
			cpu_boot_info[i].boot_base = S5P_VA_SYSRAM;
#endif
		if (soc_is_exynos4412())
			cpu_boot_info[i].boot_base += (0x4 * i);
		else if (soc_is_exynos5410()) {
			int cluster_id = read_cpuid_mpidr() & 0x100;
			if (samsung_rev() < EXYNOS5410_REV_1_0) {
				if (cluster_id == 0)
					pwr_offset = 4;
			} else {
				if (cluster_id != 0)
					pwr_offset = 4;
			}
		}

		cpu_boot_info[i].power_base =
			EXYNOS_ARM_CORE_CONFIGURATION(i + pwr_offset);
	}
}
Beispiel #5
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/**
 * exynos_cpu_power_up : power up the specified cpu
 * @cpu : the cpu to power up
 *
 * Power up the specified cpu
 */
void exynos_cpu_power_up(int cpu)
{
	pmu_raw_writel(S5P_CORE_LOCAL_PWR_EN,
			EXYNOS_ARM_CORE_CONFIGURATION(cpu));
}
Beispiel #6
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/**
 * exynos_core_power_down : power down the specified cpu
 * @cpu : the cpu to power down
 *
 * Power down the specified cpu. The sequence must be finished by a
 * call to cpu_do_idle()
 *
 */
void exynos_cpu_power_down(int cpu)
{
	pmu_raw_writel(0, EXYNOS_ARM_CORE_CONFIGURATION(cpu));
}