static void exynos_core_option(void) { unsigned int cpu, tmp; for (cpu = 0; cpu < NR_CPUS; cpu++) { tmp = __raw_readl(EXYNOS_ARM_CORE_OPTION(cpu)); tmp |= EXYNOS5_USE_SC_COUNTER; tmp |= EXYNOS5_USE_SC_FEEDBACK; tmp |= EXYNOS7420_USE_SMPEN; __raw_writel(tmp, EXYNOS_ARM_CORE_OPTION(cpu)); } for (cpu = 0; cpu < NR_CPUS; cpu++) { tmp = __raw_readl(EXYNOS7420_ARM_CORE_DURATION(cpu)); tmp &= ~EXYNOS7420_DUR_SCALL; tmp |= (0x1 << EXYNOS7420_DUR_SCALL_SHIFT); __raw_writel(tmp, EXYNOS7420_ARM_CORE_DURATION(cpu)); } }
void exynos_reset_assert_ctrl(bool on) { unsigned int i; unsigned int option; for (i = 0; i < num_possible_cpus(); i++) { option = __raw_readl(EXYNOS_ARM_CORE_OPTION(i)); option = on ? (option | EXYNOS_USE_DELAYED_RESET_ASSERTION) : (option & ~EXYNOS_USE_DELAYED_RESET_ASSERTION); __raw_writel(option, EXYNOS_ARM_CORE_OPTION(i)); } if (soc_is_exynos5410()) { option = __raw_readl(EXYNOS5410_ARM_COMMON_OPTION); option = on ? (option | EXYNOS_USE_DELAYED_RESET_ASSERTION) : (option & ~EXYNOS_USE_DELAYED_RESET_ASSERTION); __raw_writel(option, EXYNOS5410_ARM_COMMON_OPTION); option = __raw_readl(EXYNOS5410_KFC_COMMON_OPTION); option = on ? (option | EXYNOS_USE_DELAYED_RESET_ASSERTION) : (option & ~EXYNOS_USE_DELAYED_RESET_ASSERTION); __raw_writel(option, EXYNOS5410_KFC_COMMON_OPTION); } }
EXYNOS5_TOP_PWR_OPTION, EXYNOS5_TOP_PWR_SYSMEM_OPTION, }; void __iomem *exynos5_list_diable_wfi_wfe[] = { EXYNOS5_FSYS_ARM_OPTION, EXYNOS5_ISP_ARM_OPTION, }; void __iomem *exynos5_list_disable_pmu_reg[] = { EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG, EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG, }; void __iomem *exynos5410_list_feed[] = { EXYNOS_ARM_CORE_OPTION(0), EXYNOS_ARM_CORE_OPTION(1), EXYNOS_ARM_CORE_OPTION(2), EXYNOS_ARM_CORE_OPTION(3), EXYNOS_ARM_CORE_OPTION(4), EXYNOS_ARM_CORE_OPTION(5), EXYNOS_ARM_CORE_OPTION(6), EXYNOS_ARM_CORE_OPTION(7), EXYNOS5410_ARM_COMMON_OPTION, EXYNOS5410_KFC_COMMON_OPTION, EXYNOS5_GSCL_OPTION, EXYNOS5_ISP_OPTION, EXYNOS5410_MFC_OPTION, EXYNOS5410_G3D_OPTION, EXYNOS5410_DISP0_OPTION, EXYNOS5410_DISP1_OPTION,