/* TTI data structures tti_dev TTI device descriptor tti_unit TTI unit descriptor tti_reg TTI register list */ DIB tti_dib = { 0, 0, NULL, NULL, 1, IVCL (TTI), SCB_TTI, { NULL } }; UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE|TT_MODE_8B, 0), TMLN_SPD_9600_BPS }; REG tti_reg[] = { { HRDATAD (BUF, tti_unit.buf, 16, "last data item processed") }, { HRDATAD (CSR, tti_csr, 16, "control/status register") }, { FLDATAD (INT, int_req[IPL_TTI], INT_V_TTI, "interrupt pending flag") }, { FLDATAD (ERR, tti_csr, CSR_V_ERR, "error flag (CSR<15>)") }, { FLDATAD (DONE, tti_csr, CSR_V_DONE, "device done flag (CSR<7>)") }, { FLDATAD (IE, tti_csr, CSR_V_IE, "interrupt enable flag (CSR<6>)") }, { DRDATAD (POS, tti_unit.pos, T_ADDR_W, "number of characters input"), PV_LEFT }, { DRDATAD (TIME, tti_unit.wait, 24, "input polling interval"), PV_LEFT }, { NULL } }; MTAB tti_mod[] = { { TT_MODE, TT_MODE_7B, "7b", "7B", NULL, NULL, NULL, "Set 7 bit mode" }, { TT_MODE, TT_MODE_8B, "8b", "8B", NULL, NULL, NULL, "Set 8 bit mode" }, { MTAB_XTD|MTAB_VDV, 0, "VECTOR", NULL, NULL, &show_vec, NULL, "Display interrupt vector" }, { 0 } };
extern int32 con_halt (int32 code, int32 cc); /* TTI data structures tti_dev TTI device descriptor tti_unit TTI unit descriptor tti_reg TTI register list */ UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE|TT_MODE_8B, 0), TMLN_SPD_9600_BPS }; REG tti_reg[] = { { HRDATAD (RXDB, tti_buf, 16, "last data item processed") }, { HRDATAD (RXCS, tti_csr, 16, "control/status register") }, { FLDATAD (INT, tti_int, 0, "interrupt pending flag") }, { FLDATAD (DONE, tti_csr, CSR_V_DONE, "device done flag (CSR<7>)") }, { FLDATAD (IE, tti_csr, CSR_V_IE, "interrupt enable flag (CSR<6>)") }, { DRDATAD (POS, tti_unit.pos, T_ADDR_W, "number of characters input"), PV_LEFT }, { DRDATAD (TIME, tti_unit.wait, 24, "input polling interval"), PV_LEFT }, { NULL } }; MTAB tti_mod[] = { { TT_MODE, TT_MODE_7B, "7b", "7B", NULL, NULL, NULL, "Set 7 bit mode" }, { TT_MODE, TT_MODE_8B, "8b", "8B", NULL, NULL, NULL, "Set 8 bit mode" }, { 0 } }; DEVICE tti_dev = { "TTI", &tti_unit, tti_reg, tti_mod,
/* TTI data structures tti_dev TTI device descriptor tti_unit TTI unit descriptor tti_reg TTI register list */ DIB tti_dib = { 0, 0, NULL, NULL, 1, IVCL (TTI), SCB_TTI, { NULL } }; UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE|TT_MODE_8B, 0), 0 }; REG tti_reg[] = { { HRDATAD (BUF, tti_unit.buf, 16, "last data item processed") }, { HRDATAD (CSR, tti_csr, 16, "control/status register") }, { FLDATAD (INT, int_req[IPL_TTI], INT_V_TTI, "interrupt pending flag") }, { FLDATAD (ERR, tti_csr, CSR_V_ERR, "error flag (CSR<15>)") }, { FLDATAD (DONE, tti_csr, CSR_V_DONE, "device done flag (CSR<7>)") }, { FLDATAD (IE, tti_csr, CSR_V_IE, "interrupt enable flag (CSR<6>)") }, { DRDATAD (POS, tti_unit.pos, T_ADDR_W, "number of characters input"), PV_LEFT }, { DRDATAD (TIME, tti_unit.wait, 24, "input polling interval"), PV_LEFT }, { NULL } }; MTAB tti_mod[] = { { TT_MODE, TT_MODE_7B, "7b", "7B", NULL }, { TT_MODE, TT_MODE_8B, "8b", "8B", NULL }, { MTAB_XTD|MTAB_VDV, 0, "VECTOR", NULL, NULL, &show_vec, NULL }, { 0 } };
/* TTI data structures tti_dev TTI device descriptor tti_unit TTI unit descriptor tti_reg TTI register list tti_mod TTI modifiers list */ DIB tti_dib = { DEV_TTI, 1, { &tti } }; UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE|TT_MODE_KSR, 0), SERIAL_IN_WAIT }; REG tti_reg[] = { { ORDATAD (BUF, tti_unit.buf, 8, "last data item processed") }, { FLDATAD (DONE, dev_done, INT_V_TTI, "device done flag") }, { FLDATAD (ENABLE, int_enable, INT_V_TTI, "interrupt enable flag") }, { FLDATAD (INT, int_req, INT_V_TTI, "interrupt pending flag") }, { DRDATAD (POS, tti_unit.pos, T_ADDR_W, "number of characters input"), PV_LEFT }, { DRDATAD (TIME, tti_unit.wait, 24, "input polling interval (if 0, the keyboard is polled synchronously with the clock)"), PV_LEFT+REG_NZ }, { NULL } }; MTAB tti_mod[] = { { TT_MODE, TT_MODE_KSR, "KSR", "KSR", &tty_set_mode }, { TT_MODE, TT_MODE_7B, "7b", "7B", &tty_set_mode }, { TT_MODE, TT_MODE_8B, "8b", "8B", &tty_set_mode }, { TT_MODE, TT_MODE_7P, "7b", NULL, NULL }, { MTAB_XTD|MTAB_VDV, 0, "DEVNO", NULL, NULL, &show_dev, NULL }, { 0 } };
{ UDATA (&rk_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+ UNIT_ROABLE, RK_SIZE) }, { UDATA (&rk_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+ UNIT_ROABLE, RK_SIZE) }, { UDATA (&rk_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+ UNIT_ROABLE, RK_SIZE) }, { UDATA (&rk_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+ UNIT_ROABLE, RK_SIZE) } }; REG rk_reg[] = { { ORDATAD (RKSTA, rk_sta, 12, "status") }, { ORDATAD (RKCMD, rk_cmd, 12, "disk command") }, { ORDATAD (RKDA, rk_da, 12, "disk address") }, { ORDATAD (RKMA, rk_ma, 12, "current memory address") }, { FLDATAD (BUSY, rk_busy, 0, "control busy flag") }, { FLDATAD (INT, int_req, INT_V_RK, "interrupt pending flag") }, { DRDATAD (STIME, rk_swait, 24, "seek time, per cylinder"), PV_LEFT }, { DRDATAD (RTIME, rk_rwait, 24, "rotational delay"), PV_LEFT }, { FLDATAD (STOP_IOE, rk_stopioe, 0, "stop on I/O error") }, { ORDATA (DEVNUM, rk_dib.dev, 6), REG_HRO }, { NULL } }; MTAB rk_mod[] = { { UNIT_HWLK, 0, "write enabled", "WRITEENABLED", NULL }, { UNIT_HWLK, UNIT_HWLK, "write locked", "LOCKED", NULL }, { MTAB_XTD|MTAB_VDV, 0, "DEVNO", "DEVNO", &set_dev, &show_dev, NULL }, { 0 } };
{ GRDATAD (CADL, cmdadl, DEV_RDX, 16, 0, "command packet low address or count") }, { GRDATAD (CADH, cmdadh, DEV_RDX, 16, 0, "command packet high address") }, { GRDATAD (CLNT, cmdlnt, DEV_RDX, 16, 0, "command packet length") }, { GRDATAD (MHDR, msghdr, DEV_RDX, 16, 0, "message packet header") }, { GRDATAD (MRFC, msgrfc, DEV_RDX, 16, 0, "message packet residual frame count") }, { GRDATAD (MXS0, msgxs0, DEV_RDX, 16, 0, "message packet extended status 0") }, { GRDATAD (MXS1, msgxs1, DEV_RDX, 16, 0, "message packet extended status 1") }, { GRDATAD (MXS2, msgxs2, DEV_RDX, 16, 0, "message packet extended status 2") }, { GRDATAD (MXS3, msgxs3, DEV_RDX, 16, 0, "message packet extended status 3") }, { GRDATAD (MSX4, msgxs4, DEV_RDX, 16, 0, "message packet extended status 4") }, { GRDATAD (WADL, wchadl, DEV_RDX, 16, 0, "write char packet low address") }, { GRDATAD (WADH, wchadh, DEV_RDX, 16, 0, "write char packet high address") }, { GRDATAD (WLNT, wchlnt, DEV_RDX, 16, 0, "write char packet length") }, { GRDATAD (WOPT, wchopt, DEV_RDX, 16, 0, "write char packet options") }, { GRDATAD (WXOPT, wchxopt, DEV_RDX, 16, 0, "write char packet extended options") }, { FLDATAD (INT, IREQ (TS), INT_V_TS, "interrupt pending") }, { FLDATAD (ATTN, ts_qatn, 0, "attention message pending") }, { FLDATAD (BOOT, ts_bcmd, 0, "boot request pending") }, { FLDATAD (OWNC, ts_ownc, 0, "if set, tape owns command buffer") }, { FLDATAD (OWNM, ts_ownm, 0, "if set, tape owns message buffer") }, { DRDATAD (TIME, ts_time, 24, "delay"), PV_LEFT + REG_NZ }, { DRDATAD (POS, ts_unit.pos, T_ADDR_W, "position"), PV_LEFT + REG_RO }, { GRDATA (DEVADDR, ts_dib.ba, DEV_RDX, 32, 0), REG_HRO }, { GRDATA (DEVVEC, ts_dib.vec, DEV_RDX, 16, 0), REG_HRO }, { NULL } }; MTAB ts_mod[] = { { MTUF_WLK, 0, "write enabled", "WRITEENABLED", NULL, NULL, NULL, "Write enable tape drive" }, { MTUF_WLK, MTUF_WLK, "write locked", "LOCKED",
tti_dev TTI device descriptor tti_unit TTI unit descriptor tti_reg TTI register list */ DIB tti_dib = { IOBA_TTI, IOLN_TTI, &tti_rd, &tti_wr, 1, IVCL (TTI), VEC_TTI, { NULL } }; UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE, 0), SERIAL_IN_WAIT }; REG tti_reg[] = { { HRDATAD (BUF, tti_unit.buf, 8, "last data item processed") }, { HRDATAD (CSR, tti_csr, 16, "control/status register") }, { FLDATAD (INT, IREQ (TTI), INT_V_TTI, "interrupt pending flag") }, { FLDATAD (DONE, tti_csr, CSR_V_DONE, "device done flag (CSR<7>)") }, { FLDATAD (ERR, tti_csr, CSR_V_ERR, "device error flag (CSR<15>)") }, { FLDATAD (IE, tti_csr, CSR_V_IE, "interrupt enable flag (CSR<6>)") }, { DRDATAD (POS, tti_unit.pos, T_ADDR_W, "number of characters input"), PV_LEFT }, { DRDATAD (TIME, tti_unit.wait, 24, "input polling interval"), PV_LEFT }, { NULL } }; MTAB tti_mod[] = { { TT_MODE, TT_MODE_UC, "UC", "UC", &tty_set_mode }, { TT_MODE, TT_MODE_7B, "7b", "7B", &tty_set_mode }, { TT_MODE, TT_MODE_8B, "8b", "8B", &tty_set_mode }, { TT_MODE, TT_MODE_7P, "7b", NULL, NULL }, { MTAB_XTD|MTAB_VDV, 0, "ADDRESS", NULL, NULL, &show_addr, NULL },
DIB ptr_dib = { IOBA_AUTO, IOLN_PTR, &ptr_rd, &ptr_wr, 1, IVCL (PTR), VEC_AUTO, { NULL } }; UNIT ptr_unit = { UDATA (&ptr_svc, UNIT_SEQ+UNIT_ATTABLE+UNIT_ROABLE, 0), SERIAL_IN_WAIT }; extern DEVICE ptr_dev; REG ptr_reg[] = { { GRDATAD (BUF, ptr_unit.buf, DEV_RDX, 8, 0, "last data item processed") }, { GRDATAD (CSR, ptr_csr, DEV_RDX, 16, 0, "control/status register") }, { FLDATAD (INT, int_req, INT_V_PTR, "interrupt pending flag") }, { FLDATAD (ERR, ptr_csr, CSR_V_ERR, "error flag (CSR<15>)") }, { FLDATAD (BUSY, ptr_csr, CSR_V_BUSY, "busy flag (CSR<11>)") }, { FLDATAD (DONE, ptr_csr, CSR_V_DONE, "device done flag (CSR<7>)") }, { FLDATAD (IE, ptr_csr, CSR_V_IE, "interrupt enable flag (CSR<6>)") }, { DRDATAD (POS, ptr_unit.pos, T_ADDR_W, "position in the input file"), PV_LEFT }, { DRDATAD (TIME, ptr_unit.wait, 24, "time from I/O initiation to interrupt"), PV_LEFT }, { FLDATAD (STOP_IOE, ptr_stopioe, 0, "stop on I/O error") }, { FLDATA (DEVDIS, ptr_dev.flags, DEV_V_DIS), REG_HRO }, { GRDATA (DEVADDR, ptr_dib.ba, DEV_RDX, 32, 0), REG_HRO }, { GRDATA (DEVVEC, ptr_dib.vec, DEV_RDX, 16, 0), REG_HRO }, { NULL } }; MTAB ptr_mod[] = { { MTAB_XTD|MTAB_VDV, 0, "ADDRESS", NULL,
UNIT_BUFABLE|UNIT_MUSTBUF|(RS04_DTYPE << UNIT_V_DTYPE), RS04_SIZE) }, { UDATA (&rs_svc, UNIT_FIX|UNIT_ATTABLE|UNIT_DISABLE|UNIT_AUTO| UNIT_BUFABLE|UNIT_MUSTBUF|(RS04_DTYPE << UNIT_V_DTYPE), RS04_SIZE) } }; REG rs_reg[] = { { BRDATAD (CS1, rscs1, DEV_RDX, 16, RS_NUMDR, "control/status 1") }, { BRDATAD (DA, rsda, DEV_RDX, 16, RS_NUMDR, "track/sector") }, { BRDATAD (DS, rsds, DEV_RDX, 16, RS_NUMDR, "drive status") }, { BRDATAD (ER, rser, DEV_RDX, 16, RS_NUMDR, "error status") }, { BRDATAD (MR, rsmr, DEV_RDX, 16, RS_NUMDR, "maint register") }, { BRDATAD (WLKS, rswlk, DEV_RDX, 6, RS_NUMDR, "write lock switches") }, { DRDATAD (TIME, rs_wait, 24, "rotate time"), REG_NZ + PV_LEFT }, { URDATAD (CAPAC, rs_unit[0].capac, 10, T_ADDR_W, 0, RS_NUMDR, PV_LEFT | REG_HRO, "Capacity") }, { FLDATAD (STOP_IOE, rs_stopioe, 0, "stop on I/O error") }, { NULL } }; MTAB rs_mod[] = { { MTAB_XTD|MTAB_VDV, 0, "MASSBUS", NULL, NULL, &mba_show_num, NULL, "Display Massbus Address" }, { UNIT_WLK, 0, "write enabled", "WRITEENABLED", NULL, NULL, NULL, "Write enable disk drive" }, { UNIT_WLK, UNIT_WLK, "write lockable", "LOCKED", NULL, NULL, NULL, "Write lock disk drive" }, { (UNIT_DTYPE|UNIT_ATT), (RS03_DTYPE << UNIT_V_DTYPE) + UNIT_ATT, "RS03", NULL, NULL }, { (UNIT_DTYPE|UNIT_ATT), (RS04_DTYPE << UNIT_V_DTYPE) + UNIT_ATT, "RS04", NULL, NULL }, { (UNIT_AUTO|UNIT_DTYPE|UNIT_ATT), (RS03_DTYPE << UNIT_V_DTYPE), "RS03", NULL, NULL }, { (UNIT_AUTO|UNIT_DTYPE|UNIT_ATT), (RS04_DTYPE << UNIT_V_DTYPE), "RS04", NULL, NULL },
*/ DIB uba_dib = { TR_UBA, 0, &uba_rdreg, &uba_wrreg, 0, 0 }; UNIT uba_unit = { UDATA (&uba_svc, 0, 0) }; REG uba_reg[] = { { HRDATAD (IPL14, int_req[0], 32, "IPL 14 Interrupt Request"), REG_RO }, { HRDATAD (IPL15, int_req[1], 32, "IPL 15 Interrupt Request"), REG_RO }, { HRDATAD (IPL16, int_req[2], 32, "IPL 16 Interrupt Request"), REG_RO }, { HRDATAD (IPL17, int_req[3], 32, "IPL 17 Interrupt Request"), REG_RO }, { HRDATAD (CNFR, uba_cnf, 32, "config register") }, { HRDATAD (CR, uba_cr, 32, "control register") }, { HRDATAD (SR, uba_sr, 32, "status register") }, { HRDATAD (DR, uba_dr, 32, "diagnostic control register") }, { FLDATAD (INT, uba_int, 0, "UBA interrupt") }, { FLDATAD (NEXINT, nexus_req[IPL_UBA], TR_UBA, "") }, { FLDATAD (AIIP, uba_aiip, 0, "adapter interrupt in progress") }, { FLDATAD (UIIP, uba_uiip, 0, "Unibus interrupt in progress") }, { HRDATAD (FMER, uba_fmer, 32, "failing map register") }, { HRDATAD (FUBAR, uba_fubar, 32, "failing Unibus address") }, { HRDATAD (BRSVR0, uba_svr[0], 32, "diagnostic register 0") }, { HRDATAD (BRSVR1, uba_svr[1], 32, "diagnostic register 1") }, { HRDATAD (BRSVR2, uba_svr[2], 32, "diagnostic register 2") }, { HRDATAD (BRSVR3, uba_svr[3], 32, "diagnostic register 3") }, { HRDATAD (BRRVR4, uba_rvr[0], 32, "vector register 0") }, { HRDATAD (BRRVR5, uba_rvr[1], 32, "vector register 1") }, { HRDATAD (BRRVR6, uba_rvr[2], 32, "vector register 2") }, { HRDATAD (BRRVR7, uba_rvr[3], 32, "vector register 3") }, { BRDATAD (DPR, uba_dpr, 16, 32, 16, "number data paths") }, { BRDATAD (MAP, uba_map, 16, 32, 496, "Unibus map registers") },
ptr_dev PTR device descriptor ptr_unit PTR unit descriptor ptr_reg PTR register list */ DIB ptr_dib = { DEV_PTR, 1, { &ptr } }; UNIT ptr_unit = { UDATA (&ptr_svc, UNIT_SEQ+UNIT_ATTABLE+UNIT_ROABLE, 0), SERIAL_IN_WAIT }; REG ptr_reg[] = { { ORDATAD (BUF, ptr_unit.buf, 8, "last data item processed") }, { FLDATAD (DONE, dev_done, INT_V_PTR, "device done flag") }, { FLDATAD (ENABLE, int_enable, INT_V_PTR, "interrupt enable flag") }, { FLDATAD (INT, int_req, INT_V_PTR, "interrupt pending flag") }, { DRDATAD (POS, ptr_unit.pos, T_ADDR_W, "position in the input file"), PV_LEFT }, { DRDATAD (TIME, ptr_unit.wait, 24, "time from I/O initiation to interrupt"), PV_LEFT }, { FLDATAD (STOP_IOE, ptr_stopioe, 0, "stop on I/O error") }, { NULL } }; MTAB ptr_mod[] = { { MTAB_XTD|MTAB_VDV, 0, "DEVNO", NULL, NULL, &show_dev }, { 0 } }; DEVICE ptr_dev = { "PTR", &ptr_unit, ptr_reg, ptr_mod,
/* Type 62 LPT data structures lp62_dev LPT device descriptor lp62_unit LPT unit lp62_reg LPT register list */ DIB lp62_dib = { DEV_LPT, 2, &lp62_iors, { &lp62_65, &lp62_66 } }; UNIT lp62_unit = { UDATA (&lp62_svc, UNIT_SEQ+UNIT_ATTABLE+UNIT_TEXT, 0), SERIAL_OUT_WAIT }; REG lp62_reg[] = { { ORDATAD (BUF, lp62_unit.buf, 8, "last data item processed") }, { FLDATAD (INT, int_hwre[API_LPT], INT_V_LPT, "interrupt pending flag") }, { FLDATAD (DONE, int_hwre[API_LPT], INT_V_LPT, "device done flag") }, { FLDATAD (SPC, int_hwre[API_LPTSPC], INT_V_LPTSPC, "spacing done flag") }, { DRDATAD (BPTR, lp62_bp, 6, "print buffer pointer") }, { ORDATA (STATE, lp62_spc, 6), REG_HRO }, { FLDATA (OVRPR, lp62_ovrpr, 0), REG_HRO }, { DRDATAD (POS, lp62_unit.pos, T_ADDR_W, "position in the output file"), PV_LEFT }, { DRDATAD (TIME, lp62_unit.wait, 24, "time from I/O initiation to interrupt"), PV_LEFT }, { FLDATAD (STOP_IOE, lp62_stopioe, 0, "stop on I/O error") }, { BRDATAD (LBUF, lp62_buf, 8, 8, LP62_BSIZE, "line buffer") }, { ORDATA (DEVNO, lp62_dib.dev, 6), REG_HRO }, { NULL } }; MTAB lp62_mod[] = { { MTAB_XTD|MTAB_VDV, 0, "DEVNO", "DEVNO", &set_devno, &show_devno },
{ UDATA (&rp_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE, RP02_SIZE) }, { UDATA (&rp_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE, RP02_SIZE) }, { UDATA (&rp_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE, RP02_SIZE) }, { UDATA (&rp_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE, RP02_SIZE) }, { UDATA (&rp_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE, RP02_SIZE) }, { UDATA (&rp_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE, RP02_SIZE) }, { UDATA (&rp_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE, RP02_SIZE) } }; REG rp_reg[] = { { ORDATAD (STA, rp_sta, 18, "status A") }, { ORDATAD (STB, rp_stb, 18, "status B") }, { ORDATAD (DA, rp_da, 18, "disk address") }, { ORDATAD (MA, rp_ma, 18, "current memory address") }, { ORDATAD (WC, rp_wc, 18, "word count") }, { FLDATAD (INT, int_hwre[API_RP], INT_V_RP, "interrupt pending flag") }, { FLDATAD (BUSY, rp_busy, 0, "control busy flag") }, { FLDATAD (STOP_IOE, rp_stopioe, 0, "stop on I/O error") }, { DRDATAD (STIME, rp_swait, 24, "seek time per cylinder"), PV_LEFT }, { DRDATAD (RTIME, rp_rwait, 24, "rotational delay"), PV_LEFT }, { ORDATA (DEVNO, rp_dib.dev, 6), REG_HRO }, { ORDATA (APIVEC, api_vec[API_RP][INT_V_RP], 6), REG_HRO }, { NULL } }; MTAB rp_mod[] = { { UNIT_RP03, 0, "RP02", "RP02", &rp_set_size }, { UNIT_RP03, UNIT_RP03, "RP03", "RP03", &rp_set_size }, { UNIT_WLK, 0, "write enabled", "WRITEENABLED", NULL }, { UNIT_WLK, UNIT_WLK, "write locked", "LOCKED", NULL }, { MTAB_XTD|MTAB_VDV, 0, "DEVNO", "DEVNO", &set_devno, &show_devno },
*/ DIB mba0_dib = { TR_MBA0, 0, &mba_rdreg, &mba_wrreg, 0, NVCL (MBA0) }; UNIT mba0_unit = { UDATA (NULL, 0, 0) }; REG mba0_reg[] = { { HRDATAD (CNFR, mba_cnf[0], 32, "config register") }, { HRDATAD (CR, mba_cr[0], 4, "control register") }, { HRDATAD (SR, mba_sr[0], 32, "status register") }, { HRDATAD (VA, mba_va[0], 17, "virtual address register") }, { HRDATAD (BC, mba_bc[0], 16, "byte count register") }, { HRDATAD (DR, mba_dr[0], 32, "diag register") }, { HRDATAD (SMR, mba_dr[0], 32, "sel map register") }, { BRDATAD (MAP, mba_map[0], 16, 32, MBA_NMAPR, "map registers") }, { FLDATAD (NEXINT, nexus_req[IPL_MBA0], TR_MBA0, "nexus interrupt request") }, { NULL } }; MTAB mba0_mod[] = { { MTAB_XTD|MTAB_VDV, TR_MBA0, "NEXUS", NULL, NULL, &show_nexus, NULL, "Display nexus" }, { 0 } }; DIB mba1_dib = { TR_MBA1, 0, &mba_rdreg, &mba_wrreg, 0, NVCL (MBA1) }; UNIT mba1_unit = { UDATA (NULL, 0, 0) }; MTAB mba1_mod[] = { { MTAB_XTD|MTAB_VDV, TR_MBA1, "NEXUS", NULL,
/* PTR data structures ptr_dev PTR device descriptor ptr_unit PTR unit ptr_reg PTR register list */ UNIT ptr_unit = { UDATA (&ptr_svc, UNIT_SEQ+UNIT_ATTABLE+UNIT_ROABLE, 0), SERIAL_IN_WAIT }; REG ptr_reg[] = { { ORDATAD (BUF, ptr_unit.buf, 18, "last data item processed") }, { FLDATA (UC, ptr_uc, UC_V) }, { FLDATAD (DONE, iosta, IOS_V_PTR, "device done flag") }, { FLDATAD (RPLS, cpls, CPLS_V_PTR, "return restart pulse flag") }, { ORDATA (HOLD, ptr_hold, 9), REG_HRO }, { ORDATA (STATE, ptr_state, 5), REG_HRO }, { FLDATA (WAIT, ptr_wait, 0), REG_HRO }, { DRDATAD (POS, ptr_unit.pos, T_ADDR_W, "position in the input file"), PV_LEFT }, { DRDATAD (TIME, ptr_unit.wait, 24, "time from I/O initiation to interrupt"), PV_LEFT }, { DRDATA (LEADER, ptr_leader, 6), REG_HRO }, { FLDATAD (STOP_IOE, ptr_stopioe, 0, "stop on I/O error") }, { DRDATA (SBSLVL, ptr_sbs, 4), REG_HRO }, { NULL } }; MTAB ptr_mod[] = { { MTAB_XTD|MTAB_VDV, 0, "SBSLVL", "SBSLVL", &dev_set_sbs, &dev_show_sbs, (void *) &ptr_sbs },