void ConstantLengthDoublePulseCycleProtocolBase::Decode(short state, unsigned int duration)
{
    if (state==LOW)
    {
		unsigned int pulsecycleduration = duration + _highpulseduration ;
		if (WithinExpectedDeviation( pulsecycleduration , (_shortperiods+_longperiods) * _timeperiodduration ,  _timeperiodduration / 8) )
		{
			if (_prev_pulsecycleduration!=0)
			{
				if (WithinExpectedDeviation( _prev_pulsecycleduration , (_shortperiods+_longperiods) * _timeperiodduration ,  _timeperiodduration / 8) )
				{
					FlipBits(decoder_bitbuffer , decoder_bitbufferlength, decoder_bitpos);
				} else
				{
					AddBit( decoder_bitbuffer , decoder_bitbufferlength, decoder_bitpos , false);				
					pulsecycleduration = 0;
				}
			}
			// Are there more bits in the buffer than is expected for this protocol?
			if (decoder_bitpos > GetBitstreamLength()) 
			{ 
				ShiftFirstBitOut(decoder_bitbuffer , decoder_bitbufferlength, decoder_bitpos);
			}
		} else if (WithinExpectedDeviation( pulsecycleduration , ( _shortperiods + _shortperiods ) * _timeperiodduration ,  _timeperiodduration / 8) )
		{
			if (_prev_pulsecycleduration!=0)
			{
				if (WithinExpectedDeviation( _prev_pulsecycleduration , ( _shortperiods + _shortperiods ) * _timeperiodduration ,  _timeperiodduration / 8) ) 
				{
					FlipBits(decoder_bitbuffer , decoder_bitbufferlength, decoder_bitpos);
				} else
				{
					AddBit( decoder_bitbuffer , decoder_bitbufferlength, decoder_bitpos , true);			
					pulsecycleduration = 0;
				}
			}
			// Are there more bits in the buffer than is expected for this protocol?
			if (decoder_bitpos > GetBitstreamLength()) 
			{ 
				ShiftFirstBitOut(decoder_bitbuffer , decoder_bitbufferlength, decoder_bitpos);
			}
		} else 
		{
			DecodeBitstream(_highpulseduration, duration);
			ResetDecoder();
			pulsecycleduration = 0;
		}
		_prev_pulsecycleduration = pulsecycleduration;
    } else if (state==HIGH)
	{
		_highpulseduration = duration;
	}
}
Beispiel #2
0
//=============================================================
// performs a reverse-bit copy of a DPoly into a new CDPoly
static CDPoly BitRevCopy(const DPoly & p)
{
  size_t n = p.Degree();
  size_t b = log2(n);
  CDPoly a(n);

  for (size_t k = 0; k < n; ++k)
    a[FlipBits(k,b)] = DComplex(p.Get(k));

  return a;
}
Beispiel #3
0
    /// Polls the inbound socket until the message queue is empty. Also resends any timed out reliable messages.
    void NetMessageManager::ProcessMessages()
    {
        PROFILE (NetMessageManager_ProcessMessages);
        if (!connection)
            return;

        if (!ResendQueueIsEmpty())
            ProcessResendQueue();

        // Process network messages for max. 0.1 seconds, to prevent lack of rendering/mainloop execution during heavy processing
        static const double MAX_PROCESS_TIME = 0.1;
        boost::timer timer;

        PROFILE(NetMessageManager_WhilePacketsAvailable);
        while(connection->PacketsAvailable() && timer.elapsed() < MAX_PROCESS_TIME)
        {
            const int cMaxPayload = 2048;
            std::vector<uint8_t> data(cMaxPayload, 0);
            int numBytes = connection->ReceiveBytes(&data[0], cMaxPayload);
            if (numBytes == 0)
                break;

            data.resize(numBytes);

            tick_t now = GetCurrentClockTime();
            lastHeardSince = (double)(now - lastHeardSinceTick) / GetCurrentClockFreq() * 1000;
            lastHeardSinceTick = now;

#ifdef PROTOCOL_STRESS_TEST
            const int numDuplications = 10;
            const double bitErrorRate = 0.05;
            for(int i = 0; i < numDuplications; ++i)
            {
#endif
                HandleInboundBytes(data);
#ifdef PROTOCOL_STRESS_TEST
                FlipBits(data, (int)ceil(data.size() * bitErrorRate));
            }
#endif
        }
        if (!connection->Open())
            connection.reset();

        // To keep memory footprint down and to defend against memory attacks, keep the list of seen sequence numbers to a fixed size.
        const size_t cMaxSeqNumMemorySize = 300;
        while(receivedSequenceNumbers.size() > cMaxSeqNumMemorySize)
            receivedSequenceNumbers.erase(receivedSequenceNumbers.begin()); // We remove from the front to guarantee the smallest(oldest) are removed first.

        // Acknowledge all the new accumulated packets that the server sent as reliable.
        SendPendingACKs();

        ManagePingSends();
    }
Beispiel #4
0
int main()
{
	volatile int i;
    StatusRegOnRead SR;
    STField		ST;
    phy_cmd_type0 pct;
    phy_cmd_type t;

    init_platform();

    DisableModuleHandlersAndTranfers();

    // Setare asteptare -- 0 adica exista un singur tact de delay intre cand incepe sa scrie si cand incepe sa inregistreze intrarile
    SetDelayRegisterNoDelay();

    ResetMemoryToZero();
//    xil_printf("struct : %08X\n", t.uint32_Data);

	// let's check if we are in dormant state : lanes are in EIDL state = RDS( 0 ) / RDTS ( 0 )
	 SR.uint32_Data = module[2];
	 ST.uint8_Data = SR.fields.ST;
	 xil_printf("1) Status reg( 2 ) : Amplitude(%x) Lock(%x) Pack(%x) Err(%x) RDS(%x) RDTS(%x)\n", ST.fields.Amplitude, ST.fields.Lock, ST.fields.Pack, ST.fields.Err, ST.fields.RDS, ST.fields.RDTS  );
	
    ////////////////////////////////////////////////////////////////
    //setup CFG register to set physical layers in EIDL state - 0x0067E09F
    // !! this will be visible only once for each time you reset VTE !!!
    {
		t.uint32_Data = 0;
		t.fields.TDM = 3;
		t.fields.TDRM = 3;
		t.fields.MODE = 1;
		t.fields.CT_PHY_CMD = 0;
		t.fields.CT_Tx = 0;	//EIDL
		t.fields.HOST_MODE = 1;
		t.fields.BUSIF16 = 1;
		t.fields.DET_EN = 1;
		t.fields.RCLKOE = 1;
		t.fields.RCLKTRMEN = 1;
		t.fields.CNFG_ALIGN_EN = 1;
		t.fields.CNFG_LOCK_PERIOD = 0;
		t.fields.CNFG_LOCK_MARGIN = 3;
		module[2]= t.uint32_Data;	//setup CFG register to set physical layers in EIDL state - 0x0067E09F

		Sleep( 100 );
		 //read the status of the lanes
		 SR.uint32_Data = module[2];
		 ST.uint8_Data = SR.fields.ST;
	//     xil_printf("1) Status reg( 2 ) RDM: %x %x %x %x\n", SR.fields.RDM,SR.fields.RDTM,SR.fields.ST ,SR.fields.b0  );
		 xil_printf("1) Status reg( 2 ) : Amplitude(%x) Lock(%x) Pack(%x) Err(%x) RDS(%x) RDTS(%x)\n", ST.fields.Amplitude, ST.fields.Lock, ST.fields.Pack, ST.fields.Err, ST.fields.RDS, ST.fields.RDTS  );
    }
    ////////////////////////////////////////////////////////////////

    ////////////////////////////////////////////////////////////////
    //setup CFG register to set physical layers in STB.L state - 0x0067E09F
    {
		t.uint32_Data = 0;
		t.fields.TDM = 3;
		t.fields.TDRM = 3;
		t.fields.MODE = 1;
		t.fields.CT_PHY_CMD = 0;
		t.fields.CT_Tx = 2; //STB.L
		t.fields.HOST_MODE = 1;
		t.fields.BUSIF16 = 1;
		t.fields.DET_EN = 1;
		t.fields.RCLKOE = 1;
		t.fields.RCLKTRMEN = 1;
		t.fields.CNFG_ALIGN_EN = 1;
		t.fields.CNFG_LOCK_PERIOD = 3;
		t.fields.CNFG_LOCK_MARGIN = 3;
		module[2]= t.uint32_Data;	//setup CFG register to set physical layers in STB.L state

		Sleep( 100 );

		 //read the status of the lanes
		 SR.uint32_Data = module[2];
		 ST.uint8_Data = SR.fields.ST;
		 xil_printf("1) Status reg( 2 ) : Amplitude(%x) Lock(%x) Pack(%x) Err(%x) RDS(%x) RDTS(%x)\n", ST.fields.Amplitude, ST.fields.Lock, ST.fields.Pack, ST.fields.Err, ST.fields.RDS, ST.fields.RDTS  );
    }
    ////////////////////////////////////////////////////////////////
	
    ////////////////////////////////////////////////////////////////
    //setup CFG register to set physical layers in VLD state - 0x0067E09F
    {
		t.uint32_Data = 0;
		t.fields.TDM = 3;
		t.fields.TDRM = 3;
		t.fields.MODE = 1;
		t.fields.CT_PHY_CMD = 0;
		t.fields.CT_Tx = 3; //STB.L
		t.fields.HOST_MODE = 1;
		t.fields.BUSIF16 = 1;
		t.fields.DET_EN = 1;
		t.fields.RCLKOE = 1;
		t.fields.RCLKTRMEN = 1;
		t.fields.CNFG_ALIGN_EN = 1;
		t.fields.CNFG_LOCK_PERIOD = 3;
		t.fields.CNFG_LOCK_MARGIN = 3;
		module[2]= t.uint32_Data;	//setup CFG register to set physical layers in VLD state

		Sleep( 100 );

		 //read the status of the lanes
		 SR.uint32_Data = module[2];
		 ST.uint8_Data = SR.fields.ST;
		 xil_printf("1) Status reg( 2 ) : Amplitude(%x) Lock(%x) Pack(%x) Err(%x) RDS(%x) RDTS(%x)\n", ST.fields.Amplitude, ST.fields.Lock, ST.fields.Pack, ST.fields.Err, ST.fields.RDS, ST.fields.RDTS  );
    }
    ////////////////////////////////////////////////////////////////

 	//Sleep( 400 );

 	DisableDataTransferEnablePINS();

 	i = module[1];
 	xil_printf("delay reg( 1 ) : %04x\n", i );
 	Sleep( 100 );

 /*	Sleep( 100 );
 	pct.uint32_Data = 0;
	pct.fields.TDM = 3;
	pct.fields.TDRM = 3;
	pct.fields.MODE = 1;
	pct.fields.HOST_MODE = 1;
	pct.fields.BUSIF16 = 1;
	pct.fields.DET_EN = 1;
	pct.fields.RCLKOE = 1;
	pct.fields.RCLKTRMEN = 1;
	pct.fields.CNFG_ALIGN_EN = 1;
	pct.fields.CNFG_LOCK_PERIOD = 3;
	pct.fields.CNFG_LOCK_MARGIN = 3;
 	for(pct.fields.CT=0;pct.fields.CT<=255;pct.fields.CT++)
 	{
 		//Send out Sync symbol - wait till UHSII device responds with sync byte
		module[2]=pct.uint32_Data;
		Sleep(100);

		//read the new status of the lanes
		SR.uint32_Data = module[2];

		{
			CTFieldMode0 	CT[4];
			STField			ST[4];
			
			xil_printf("\n");
			CT[0].uint8_Data = pct.fields.CT;
			CT[1].fields.CT_PHY_CMD = FlipBits( CT[0].fields.CT_PHY_CMD, 4 );
			CT[1].fields.CT_Tx = FlipBits( CT[0].fields.CT_Tx, 2 );
			CT[1].fields.CT_Rx = FlipBits( CT[0].fields.CT_Rx, 2 );
			CT[2].uint8_Data = FlipBits( pct.fields.CT, 8 );
			CT[3].fields.CT_PHY_CMD = FlipBits( CT[2].fields.CT_PHY_CMD, 4 );
			CT[3].fields.CT_Tx = FlipBits( CT[2].fields.CT_Tx, 2 );
			CT[3].fields.CT_Rx = FlipBits( CT[2].fields.CT_Rx, 2 );
			xil_printf("CT = %d - %x - CMD = %x Tx = %x Rx = %x\n", pct.fields.CT, pct.fields.CT, CT[0].fields.CT_PHY_CMD, CT[0].fields.CT_Tx, CT[0].fields.CT_Rx );
			xil_printf("CT = %d - %x - CMD = %x Tx = %x Rx = %x\n", pct.fields.CT, pct.fields.CT, CT[1].fields.CT_PHY_CMD, CT[1].fields.CT_Tx, CT[1].fields.CT_Rx );
			xil_printf("CT = %d - %x - CMD = %x Tx = %x Rx = %x\n", pct.fields.CT, pct.fields.CT, CT[2].fields.CT_PHY_CMD, CT[2].fields.CT_Tx, CT[2].fields.CT_Rx );
			xil_printf("CT = %d - %x - CMD = %x Tx = %x Rx = %x\n", pct.fields.CT, pct.fields.CT, CT[3].fields.CT_PHY_CMD, CT[3].fields.CT_Tx, CT[3].fields.CT_Rx );
			
			xil_printf("ST: %x %x %x %x\n", SR.fields.RDM, SR.fields.RDTM, SR.fields.ST ,SR.fields.b0  );
			
			ST[0].uint8_Data = SR.fields.ST;
			ST[1].uint8_Data = ST[0].uint8_Data;
			ST[1].fields.RDS = FlipBits( ST[0].fields.RDS, 2 );
			ST[1].fields.RDTS = FlipBits( ST[0].fields.RDTS, 2 );
			ST[2].uint8_Data = FlipBits( ST[0].uint8_Data, 8 );
			ST[3].uint8_Data = ST[2].uint8_Data;
			ST[3].fields.RDS = FlipBits( ST[2].fields.RDS, 2 );
			ST[3].fields.RDTS = FlipBits( ST[2].fields.RDTS, 2 );
			xil_printf("ST : Amplitude(%x) Lock(%x) Pack(%x) Err(%x) RDS(%x) RDTS(%x)\n", ST[0].fields.Amplitude, ST[0].fields.Lock, ST[0].fields.Pack, ST[0].fields.Err, ST[0].fields.RDS, ST[0].fields.RDTS  );
			xil_printf("ST : Amplitude(%x) Lock(%x) Pack(%x) Err(%x) RDS(%x) RDTS(%x)\n", ST[1].fields.Amplitude, ST[1].fields.Lock, ST[1].fields.Pack, ST[1].fields.Err, ST[1].fields.RDS, ST[1].fields.RDTS  );
			xil_printf("ST : Amplitude(%x) Lock(%x) Pack(%x) Err(%x) RDS(%x) RDTS(%x)\n", ST[2].fields.Amplitude, ST[2].fields.Lock, ST[2].fields.Pack, ST[2].fields.Err, ST[2].fields.RDS, ST[2].fields.RDTS  );
			xil_printf("ST : Amplitude(%x) Lock(%x) Pack(%x) Err(%x) RDS(%x) RDTS(%x)\n", ST[3].fields.Amplitude, ST[3].fields.Lock, ST[3].fields.Pack, ST[3].fields.Err, ST[3].fields.RDS, ST[3].fields.RDTS  );
			
			if( ( CT[0].fields.CT_Tx == ST[0].fields.RDS && CT[0].fields.CT_Rx == ST[0].fields.RDTS )
				|| ( CT[0].fields.CT_Tx == ST[0].fields.RDTS && CT[0].fields.CT_Rx == ST[0].fields.RDS )

				|| ( CT[1].fields.CT_Tx == ST[1].fields.RDTS && CT[1].fields.CT_Rx == ST[1].fields.RDS )
				|| ( CT[1].fields.CT_Tx == ST[1].fields.RDTS && CT[1].fields.CT_Rx == ST[1].fields.RDS )

				|| ( CT[2].fields.CT_Tx == ST[2].fields.RDTS && CT[2].fields.CT_Rx == ST[2].fields.RDS )
				|| ( CT[2].fields.CT_Tx == ST[2].fields.RDTS && CT[2].fields.CT_Rx == ST[2].fields.RDS )

				|| ( CT[3].fields.CT_Tx == ST[3].fields.RDTS && CT[3].fields.CT_Rx == ST[3].fields.RDS )
				|| ( CT[3].fields.CT_Tx == ST[3].fields.RDTS && CT[3].fields.CT_Rx == ST[3].fields.RDS ) )
					xil_printf( "This is science !\n");
				
		}
 	}/**/

// 	EnableModuleHandlersAndTranfers();
 	module[3]=0xBCBFBCBF;
 	Sleep(100);
 	//read the new status of the lanes
 	SR.uint32_Data = module[2];
 	xil_printf("4) Status reg( 2 ) RDM: %x %x %x %x\n", SR.fields.RDM,SR.fields.RDTM,SR.fields.ST ,SR.fields.b0  );
 	xil_printf("5) data in: %x\n", module[3] );
 	SynPacket Synp;
 #if 0
 	Synp.fields.com = LSS_COM;
 	Synp.fields.syn = LSS_SYN0;
 	data[0] = FlipBits(  Synp.uint16_Data | ( Synp.uint16_Data << 16 ), 32 );
 //	data[0] = Synp.uint16_Data | ( Synp.uint16_Data << 16 );
 	count[0] = 20;
 	cfg[0] = t.uint32_Data;
 #endif
 #if 0
 	Synp.fields.com = LSS_COM;
 	Synp.fields.syn = LSS_SYN0;
 	data[0] = Synp.uint16_Data | ( Synp.uint16_Data << 16 );
 	count[0] = 20;
 	cfg[0] = t.uint32_Data;
 #endif
 #if 0
 	Synp.fields.com = FlipBits( LSS_COM, 8 );
 	Synp.fields.syn = FlipBits( LSS_SYN0, 8 );
 	data[0] = Synp.uint16_Data | ( Synp.uint16_Data << 16 );
 	count[0] = 20;
 	cfg[0] = t.uint32_Data;
 #endif
 #if 0
 	Synp.fields.com = FlipBits( LSS_COM, 8 );
 	Synp.fields.syn = FlipBits( LSS_SYN0, 8 );
 	data[0] = Synp.uint16_Data | ( Synp.uint16_Data << 16 );
 	count[0] = 20;
 	cfg[0] = 0x04585634;
 #endif

 //	#include "SetData.h"
/*
 //	xil_printf("Data 1 is %x\n", data[1]  );
 	//start writing
 //	module[0] = 0x1F;	// enable handlers and transfers
 	EnableModuleHandlersAndTranfers();
 //	module[0] = 0xFFFFFFFF;

 	//wait until write is finished
 	int AntiDeadlockCounter = 10000000;
 	while (module[0] != 0x0000001E && AntiDeadlockCounter > 0 )
 		AntiDeadlockCounter--;

 	if( AntiDeadlockCounter > 0 )
 		xil_printf("there is hope");

 	xil_printf("count_read = %x\n", count_read[0]);
 	xil_printf("st_read = %x\n", st_read[0]);
 	xil_printf("data_read = %x\n", data_read[0]);

 	xil_printf("data = %x %x %x\n", data[0], data[1], data[2]);
 	xil_printf("count = %x %x %x\n", count[0], count[1], count[2]);

 	//read the new status of the lanes
 	SR.uint32_Data = module[2];
 	xil_printf("3) Status reg( 2 ) RDM: %x %x %x %x\n", SR.fields.RDM,SR.fields.RDTM,SR.fields.ST ,SR.fields.b0  );
*/
    Sleep( 1000 );
    return 0;
}