int s5p6442_get_index(void)
{
unsigned long clk_div0;
unsigned long armClkRatio;
unsigned int d0ClkRatio;
unsigned int d1ClkRatio;
unsigned int p0ClkRatio;
unsigned int p1ClkRatio;
unsigned int a2MClkRatio;
int index = 0;
u32 size;
u32 (*cpu_clk_tab)[10];
cpu_clk_tab = s5p_cpu_clk_tab[S5P6442_FREQ_TAB];
clk_div0 = __raw_readl(S5P_CLK_DIV0);
if(S5P6442_FREQ_TAB == 1){
armClkRatio = GET_DIV(clk_div0, S5P_CLKDIV0_APLL)- 1;
d0ClkRatio = GET_DIV(clk_div0, S5P_CLKDIV0_D0CLK) - 1;
d1ClkRatio = GET_DIV(clk_div0, S5P_CLKDIV0_D1CLK) - 1;
p0ClkRatio = GET_DIV(clk_div0, S5P_CLKDIV0_P0CLK) - 1;
p1ClkRatio = GET_DIV(clk_div0, S5P_CLKDIV0_P1CLK) - 1;
size = s5p_cpu_clk_tab_size();
for(index = 0 ; index < size ; index++) {
if((cpu_clk_tab[index][3]== armClkRatio)&&
(cpu_clk_tab[index][4] == d0ClkRatio) &&
(cpu_clk_tab[index][5] == p0ClkRatio) &&
(cpu_clk_tab[index][6] == d1ClkRatio) &&
(cpu_clk_tab[index][7] == p1ClkRatio)){
return index;
}
}
}
else {
armClkRatio = GET_DIV(clk_div0, S5P_CLKDIV0_APLL)- 1;
d0ClkRatio = GET_DIV(clk_div0, S5P_CLKDIV0_D0CLK) - 1;
d1ClkRatio = GET_DIV(clk_div0, S5P_CLKDIV0_D1CLK) - 1;
p0ClkRatio = GET_DIV(clk_div0, S5P_CLKDIV0_P0CLK) - 1;
p1ClkRatio = GET_DIV(clk_div0, S5P_CLKDIV0_P1CLK) - 1;
size = s5p_cpu_clk_tab_size();
for(index = 0 ; index < size ; index++) {
if(cpu_clk_tab[index][5]== armClkRatio) {
if((cpu_clk_tab[index][6] == d0ClkRatio) &&
(cpu_clk_tab[index][7] == p0ClkRatio) &&
(cpu_clk_tab[index][8] == d1ClkRatio) &&
(cpu_clk_tab[index][9] == p1ClkRatio))
return index;
}
}
}
return -1;
}
unsigned long s5p_fclk_get_rate(void)
{
unsigned long apll_con;
unsigned long clk_div0;
unsigned long ret;
apll_con = __raw_readl(S5P_APLL_CON);
clk_div0 = __raw_readl(S5P_CLK_DIV0);
ret = s5p64xx_get_pll(INIT_XTAL, apll_con, S5P64XX_PLL_APLL);
return (ret / GET_DIV(clk_div0, S5P_CLKDIV0_APLL));
}
void __init_or_cpufreq s5pc100_setup_clocks(void)
{
struct clk *xtal_clk;
unsigned long xtal;
unsigned long armclk;
unsigned long hclkd0;
unsigned long hclk;
unsigned long pclkd0;
unsigned long pclk;
unsigned long apll;
unsigned long mpll;
unsigned long hpll;
unsigned long epll;
unsigned int ptr;
u32 clkdiv0, clkdiv1;
printk(KERN_DEBUG "%s: registering clocks\n", __func__);
clkdiv0 = __raw_readl(S5PC1XX_CLK_DIV0);
clkdiv1 = __raw_readl(S5PC1XX_CLK_DIV1);
printk(KERN_DEBUG "%s: clkdiv0 = %08x, clkdiv1 = %08x\n",
__func__, clkdiv0, clkdiv1);
xtal_clk = clk_get(NULL, "xtal");
BUG_ON(IS_ERR(xtal_clk));
xtal = clk_get_rate(xtal_clk);
clk_put(xtal_clk);
printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
apll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC1XX_APLL_CON));
mpll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC1XX_MPLL_CON));
epll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC1XX_EPLL_CON));
hpll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC100_HPLL_CON));
printk(KERN_INFO "S5PC100: PLL settings, A=%ld, M=%ld, E=%ld, H=%ld\n",
apll, mpll, epll, hpll);
armclk = apll / GET_DIV(clkdiv0, S5PC1XX_CLKDIV0_APLL);
armclk = armclk / GET_DIV(clkdiv0, S5PC100_CLKDIV0_ARM);
hclkd0 = armclk / GET_DIV(clkdiv0, S5PC100_CLKDIV0_D0);
pclkd0 = hclkd0 / GET_DIV(clkdiv0, S5PC100_CLKDIV0_PCLKD0);
hclk = mpll / GET_DIV(clkdiv1, S5PC100_CLKDIV1_D1);
pclk = hclk / GET_DIV(clkdiv1, S5PC100_CLKDIV1_PCLKD1);
printk(KERN_INFO "S5PC100: ARMCLK=%ld, HCLKD0=%ld, PCLKD0=%ld, HCLK=%ld, PCLK=%ld\n",
armclk, hclkd0, pclkd0, hclk, pclk);
clk_fout_apll.rate = apll;
clk_fout_mpll.rate = mpll;
clk_fout_epll.rate = epll;
clk_fout_apll.rate = apll;
clk_h.rate = hclk;
clk_p.rate = pclk;
for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++)
s5pc1xx_set_clksrc(init_parents[ptr]);
}
void __init_or_cpufreq s3c6400_setup_clocks(void)
{
struct clk *xtal_clk;
unsigned long xtal;
unsigned long fclk;
unsigned long hclk;
unsigned long hclk2;
unsigned long pclk;
unsigned long epll;
unsigned long apll;
unsigned long mpll;
unsigned int ptr;
u32 clkdiv0;
printk(KERN_DEBUG "%s: registering clocks\n", __func__);
clkdiv0 = __raw_readl(S3C_CLK_DIV0);
printk(KERN_DEBUG "%s: clkdiv0 = %08x\n", __func__, clkdiv0);
xtal_clk = clk_get(NULL, "xtal");
BUG_ON(IS_ERR(xtal_clk));
xtal = clk_get_rate(xtal_clk);
clk_put(xtal_clk);
printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
/* For now assume the mux always selects the crystal */
clk_ext_xtal_mux.parent = xtal_clk;
epll = s3c6400_get_epll(xtal);
mpll = s3c6400_get_pll(xtal, __raw_readl(S3C_MPLL_CON));
apll = s3c6400_get_pll(xtal, __raw_readl(S3C_APLL_CON));
fclk = mpll;
printk(KERN_INFO "S3C64XX: PLL settings, A=%ld, M=%ld, E=%ld\n",
apll, mpll, epll);
if(__raw_readl(S3C64XX_OTHERS) & S3C64XX_OTHERS_SYNCMUXSEL_SYNC) {
/* Synchronous mode */
hclk2 = apll / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK2);
} else {
/* Asynchronous mode */
hclk2 = mpll / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK2);
}
hclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK);
pclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_PCLK);
printk(KERN_INFO "S3C64XX: HCLK2=%ld, HCLK=%ld, PCLK=%ld\n",
hclk2, hclk, pclk);
clk_fout_mpll.rate = mpll;
clk_fout_epll.rate = epll;
clk_fout_apll.rate = apll;
clk_h2.rate = hclk2;
clk_h.rate = hclk;
clk_p.rate = pclk;
clk_f.rate = fclk;
for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++)
s3c_set_clksrc(init_parents[ptr], true);
for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
s3c_set_clksrc(&clksrcs[ptr], true);
}