/*
************************************************************************************************************
*
* function
*
* name :
*
* parmeters :
*
* return :
*
* note :
*
*
************************************************************************************************************
*/
static void gic_cpuif_init(void)
{
uint i;
writel(0, GIC_CPU_IF_CTRL);
/*
* Deal with the banked PPI and SGI interrupts - disable all
* PPI interrupts, ensure all SGI interrupts are enabled.
*/
writel(0xffff0000, GIC_CLR_EN(0));
writel(0x0000ffff, GIC_SET_EN(0));
/* Set priority on PPI and SGI interrupts */
for (i=0; i<16; i+=4)
{
writel(0xa0a0a0a0, GIC_SGI_PRIO(i>>2));
}
for (i=16; i<32; i+=4)
{
writel(0xa0a0a0a0, GIC_PPI_PRIO((i-16)>>2));
}
writel(0xf0, GIC_INT_PRIO_MASK);
writel(1, GIC_CPU_IF_CTRL);
return ;
}
/*
************************************************************************************************************
*
* function
*
* name :
*
* parmeters :
*
* return :
*
* note :
*
*
************************************************************************************************************
*/
static void gic_cpuif_init(void)
{
writel(0, GIC_CPU_IF_CTRL);
/*
* Deal with the banked PPI and SGI interrupts - disable all
* PPI interrupts, ensure all SGI interrupts are enabled.
*/
writel(0xffffffff, GIC_CON_IGRP(0));
writel(0xffff0000, GIC_CLR_EN(0));
writel(0x0000ffff, GIC_SET_EN(0));
writel(0xf0, GIC_INT_PRIO_MASK);
writel(0xf, GIC_CPU_IF_CTRL);
return ;
}
s32 irq_disable(u32 irq_no)
{
u32 base;
u32 base_os;
u32 bit_os;
if (irq_no >= GIC_IRQ_NUM) {
//printk("irq NO.(%d) > GIC_IRQ_NUM(%d) !!\n", irq_no, GIC_IRQ_NUM);
return -1;
}
base_os = irq_no >> 5; // ³ý32
base = GIC_CLR_EN(base_os);
bit_os = irq_no & 0x1f; // %32
sr32_aw(base, bit_os, 1, 1);
return 0;
}
