int board_init (void) {
DECLARE_GLOBAL_DATA_PTR;
volatile unsigned int tmp;
mc9328sid = SIDR;
GPCR = 0x000003AB; /* I/O pad driving strength */
/* MX1_CS1U = 0x00000A00; */ /* SRAM initialization */
/* MX1_CS1L = 0x11110601; */
MPCTL0 = 0x04632410; /* setting for 150 MHz MCU PLL CLK */
/* set FCLK divider 1 (i.e. FCLK to MCU PLL CLK) and
* BCLK divider to 2 (i.e. BCLK to 48 MHz)
*/
CSCR = 0xAF000403;
CSCR |= 0x00200000; /* Trigger the restart bit(bit 21) */
CSCR &= 0xFFFF7FFF; /* Program PRESC bit(bit 15) to 0 to divide-by-1 */
/* setup cs4 for cs8900 ethernet */
CS4U = 0x00000F00; /* Initialize CS4 for CS8900 ethernet */
CS4L = 0x00001501;
GIUS(0) &= 0xFF3FFFFF;
GPR(0) &= 0xFF3FFFFF;
tmp = *(unsigned int *)(0x1500000C);
tmp = *(unsigned int *)(0x1500000C);
SetAsynchMode();
gd->bd->bi_arch_number = MACH_TYPE_MX1ADS;
gd->bd->bi_boot_params = 0x08000100; /* adress of boot parameters */
icache_enable();
dcache_enable();
/* set PERCLKs */
PCDR = 0x00000055; /* set PERCLKS */
/* PERCLK3 is only used by SSI so the SSI driver can set it any value it likes
* PERCLK1 and PERCLK2 are shared so DO NOT change it in any other place
* all sources selected as normal interrupt
*/
/* MX1_INTTYPEH = 0;
MX1_INTTYPEL = 0;
*/
return 0;
}
static int
imx21_gpio_irq_type(unsigned int _irq, unsigned int type)
{
unsigned int irq_type = 0, irq, reg, bit;
irq = _irq - IRQ_GPIOA(0);
reg = irq >> 5;
bit = 1 << (irq % 32);
if (type == IRQT_PROBE) {
/* Don't mess with enabled GPIOs using preconfigured edges or
GPIOs set to alternate function during probe */
/* TODO: support probe */
// if ((GPIO_IRQ_rising_edge[idx] | GPIO_IRQ_falling_edge[idx]) &
// GPIO_bit(gpio))
// return 0;
// if (GAFR(gpio) & (0x3 << (((gpio) & 0xf)*2)))
// return 0;
// type = __IRQT_RISEDGE | __IRQT_FALEDGE;
}
GIUS(reg) |= bit;
DDIR(reg) &= ~(bit);
DEBUG_IRQ("setting type of irq %d to ", _irq);
if (type & __IRQT_RISEDGE) {
DEBUG_IRQ("rising edges\n");
irq_type = 0x0;
}
if (type & __IRQT_FALEDGE) {
DEBUG_IRQ("falling edges\n");
irq_type = 0x1;
}
if (type & __IRQT_LOWLVL) {
DEBUG_IRQ("low level\n");
irq_type = 0x3;
}
if (type & __IRQT_HIGHLVL) {
DEBUG_IRQ("high level\n");
irq_type = 0x2;
}
if (irq % 32 < 16) {
ICR1(reg) = (ICR1(reg) & ~(0x3 << ((irq % 16) * 2))) |
(irq_type << ((irq % 16) * 2));
} else {
ICR2(reg) = (ICR2(reg) & ~(0x3 << ((irq % 16) * 2))) |
(irq_type << ((irq % 16) * 2));
}
return 0;
}
int board_early_init_f(void)
{
mc9328sid = SIDR;
GPCR = 0x000003AB; /* I/O pad driving strength */
/* MX1_CS1U = 0x00000A00; */ /* SRAM initialization */
/* MX1_CS1L = 0x11110601; */
MPCTL0 = 0x04632410; /* setting for 150 MHz MCU PLL CLK */
/* set FCLK divider 1 (i.e. FCLK to MCU PLL CLK) and
* BCLK divider to 2 (i.e. BCLK to 48 MHz)
*/
CSCR = 0xAF000403;
CSCR |= 0x00200000; /* Trigger the restart bit(bit 21) */
CSCR &= 0xFFFF7FFF; /* Program PRESC bit(bit 15) to 0 to divide-by-1 */
/* setup cs4 for cs8900 ethernet */
CS4U = 0x00000F00; /* Initialize CS4 for CS8900 ethernet */
CS4L = 0x00001501;
GIUS (0) &= 0xFF3FFFFF;
GPR (0) &= 0xFF3FFFFF;
readl(0x1500000C);
readl(0x1500000C);
SetAsynchMode ();
icache_enable ();
dcache_enable ();
/* set PERCLKs */
PCDR = 0x00000055; /* set PERCLKS */
/* PERCLK3 is only used by SSI so the SSI driver can set it any value it likes
* PERCLK1 and PERCLK2 are shared so DO NOT change it in any other place
* all sources selected as normal interrupt
*/
/* MX1_INTTYPEH = 0;
MX1_INTTYPEL = 0;
*/
return 0;
}
