//*****************************************************************************
//
// Configure EPI0 in SDRAM mode. The EPI memory space is setup using an a
// simple C array. This example shows how to read and write to an SDRAM card
// using the EPI bus in SDRAM mode.
//
//*****************************************************************************
int
main(void)
{
uint32_t ui32Val, ui32Freq, ui32SysClock;
//
// Set the clocking to run at 120MHz from the PLL.
// TODO: Update this call to set the system clock frequency your
// application requires.
//
ui32SysClock = SysCtlClockFreqSet((SYSCTL_OSC_INT | SYSCTL_USE_PLL |
SYSCTL_CFG_VCO_320), 120000000);
//
// Set up the serial console to use for displaying messages. This is
// just for this example program and is not needed for EPI operation.
//
InitConsole();
//
// Display the setup on the console.
//
UARTprintf("EPI SDRAM Mode ->\n");
UARTprintf(" Type: SDRAM\n");
UARTprintf(" Starting Address: 0x%08x\n", SDRAM_MAPPING_ADDRESS);
UARTprintf(" End Address: 0x%08x\n",
(SDRAM_MAPPING_ADDRESS + SDRAM_END_ADDRESS));
UARTprintf(" Data: 16-bit\n");
UARTprintf(" Size: 64MB (32Meg x 16bits)\n\n");
//
// The EPI0 peripheral must be enabled for use.
//
SysCtlPeripheralEnable(SYSCTL_PERIPH_EPI0);
//
// For this example EPI0 is used with multiple pins on PortA, B, C, G, H,
// K, L, M and N. The actual port and pins used may be different on your
// part, consult the data sheet for more information.
// TODO: Update based upon the EPI pin assignment on your target part.
//
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOG);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOK);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOL);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOM);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPION);
//
// This step configures the internal pin muxes to set the EPI pins for use
// with EPI. Please refer to the datasheet for more information about pin
// muxing. Note that EPI0S27:20 are not used for the EPI SDRAM
// implementation.
// TODO: Update this section based upon the EPI pin assignment on your
// target part.
//
//
// EPI0S4 ~ EPI0S7: C4 ~ 7
//
ui32Val = HWREG(GPIO_PORTC_BASE + GPIO_O_PCTL);
ui32Val &= 0x0000FFFF;
ui32Val |= 0xFFFF0000;
HWREG(GPIO_PORTC_BASE + GPIO_O_PCTL) = ui32Val;
//
// EPI0S8 ~ EPI0S9: A6 ~ 7
//
ui32Val = HWREG(GPIO_PORTA_BASE + GPIO_O_PCTL);
ui32Val &= 0x00FFFFFF;
ui32Val |= 0xFF000000;
HWREG(GPIO_PORTA_BASE + GPIO_O_PCTL) = ui32Val;
//
// EPI0S10 ~ EPI0S11: G0 ~ 1
//
ui32Val = HWREG(GPIO_PORTG_BASE + GPIO_O_PCTL);
ui32Val &= 0xFFFFFF00;
ui32Val |= 0x000000FF;
HWREG(GPIO_PORTG_BASE + GPIO_O_PCTL) = ui32Val;
//
// EPI0S12 ~ EPI0S15: M0 ~ 3
//
ui32Val = HWREG(GPIO_PORTM_BASE + GPIO_O_PCTL);
ui32Val &= 0xFFFF0000;
ui32Val |= 0x0000FFFF;
HWREG(GPIO_PORTM_BASE + GPIO_O_PCTL) = ui32Val;
//
// EPI0S16 ~ EPI0S19: L0 ~ 3
//
ui32Val = HWREG(GPIO_PORTL_BASE + GPIO_O_PCTL);
ui32Val &= 0xFFFF0000;
ui32Val |= 0x0000FFFF;
HWREG(GPIO_PORTL_BASE + GPIO_O_PCTL) = ui32Val;
//
// EPI0S28 : B3
//
ui32Val = HWREG(GPIO_PORTB_BASE + GPIO_O_PCTL);
ui32Val &= 0xFFFF0FFF;
ui32Val |= 0x0000F000;
HWREG(GPIO_PORTB_BASE + GPIO_O_PCTL) = ui32Val;
//
// EPI0S29 ~ EPI0S30: N2 ~ 3
//
ui32Val = HWREG(GPIO_PORTN_BASE + GPIO_O_PCTL);
ui32Val &= 0xFFFF00FF;
ui32Val |= 0x0000FF00;
HWREG(GPIO_PORTN_BASE + GPIO_O_PCTL) = ui32Val;
//
// EPI0S00 ~ EPI0S03, EPI0S31 : K0 ~ 3, K5
//
ui32Val = HWREG(GPIO_PORTK_BASE + GPIO_O_PCTL);
ui32Val &= 0xFF0F0000;
ui32Val |= 0x00F0FFFF;
HWREG(GPIO_PORTK_BASE + GPIO_O_PCTL) = ui32Val;
//
// Configure the GPIO pins for EPI mode. All the EPI pins require 8mA
// drive strength in push-pull operation. This step also gives control of
// pins to the EPI module.
//
GPIOPinTypeEPI(GPIO_PORTA_BASE, EPI_PORTA_PINS);
GPIOPinTypeEPI(GPIO_PORTB_BASE, EPI_PORTB_PINS);
GPIOPinTypeEPI(GPIO_PORTC_BASE, EPI_PORTC_PINS);
GPIOPinTypeEPI(GPIO_PORTG_BASE, EPI_PORTG_PINS);
GPIOPinTypeEPI(GPIO_PORTK_BASE, EPI_PORTK_PINS);
GPIOPinTypeEPI(GPIO_PORTL_BASE, EPI_PORTL_PINS);
GPIOPinTypeEPI(GPIO_PORTM_BASE, EPI_PORTM_PINS);
GPIOPinTypeEPI(GPIO_PORTN_BASE, EPI_PORTN_PINS);
//
// Is our current system clock faster than we can drive the SDRAM clock?
//
if(ui32SysClock > 60000000)
{
//
// Yes. Set the EPI clock to half the system clock.
//
EPIDividerSet(EPI0_BASE, 1);
}
else
{
//
// With a system clock of 60MHz or lower, we can drive the SDRAM at
// the same rate so set the divider to 0.
//
EPIDividerSet(EPI0_BASE, 0);
}
//
// Sets the usage mode of the EPI module. For this example we will use
// the SDRAM mode to talk to the external 64MB SDRAM daughter card.
//
EPIModeSet(EPI0_BASE, EPI_MODE_SDRAM);
//
// Keep the compiler happy by setting a default value for the frequency
// flag.
//
ui32Freq = g_psSDRAMFreq[NUM_SDRAM_FREQ - 1].ui32FreqFlag;
//
// Examine the system clock frequency to determine how to set the SDRAM
// controller's frequency flag.
//
for(ui32Val = 0; ui32Val < NUM_SDRAM_FREQ; ui32Val++)
{
//
// Is the system clock frequency above the break point in the table?
//
if(ui32SysClock >= g_psSDRAMFreq[ui32Val].ui32SysClock)
{
//
// Yes - remember the frequency flag to use and exit the loop.
//
ui32Freq = g_psSDRAMFreq[ui32Val].ui32FreqFlag;
break;
}
}
//
// Configure the SDRAM mode. We configure the SDRAM according to our core
// clock frequency. We will use the normal (or full power) operating
// state which means we will not use the low power self-refresh state.
// Set the SDRAM size to 64MB with a refresh interval of 1024 clock ticks.
//
EPIConfigSDRAMSet(EPI0_BASE, (ui32Freq | EPI_SDRAM_FULL_POWER |
EPI_SDRAM_SIZE_512MBIT), 1024);
//
// Set the address map. The EPI0 is mapped from 0x60000000 to 0x01FFFFFF.
// For this example, we will start from a base address of 0x60000000 with
// a size of 256MB. Although our SDRAM is only 64MB, there is no 64MB
// aperture option so we pick the next larger size.
//
EPIAddressMapSet(EPI0_BASE, EPI_ADDR_RAM_SIZE_256MB | EPI_ADDR_RAM_BASE_6);
//
// Wait for the SDRAM wake-up to complete by polling the SDRAM
// initialization sequence bit. This bit is true when the SDRAM interface
// is going through the initialization and false when the SDRAM interface
// it is not in a wake-up period.
//
while(HWREG(EPI0_BASE + EPI_O_STAT) & EPI_STAT_INITSEQ)
{
}
//
// Set the EPI memory pointer to the base of EPI memory space. Note that
// g_pui16EPISdram is declared as volatile so the compiler should not
// optimize reads out of the memory. With this pointer, the memory space
// is accessed like a simple array.
//
g_pui16EPISdram = (uint16_t *)0x60000000;
//
// Read the initial data in SDRAM, and display it on the console.
//
UARTprintf(" SDRAM Initial Data:\n");
UARTprintf(" Mem[0x6000.0000] = 0x%4x\n",
g_pui16EPISdram[SDRAM_START_ADDRESS]);
UARTprintf(" Mem[0x6000.0001] = 0x%4x\n",
g_pui16EPISdram[SDRAM_START_ADDRESS + 1]);
UARTprintf(" Mem[0x603F.FFFE] = 0x%4x\n",
g_pui16EPISdram[SDRAM_END_ADDRESS - 1]);
UARTprintf(" Mem[0x603F.FFFF] = 0x%4x\n\n",
g_pui16EPISdram[SDRAM_END_ADDRESS]);
//
// Display what writes we are doing on the console.
//
UARTprintf(" SDRAM Write:\n");
UARTprintf(" Mem[0x6000.0000] <- 0xabcd\n");
UARTprintf(" Mem[0x6000.0001] <- 0x1234\n");
UARTprintf(" Mem[0x603F.FFFE] <- 0xdcba\n");
UARTprintf(" Mem[0x603F.FFFF] <- 0x4321\n\n");
//
// Write to the first 2 and last 2 address of the SDRAM card. Since the
// SDRAM card is word addressable, we will write words.
//
g_pui16EPISdram[SDRAM_START_ADDRESS] = 0xabcd;
g_pui16EPISdram[SDRAM_START_ADDRESS + 1] = 0x1234;
g_pui16EPISdram[SDRAM_END_ADDRESS - 1] = 0xdcba;
g_pui16EPISdram[SDRAM_END_ADDRESS] = 0x4321;
//
// Read back the data you wrote, and display it on the console.
//
UARTprintf(" SDRAM Read:\n");
UARTprintf(" Mem[0x6000.0000] = 0x%4x\n",
g_pui16EPISdram[SDRAM_START_ADDRESS]);
UARTprintf(" Mem[0x6000.0001] = 0x%4x\n",
g_pui16EPISdram[SDRAM_START_ADDRESS + 1]);
UARTprintf(" Mem[0x603F.FFFE] = 0x%4x\n",
g_pui16EPISdram[SDRAM_END_ADDRESS - 1]);
UARTprintf(" Mem[0x603F.FFFF] = 0x%4x\n\n",
g_pui16EPISdram[SDRAM_END_ADDRESS]);
//
// Check the validity of the data.
//
if((g_pui16EPISdram[SDRAM_START_ADDRESS] == 0xabcd) &&
(g_pui16EPISdram[SDRAM_START_ADDRESS + 1] == 0x1234) &&
(g_pui16EPISdram[SDRAM_END_ADDRESS - 1] == 0xdcba) &&
(g_pui16EPISdram[SDRAM_END_ADDRESS] == 0x4321))
{
//
// Read and write operations were successful. Return with no errors.
//
UARTprintf("Read and write to external SDRAM was successful!\n");
return(0);
}
//
// Display on the console that there was an error.
//
UARTprintf("Read and/or write failure!");
UARTprintf(" Check if your SDRAM card is plugged in.");
//
// Read and/or write operations were unsuccessful. Wait in while(1) loop
// for debugging.
//
while(1)
{
}
}
//*****************************************************************************
//
// Configure EPI0 in SDRAM mode. The EPI memory space is setup using an a
// simple C array. This example shows how to read and write to an SDRAM card
// using the EPI bus in SDRAM mode.
//
//*****************************************************************************
void
sdram_init(void)
{
unsigned long ulClk, ulNsPerTick, ulConfig, ulRefresh;
//
// Display the setup on the console.
//
// UARTprintf("EPI SDRAM Mode ->\n");
// UARTprintf(" Type: SDRAM\n");
// UARTprintf(" Starting Address: 0x6000.0000\n");
// UARTprintf(" End Address: 0x603F.FFFF\n");
// UARTprintf(" Data: 16-bit\n");
// UARTprintf(" Size: 8MB (4Meg x 16bits)\n\n");
//
// The EPI0 peripheral must be enabled for use.
//
SysCtlPeripheralEnable(SYSCTL_PERIPH_EPI0);
//
// For this example EPI0 is used with multiple pins on PortC, E, F, G, H,
// and J. The actual port and pins used may be different on your part,
// consult the data sheet for more information.
// TODO: change this to whichever GPIO port you are using.
//
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOE);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOG);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOH);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOJ);
//
// This step configures the internal pin muxes to set the EPI pins for use
// with EPI. This step is only required because the default function of
// these pins may not be to function in EPI mode. Please reference the
// datasheet for more information about pin muxing. Note that EPI0S27:20
// are not used for the EPI SDRAM implementation.
// TODO: change this to select the port/pin you are using.
//
GPIOPinConfigure(GPIO_PH3_EPI0S0);
GPIOPinConfigure(GPIO_PH2_EPI0S1);
GPIOPinConfigure(GPIO_PC4_EPI0S2);
GPIOPinConfigure(GPIO_PC5_EPI0S3);
GPIOPinConfigure(GPIO_PC6_EPI0S4);
GPIOPinConfigure(GPIO_PC7_EPI0S5);
GPIOPinConfigure(GPIO_PH0_EPI0S6);
GPIOPinConfigure(GPIO_PH1_EPI0S7);
GPIOPinConfigure(GPIO_PE0_EPI0S8);
GPIOPinConfigure(GPIO_PE1_EPI0S9);
GPIOPinConfigure(GPIO_PH4_EPI0S10);
GPIOPinConfigure(GPIO_PH5_EPI0S11);
GPIOPinConfigure(GPIO_PF4_EPI0S12);
GPIOPinConfigure(GPIO_PG0_EPI0S13);
GPIOPinConfigure(GPIO_PG1_EPI0S14);
GPIOPinConfigure(GPIO_PF5_EPI0S15);
GPIOPinConfigure(GPIO_PJ0_EPI0S16);
GPIOPinConfigure(GPIO_PJ1_EPI0S17);
GPIOPinConfigure(GPIO_PJ2_EPI0S18);
GPIOPinConfigure(GPIO_PJ3_EPI0S19);
GPIOPinConfigure(GPIO_PJ4_EPI0S28);
GPIOPinConfigure(GPIO_PJ5_EPI0S29);
GPIOPinConfigure(GPIO_PJ6_EPI0S30);
GPIOPinConfigure(GPIO_PG7_EPI0S31);
//
// Configure the GPIO pins for EPI mode. All the EPI pins require 8mA
// drive strength in push-pull operation. This step also gives control of
// pins to the EPI module.
// TODO: change this to select the port/pin you are using.
//
GPIOPinTypeEPI(GPIO_PORTC_BASE, EPI_PORTC_PINS);
GPIOPinTypeEPI(GPIO_PORTE_BASE, EPI_PORTE_PINS);
GPIOPinTypeEPI(GPIO_PORTF_BASE, EPI_PORTF_PINS);
GPIOPinTypeEPI(GPIO_PORTG_BASE, EPI_PORTG_PINS);
GPIOPinTypeEPI(GPIO_PORTH_BASE, EPI_PORTH_PINS);
GPIOPinTypeEPI(GPIO_PORTJ_BASE, EPI_PORTJ_PINS);
//
// Now set the EPI operating mode for the daughter board detected. We need
// to determine some timing information based on the ID block we have and
// also the current system clock.
//
ulClk = ROM_SysCtlClockGet();
ulNsPerTick = 1000000000 / ulClk;
//
// Set the EPI clock divider to ensure a basic EPI clock rate no faster
// than defined via the ucRate0nS and ucRate1nS fields in the info
// structure.
//
EPIDividerSet(EPI0_BASE, CalcEPIDivider(ulNsPerTick));
// //
// // Sets the clock divider for the EPI module. In this case set the
// // divider to 0, making the EPIClock = SysClk.
// //
// EPIDividerSet(EPI0_BASE, 0);
//
// Sets the usage mode of the EPI module. For this example we will use
// the SDRAM mode to talk to the external 8MB SDRAM daughter card.
//
EPIModeSet(EPI0_BASE, EPI_MODE_SDRAM);
//
// Configure the SDRAM mode. We configure the SDRAM according to our core
// clock frequency, in this case we are in the 15 MHz < clk <= 30 MHz
// range (i.e 16Mhz crystal). We will use the normal (or full power)
// operating state which means we will not use the low power self-refresh
// state. Set the SDRAM size to 8MB (or 64Mb) with a refresh counter of
// 1024 clock ticks.
// TODO: change this to select the proper clock frequency and SDRAM
// refresh counter.
//
ulRefresh = 0;
ulConfig = SDRAMConfigGet(ulClk, &ulRefresh);
EPIConfigSDRAMSet(EPI0_BASE, ulConfig | EPI_SDRAM_FULL_POWER | EPI_SDRAM_SIZE_64MBIT, 1024);
//
// Set the address map. The EPI0 is mapped from 0x60000000 to 0xCFFFFFFF.
// For this example, we will start from a base address of 0x60000000 with
// a size of 16MB. We use 16MB so we have the ability to access the
// entire 8MB SDRAM daughter card. Since there is no 8MB option, so we
// use the next closest one. If you attempt to access an address higher
// than 4Meg (since SDRAM mode uses 16-bit data, you have 4Meg of
// of addresses by 16-bits of data) a fault will not occur since we
// configured the EPI for 16MB addressability. In the case that you do
// access an address higher than 0x3FFFFF, the MSb of the address gets
// ignored.
//
EPIAddressMapSet(EPI0_BASE, EPI_ADDR_RAM_SIZE_16MB | EPI_ADDR_RAM_BASE_6);
//
// Wait for the SDRAM wake-up to complete by polling the SDRAM
// initialization sequence bit. This bit is true when the SDRAM interface
// is going through the initialization and false when the SDRAM interface
// it is not in a wake-up period.
//
while(HWREG(EPI0_BASE + EPI_O_STAT) & EPI_STAT_INITSEQ)
{
}
}
