static uint8_t
L3_getbyte(struct uda1341_softc *sc, int mode)
{
int i;
uint8_t data;
switch (mode) {
case 0: /* Address mode */
case 1: /* First data byte */
break;
default: /* second data byte via halt-Time */
GPIO_WRITE(sc, SAGPIO_PCR, L3_CLK); /* Clock down */
delay(L3_HALT);
GPIO_WRITE(sc, SAGPIO_PSR, L3_CLK); /* Clock up */
break;
}
delay(L3_MODE_SETUP);
for (i = 0; i < 8; i++)
data |= (L3_getbit(sc) << i);
delay(L3_MODE_HOLD);
return (data);
}
static void
L3_sendbyte(struct uda1341_softc *sc, uint8_t data, int mode)
{
int i;
switch (mode) {
case 0: /* Address mode */
GPIO_WRITE(sc, SAGPIO_PCR, L3_CLK); /* Clock down */
break;
case 1: /* First data byte */
break;
default: /* second data byte via halt-Time */
GPIO_WRITE(sc, SAGPIO_PCR, L3_CLK); /* Clock down */
delay(L3_HALT);
GPIO_WRITE(sc, SAGPIO_PSR, L3_CLK); /* Clock up */
break;
}
delay(L3_MODE_SETUP);
for (i = 0; i < 8; i++)
L3_sendbit(sc, data >> i);
if (mode == 0) /* Address mode */
GPIO_WRITE(sc, SAGPIO_PSR, L3_CLK); /* Clock up */
delay(L3_MODE_HOLD);
}
static void
uda1341_output_high(struct uda1341_softc *sc)
{
int cr;
GPIO_WRITE(sc, SAGPIO_PSR, (L3_DATA | L3_MODE | L3_CLK));
cr = GPIO_READ(sc, SAGPIO_PDR) | (L3_DATA | L3_MODE | L3_CLK);
GPIO_WRITE(sc, SAGPIO_PDR, cr);
}
static void
L3_sendbit(struct uda1341_softc *sc, int bit)
{
GPIO_WRITE(sc, SAGPIO_PCR, L3_CLK); /* Clock down */
if (bit & 0x01)
GPIO_WRITE(sc, SAGPIO_PSR, L3_DATA);
else
GPIO_WRITE(sc, SAGPIO_PCR, L3_DATA);
delay(L3_CLK_LOW);
GPIO_WRITE(sc, SAGPIO_PSR, L3_CLK); /* Clock up */
delay(L3_CLK_HIGH);
}
static void
tegra_gpio_pin_ctl(void *priv, int pin, int flags)
{
struct tegra_gpio_bank *bank = priv;
uint32_t v;
if (flags & GPIO_PIN_INPUT) {
v = (1 << (pin + 8));
GPIO_WRITE(bank, GPIO_MSK_OE_REG, v);
} else if (flags & GPIO_PIN_OUTPUT) {
v = (1 << (pin + 8));
v |= (1 << pin);
GPIO_WRITE(bank, GPIO_MSK_OE_REG, v);
}
}
struct tegra_gpio_pin *
tegra_gpio_acquire(const char *pinname, u_int flags)
{
struct tegra_gpio_bank bank;
struct tegra_gpio_pin *gpin;
int pin;
device_t dev;
dev = device_find_by_driver_unit("tegragpio", 0);
if (dev == NULL)
return NULL;
bank.bank_sc = device_private(dev);
bank.bank_pb = tegra_gpio_pin_lookup(pinname, &pin);
if (bank.bank_pb == NULL)
return NULL;
const uint32_t cnf = GPIO_READ(&bank, GPIO_CNF_REG);
if ((cnf & __BIT(pin)) == 0)
GPIO_WRITE(&bank, GPIO_CNF_REG, cnf | __BIT(pin));
gpin = kmem_alloc(sizeof(*gpin), KM_SLEEP);
gpin->pin_bank = bank;
gpin->pin_no = pin;
gpin->pin_flags = flags;
tegra_gpio_pin_ctl(&gpin->pin_bank, gpin->pin_no, gpin->pin_flags);
return gpin;
}
static int
L3_getbit(struct uda1341_softc *sc)
{
int cr, data;
GPIO_WRITE(sc, SAGPIO_PCR, L3_CLK); /* Clock down */
delay(L3_CLK_LOW);
cr = GPIO_READ(sc, SAGPIO_PLR);
data = (cr & L3_DATA) ? 1 : 0;
GPIO_WRITE(sc, SAGPIO_PSR, L3_CLK); /* Clock up */
delay(L3_CLK_HIGH);
return (data);
}
static void
uda1341_output_low(struct uda1341_softc *sc)
{
int cr;
cr = GPIO_READ(sc, SAGPIO_PDR);
cr &= ~(L3_DATA | L3_MODE | L3_CLK);
GPIO_WRITE(sc, SAGPIO_PDR, cr);
}
/*******************
PCB in laadmodus zetten
*******************/
void charge(){
GPIO_WRITE(DISCHARGE_BANK, DISCHARGE_PIN, 0);
charging = 1;
//if(isOn()==1){
/*We roepen meteen ook het laadalgoritme op zodat er zeker niet ongecontroleerd kan gebeuren.
We moeten voor zekerheid ook controleren dat de pcb niet aanstaat anders is het nutteloos van het oplaadalgoritme te laten rekenen.*/
//chargeAlgorithm();
//}
}
static void
uda1341_init(struct uda1341_softc *sc)
{
int cr;
/* GPIO initialize */
cr = GPIO_READ(sc, SAGPIO_AFR);
cr &= ~(GPIO_ALT_SSP_TXD | GPIO_ALT_SSP_RXD | GPIO_ALT_SSP_SCLK |
GPIO_ALT_SSP_SFRM);
cr |= GPIO_ALT_SSP_CLK;
GPIO_WRITE(sc, SAGPIO_AFR, cr);
cr = GPIO_READ(sc, SAGPIO_PDR);
cr &= ~GPIO_ALT_SSP_CLK;
GPIO_WRITE(sc, SAGPIO_PDR, cr);
/* SSP initialize & enable */
SSP_WRITE(sc, SASSP_CR1, CR1_ECS);
cr = 0xF | (CR0_FRF_MASK & (1<<4)) | (CR0_SCR_MASK & (3<<8)) | CR0_SSE;
SSP_WRITE(sc, SASSP_CR0, cr);
/* Enable the audio power */
sc->sc_parent->ipaq_egpio |=
(EGPIO_H3600_AUD_PWRON | EGPIO_H3600_AUD_ON);
sc->sc_parent->ipaq_egpio &=
~(EGPIO_H3600_CODEC_RESET | EGPIO_H3600_QMUTE);
EGPIO_WRITE(sc);
/* external clock configured for 44100 samples/sec */
cr = GPIO_READ(sc, SAGPIO_PDR);
cr |= (GPIO_H3600_CLK_SET0 | GPIO_H3600_CLK_SET1);
GPIO_WRITE(sc, SAGPIO_PDR, cr);
GPIO_WRITE(sc, SAGPIO_PSR, GPIO_H3600_CLK_SET0);
GPIO_WRITE(sc, SAGPIO_PCR, GPIO_H3600_CLK_SET1);
/* wait for power on */
delay(100*1000);
sc->sc_parent->ipaq_egpio |= EGPIO_H3600_CODEC_RESET;
EGPIO_WRITE(sc);
/* Wait for the UDA1341 to wake up */
delay(100*1000);
}
static void
tegra_gpio_pin_write(void *priv, int pin, int val)
{
struct tegra_gpio_bank *bank = priv;
uint32_t v;
v = (1 << (pin + 8));
v |= (val << pin);
GPIO_WRITE(bank, GPIO_MSK_OUT_REG, v);
}
static int
ar71xx_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value)
{
struct ar71xx_gpio_softc *sc = device_get_softc(dev);
int i;
for (i = 0; i < sc->gpio_npins; i++) {
if (sc->gpio_pins[i].gp_pin == pin)
break;
}
if (i >= sc->gpio_npins)
return (EINVAL);
if (value)
GPIO_WRITE(sc, AR71XX_GPIO_SET, (1 << pin));
else
GPIO_WRITE(sc, AR71XX_GPIO_CLEAR, (1 << pin));
return (0);
}
static int
ar71xx_gpio_pin_toggle(device_t dev, uint32_t pin)
{
int res, i;
struct ar71xx_gpio_softc *sc = device_get_softc(dev);
for (i = 0; i < sc->gpio_npins; i++) {
if (sc->gpio_pins[i].gp_pin == pin)
break;
}
if (i >= sc->gpio_npins)
return (EINVAL);
res = (GPIO_READ(sc, AR71XX_GPIO_IN) & (1 << pin)) ? 1 : 0;
if (res)
GPIO_WRITE(sc, AR71XX_GPIO_CLEAR, (1 << pin));
else
GPIO_WRITE(sc, AR71XX_GPIO_SET, (1 << pin));
return (0);
}
static int
L3_read(struct uda1341_softc *sc, uint8_t addr, uint8_t *data, int len)
{
int cr, mode;
mode = 0;
uda1341_output_high(sc);
L3_sendbyte(sc, addr, mode++);
cr = GPIO_READ(sc, SAGPIO_PDR);
cr &= ~(L3_DATA);
GPIO_WRITE(sc, SAGPIO_PDR, cr);
while(len--)
*data++ = L3_getbyte(sc, mode++);
uda1341_output_low(sc);
return len;
}
/*******************
PCB in ontlaadmodus zetten
*******************/
void discharge(){
GPIO_WRITE(DISCHARGE_BANK, DISCHARGE_PIN, 1);
charging = 0;
}
void write_gpio(int port, int n) {
GPIO_WRITE(port, n);
}
/*******************
PCB afzetten
*******************/
void turnOff(){
GPIO_WRITE(ON_OFF_BANK, ON_OFF_PIN, 0);
on = 0;
}
/*******************
PCB aanzetten
*******************/
void turnOn(){
GPIO_WRITE(ON_OFF_BANK, ON_OFF_PIN, 1);
on = 1;
}
inline static void high(void) {
s_high++;
GPIO_WRITE(s_pin, 1);
}
static int
ar71xx_gpio_attach(device_t dev)
{
struct ar71xx_gpio_softc *sc = device_get_softc(dev);
int error = 0;
int i, j, maxpin;
int mask, pinon;
int old = 0;
KASSERT((device_get_unit(dev) == 0),
("ar71xx_gpio: Only one gpio module supported"));
mtx_init(&sc->gpio_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
MTX_DEF);
/* Map control/status registers. */
sc->gpio_mem_rid = 0;
sc->gpio_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
&sc->gpio_mem_rid, RF_ACTIVE);
if (sc->gpio_mem_res == NULL) {
device_printf(dev, "couldn't map memory\n");
error = ENXIO;
ar71xx_gpio_detach(dev);
return(error);
}
if ((sc->gpio_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
&sc->gpio_irq_rid, RF_SHAREABLE | RF_ACTIVE)) == NULL) {
device_printf(dev, "unable to allocate IRQ resource\n");
return (ENXIO);
}
if ((bus_setup_intr(dev, sc->gpio_irq_res, INTR_TYPE_MISC,
ar71xx_gpio_filter, ar71xx_gpio_intr, sc, &sc->gpio_ih))) {
device_printf(dev,
"WARNING: unable to register interrupt handler\n");
return (ENXIO);
}
sc->dev = dev;
/* Enable function bits that are required */
if (resource_int_value(device_get_name(dev), device_get_unit(dev),
"function_set", &mask) == 0) {
device_printf(dev, "function_set: 0x%x\n", mask);
ar71xx_gpio_function_enable(sc, mask);
old = 1;
}
/* Disable function bits that are required */
if (resource_int_value(device_get_name(dev), device_get_unit(dev),
"function_clear", &mask) == 0) {
device_printf(dev, "function_clear: 0x%x\n", mask);
ar71xx_gpio_function_disable(sc, mask);
old = 1;
}
/* Handle previous behaviour */
if (old == 0) {
ar71xx_gpio_function_enable(sc, GPIO_FUNC_SPI_CS1_EN);
ar71xx_gpio_function_enable(sc, GPIO_FUNC_SPI_CS2_EN);
}
/* Configure all pins as input */
/* disable interrupts for all pins */
GPIO_WRITE(sc, AR71XX_GPIO_INT_MASK, 0);
/* Initialise all pins specified in the mask, up to the pin count */
(void) ar71xx_gpio_pin_max(dev, &maxpin);
if (resource_int_value(device_get_name(dev), device_get_unit(dev),
"pinmask", &mask) != 0)
mask = 0;
if (resource_int_value(device_get_name(dev), device_get_unit(dev),
"pinon", &pinon) != 0)
pinon = 0;
device_printf(dev, "gpio pinmask=0x%x\n", mask);
for (i = 0, j = 0; j < maxpin; j++) {
if ((mask & (1 << j)) == 0)
continue;
snprintf(sc->gpio_pins[i].gp_name, GPIOMAXNAME,
"pin %d", j);
sc->gpio_pins[i].gp_pin = j;
sc->gpio_pins[i].gp_caps = DEFAULT_CAPS;
sc->gpio_pins[i].gp_flags = 0;
ar71xx_gpio_pin_configure(sc, &sc->gpio_pins[i], DEFAULT_CAPS);
i++;
}
sc->gpio_npins = i;
for (i = 0; i < sc->gpio_npins; i++) {
j = sc->gpio_pins[i].gp_pin;
if ((pinon & (1 << j)) != 0)
ar71xx_gpio_pin_set(dev, j, 1);
}
device_add_child(dev, "gpioc", device_get_unit(dev));
device_add_child(dev, "gpiobus", device_get_unit(dev));
return (bus_generic_attach(dev));
}
void charge(){
GPIO_WRITE(DISCHARGE_BANK, DISCHARGE_PIN, 0);
charging = 1;
}
inline static void low(void) {
s_low++;
GPIO_WRITE(s_pin, 0);
}
static int
ar71xx_gpio_attach(device_t dev)
{
struct ar71xx_gpio_softc *sc = device_get_softc(dev);
int error = 0;
struct ar71xx_gpio_pin *pinp;
int i;
KASSERT((device_get_unit(dev) == 0),
("ar71xx_gpio: Only one gpio module supported"));
mtx_init(&sc->gpio_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
MTX_DEF);
/* Map control/status registers. */
sc->gpio_mem_rid = 0;
sc->gpio_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
&sc->gpio_mem_rid, RF_ACTIVE);
if (sc->gpio_mem_res == NULL) {
device_printf(dev, "couldn't map memory\n");
error = ENXIO;
ar71xx_gpio_detach(dev);
return(error);
}
if ((sc->gpio_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
&sc->gpio_irq_rid, RF_SHAREABLE | RF_ACTIVE)) == NULL) {
device_printf(dev, "unable to allocate IRQ resource\n");
return (ENXIO);
}
if ((bus_setup_intr(dev, sc->gpio_irq_res, INTR_TYPE_MISC,
ar71xx_gpio_filter, ar71xx_gpio_intr, sc, &sc->gpio_ih))) {
device_printf(dev,
"WARNING: unable to register interrupt handler\n");
return (ENXIO);
}
sc->dev = dev;
ar71xx_gpio_function_enable(sc, GPIO_FUNC_SPI_CS1_EN);
ar71xx_gpio_function_enable(sc, GPIO_FUNC_SPI_CS2_EN);
/* Configure all pins as input */
/* disable interrupts for all pins */
GPIO_WRITE(sc, AR71XX_GPIO_INT_MASK, 0);
pinp = ar71xx_gpio_pins;
i = 0;
while (pinp->name) {
strncpy(sc->gpio_pins[i].gp_name, pinp->name, GPIOMAXNAME);
sc->gpio_pins[i].gp_pin = pinp->pin;
sc->gpio_pins[i].gp_caps = DEFAULT_CAPS;
sc->gpio_pins[i].gp_flags = 0;
ar71xx_gpio_pin_configure(sc, &sc->gpio_pins[i], pinp->flags);
pinp++;
i++;
}
sc->gpio_npins = i;
device_add_child(dev, "gpioc", device_get_unit(dev));
device_add_child(dev, "gpiobus", device_get_unit(dev));
return (bus_generic_attach(dev));
}
