static void mv_mask_irq(unsigned int irq)
{
if(irq < 32)
MV_REG_BIT_RESET(CPU_INT_MASK_LOW_REG(coreId), (1 << irq) );
else if(irq < 64)/* irq > 32 && irq < 64 */
MV_REG_BIT_RESET(CPU_INT_MASK_HIGH_REG(coreId), (1 << (irq - 32)));
else /* gpp */
MV_REG_BIT_RESET(GPP_INT_LVL_REG(0), (1 << (irq - 64)));
}
void __init mv_init_irq(void)
{
u32 gppMask,i;
#if defined(CONFIG_MV78200) || defined(CONFIG_MV632X)
coreId = whoAmI();
printk("IRQ initialize for core %d\n", coreId);
#endif
/* Disable all interrupts initially. */
if (0 == coreId)
{
MV_REG_WRITE(GPP_INT_MASK_REG(0), 0);
MV_REG_WRITE(GPP_INT_LVL_REG(0), 0);
}
MV_REG_WRITE(CPU_INT_MASK_LOW_REG(coreId), 0);
MV_REG_WRITE(CPU_INT_MASK_HIGH_REG(coreId), 0);
/* Set Gpp interrupts as needed */
if (0 == coreId) /*GPP for core 0 only*/
{
gppMask = mvBoardGpioIntMaskGet();
mvGppTypeSet(0, gppMask , (MV_GPP_IN & gppMask));
mvGppPolaritySet(0, gppMask , (MV_GPP_IN_INVERT & gppMask));
/* clear all int */
MV_REG_WRITE(GPP_INT_MASK_REG(0), 0);
MV_REG_WRITE(CPU_INT_MASK_HIGH_REG(coreId), IRQ_GPP_MASK);
}
else
MV_REG_WRITE(CPU_INT_MASK_HIGH_REG(coreId), 0);
/* Do the core module ones */
for (i = 0; i < NR_IRQS; i++) {
set_irq_chip(i, &mv_chip);
set_irq_handler(i, handle_level_irq);
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
}
/* TBD. Add support for error interrupts */
return;
}
//----------------------------------------------------------------------
// RTC
//----------------------------------------------------------------------
void BuffaloGpio_RtcIntSetup(void)
{
mvGppTypeSet(0, BIT(BIT_RTC) , BIT(BIT_RTC)); // disable output
mvGppPolaritySet(0, BIT(BIT_RTC) , 0);
MV_REG_WRITE(GPP_INT_LVL_REG(0), 0);
}