static inline void rtc_go_output(unsigned int mask) { unsigned int f = GTREGREAD(GPP_IO_CONTROL) | mask; GT_REG_WRITE(GPP_IO_CONTROL, f); }
static inline void rtc_go_low(unsigned int mask) { unsigned int f = GTREGREAD(GPP_VALUE) & ~mask; GT_REG_WRITE(GPP_VALUE, f); }
char mpsc_getchar_debug (void) { volatile int temp; volatile unsigned int cause; cause = GTREGREAD (GALMPSC_0_INT_CAUSE); while ((cause & BIT6) == 0) { cause = GTREGREAD (GALMPSC_0_INT_CAUSE); } temp = GTREGREAD (GALMPSC_CHANNELREG_10 + (CHANNEL * GALMPSC_REG_GAP)); /* By writing 1's to the set bits, the register is cleared */ GT_REG_WRITE (GALMPSC_CHANNELREG_10 + (CHANNEL * GALMPSC_REG_GAP), temp); GT_REG_WRITE (GALMPSC_0_INT_CAUSE, cause & ~BIT6); return (temp >> 16) & 0xff; }
/************************************************************************** MII utilities - read: read from an MII register via SMI ***************************************************************************/ int gt6426x_miiphy_read(const char *devname, unsigned char phy, unsigned char reg, unsigned short *val) { unsigned int temp= (reg<<21) | (phy<<16) | 1<<26; while(GTREGREAD(ETHERNET_SMI_REGISTER) & (1<<28)); /* wait for !Busy */ GT_REG_WRITE(ETHERNET_SMI_REGISTER, temp); while(1) { temp=GTREGREAD(ETHERNET_SMI_REGISTER); if(temp & (1<<27)) break; /* wait for ReadValid */ } *val = temp & 0xffff; return 0; }
/************************************************************************** MII utilities - write: write to an MII register via SMI ***************************************************************************/ int gt6426x_miiphy_write(const char *devname, unsigned char phy, unsigned char reg, unsigned short data) { unsigned int temp= (reg<<21) | (phy<<16) | data; while(GTREGREAD(ETHERNET_SMI_REGISTER) & (1<<28)); /* wait for !Busy */ GT_REG_WRITE(ETHERNET_SMI_REGISTER, temp); return 0; }
/* special function for running out of flash. doesn't modify any * global variables [josh] */ int mpsc_putchar_early (char ch) { int mpsc = CHANNEL; int temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)); galmpsc_set_tcschar (mpsc, ch); GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp | 0x200); #define MAGIC_FACTOR (10*1000000) udelay (MAGIC_FACTOR / gd->baudrate); return 0; }
static void mpsc_debug_init (void) { volatile unsigned int temp; /* Clear the CFR (CHR4) */ /* Write random 'Z' bit (bit 29) of CHR4 to enable debug uart *UNDOCUMENTED FEATURE* */ temp = GTREGREAD (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_REG_GAP)); temp &= 0xffffff00; temp |= BIT29; GT_REG_WRITE (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_REG_GAP), temp); /* Set the Valid bit 'V' (bit 12) and int generation bit 'INT' (bit 15) */ temp = GTREGREAD (GALMPSC_CHANNELREG_5 + (CHANNEL * GALMPSC_REG_GAP)); temp |= (BIT12 | BIT15); GT_REG_WRITE (GALMPSC_CHANNELREG_5 + (CHANNEL * GALMPSC_REG_GAP), temp); /* Set int mask */ temp = GTREGREAD (GALMPSC_0_INT_MASK); temp |= BIT6; GT_REG_WRITE (GALMPSC_0_INT_MASK, temp); }
/* This is used after relocation, see serial.c and mpsc_init2 */ static int mpsc_putchar_sdma(char ch) { volatile unsigned int *p; unsigned int temp; /* align the descriptor */ p = tx_desc_base; memset((void *)p, 0, 8 * sizeof(unsigned int)); /* fill one 64 bit buffer */ /* word swap, pad with 0 */ p[4] = 0; /* x */ p[5] = (unsigned int)ch; /* x */ /* CHANGED completely according to GT64260A dox - NTL */ p[0] = 0x00010001; /* 0 */ p[1] = DESC_OWNER | DESC_FIRST | DESC_LAST; /* 4 */ p[2] = 0; /* 8 */ p[3] = (unsigned int)&p[4]; /* c */ #if 0 p[9] = DESC_FIRST | DESC_LAST; p[10] = (unsigned int)&p[0]; p[11] = (unsigned int)&p[12]; #endif FLUSH_DCACHE(&p[0], &p[8]); GT_REG_WRITE(GALSDMA_0_CUR_TX_PTR+(CHANNEL*GALSDMA_REG_DIFF), (unsigned int)&p[0]); GT_REG_WRITE(GALSDMA_0_FIR_TX_PTR+(CHANNEL*GALSDMA_REG_DIFF), (unsigned int)&p[0]); temp = GTREGREAD(GALSDMA_0_COM_REG+(CHANNEL*GALSDMA_REG_DIFF)); temp |= (TX_DEMAND | TX_STOP); GT_REG_WRITE(GALSDMA_0_COM_REG+(CHANNEL*GALSDMA_REG_DIFF), temp); INVALIDATE_DCACHE(&p[1], &p[2]); while(p[1] & DESC_OWNER) { udelay(100); INVALIDATE_DCACHE(&p[1], &p[2]); } return 0; }
/******************************************************************** * pciWriteConfigReg - Write to a PCI configuration register * - Make sure the GT is configured as a master before writing * to another device on the PCI. * - The function takes care of Big/Little endian conversion. * * * Inputs: unsigned int regOffset: The register offset as it apears in the GT spec * (or any other PCI device spec) * pciDevNum: The device number needs to be addressed. * * Configuration Address 0xCF8: * * 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number * |congif|Reserved| Bus |Device|Function|Register|00| * |Enable| |Number|Number| Number | Number | | <=field Name * *********************************************************************/ void pciWriteConfigReg (PCI_HOST host, unsigned int regOffset, unsigned int pciDevNum, unsigned int data) { volatile unsigned int DataForAddrReg; unsigned int functionNum; unsigned int busNum = PCI_BUS (pciDevNum); unsigned int addr; if (pciDevNum > 32) /* illegal device Number */ return; if (pciDevNum == SELF) { /* configure our configuration space. */ pciDevNum = (GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) & 0x1f; busNum = GTREGREAD (pci_p2p_configuration_reg[host]) & 0xff0000; }
int interrupt_init_cpu (unsigned *decrementer_count) { debug("interrupt_init: GT main cause reg: %08x:%08x\n", GTREGREAD(LOW_INTERRUPT_CAUSE_REGISTER), GTREGREAD(HIGH_INTERRUPT_CAUSE_REGISTER)); debug("interrupt_init: ethernet cause regs: %08x %08x %08x\n", GTREGREAD(ETHERNET0_INTERRUPT_CAUSE_REGISTER), GTREGREAD(ETHERNET1_INTERRUPT_CAUSE_REGISTER), GTREGREAD(ETHERNET2_INTERRUPT_CAUSE_REGISTER)); debug("interrupt_init: ethernet mask regs: %08x %08x %08x\n", GTREGREAD(ETHERNET0_INTERRUPT_MASK_REGISTER), GTREGREAD(ETHERNET1_INTERRUPT_MASK_REGISTER), GTREGREAD(ETHERNET2_INTERRUPT_MASK_REGISTER)); debug("interrupt_init: setting decrementer_count\n"); *decrementer_count = get_tbclk() / CONFIG_SYS_HZ; return (0); }
/************************************************************************** POLL - look for an rx frame, handle other conditions ***************************************************************************/ int gt6426x_eth_poll(void *v) { struct eth_device *wp = (struct eth_device *)v; struct eth_dev_s *p = wp->priv; unsigned int icr=GTREGREAD(ETHERNET0_INTERRUPT_CAUSE_REGISTER + p->reg_base); if(icr) { GT_REG_WRITE(ETHERNET0_INTERRUPT_CAUSE_REGISTER +p->reg_base, 0); #ifdef DEBUG printf("poll got ICR %08x\n", icr); #endif /* SMI done or PHY state change*/ if(icr&0x30000000) gt6426x_handle_SMI(p, icr); } /* always process. We aren't using RX interrupts */ return gt6426x_eth_receive(p, icr); }
static void gt6426x_handle_SMI(struct eth_dev_s *p, unsigned int icr) { #ifdef DEBUG printf("SMI interrupt: "); if(icr&0x20000000) { printf("SMI done\n"); } #endif if(icr&0x10000000) { #ifdef DEBUG unsigned int psr; psr=GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + p->reg_base); printf("PHY state change:\n" " GT:%s:%s:%s:%s\n", psr & 1 ? "100" : " 10", psr & 8 ? " Link" : "nLink", psr & 2 ? "FD" : "HD", psr & 4 ? " FC" : "nFC"); #ifdef CONFIG_INTEL_LXT97X /* non-standard mii reg (intel lxt972a) */ { unsigned short mii_11; mii_11 = miiphy_read_ret(ether_port_phy_addr[p->dev], 0x11); printf(" mii:%s:%s:%s:%s %s:%s %s\n", mii_11 & (1 << 14) ? "100" : " 10", mii_11 & (1 << 10) ? " Link" : "nLink", mii_11 & (1 << 9) ? "FD" : "HD", mii_11 & (1 << 4) ? " FC" : "nFC", mii_11 & (1 << 7) ? "ANc" : "ANnc", mii_11 & (1 << 8) ? "AN" : "Manual", "" ); } #endif /* CONFIG_INTEL_LXT97X */ #endif /* DEBUG */ } }
/* If link is up && autoneg compleate, and if * GT and PHY disagree about link capabilitys, * restart autoneg - something screwy with FD/HD * unless we do this. */ static void check_phy_state(struct eth_dev_s *p) { int bmsr = miiphy_read_ret(ether_port_phy_addr[p->dev], MII_BMSR); int psr = GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + p->reg_base); if ((psr & 1<<3) && (bmsr & BMSR_LSTATUS)) { int nego = miiphy_read_ret(ether_port_phy_addr[p->dev], MII_ADVERTISE) & miiphy_read_ret(ether_port_phy_addr[p->dev], MII_LPA); int want; if (nego & LPA_100FULL) { want = 0x3; printf("MII: 100Base-TX, Full Duplex\n"); } else if (nego & LPA_100HALF) { want = 0x1; printf("MII: 100Base-TX, Half Duplex\n"); } else if (nego & LPA_10FULL) { want = 0x2; printf("MII: 10Base-T, Full Duplex\n"); } else if (nego & LPA_10HALF) { want = 0x0; printf("MII: 10Base-T, Half Duplex\n"); } else { printf("MII: Unknown link-foo! %x\n", nego); return; } if ((psr & 0x3) != want) { printf("MII: GT thinks %x, PHY thinks %x, restarting autoneg..\n", psr & 0x3, want); miiphy_write(GT6426x_MII_DEVNAME,ether_port_phy_addr[p->dev],0, miiphy_read_ret(ether_port_phy_addr[p->dev],0) | (1<<9)); udelay(10000); /* the EVB's GT takes a while to notice phy went down and up */ } } }
static void gt_pci_bus_mode_display (PCI_HOST host) { unsigned int mode; mode = (GTREGREAD (pci_bus_list[host]) & (BIT4 | BIT5)) >> 4; switch (mode) { case 0: printf ("PCI %d bus mode: Conventional PCI\n", host); break; case 1: printf ("PCI %d bus mode: 66 MHz PCIX\n", host); break; case 2: printf ("PCI %d bus mode: 100 MHz PCIX\n", host); break; case 3: printf ("PCI %d bus mode: 133 MHz PCIX\n", host); break; default: printf ("Unknown BUS %d\n", mode); } }
char mpsc_getchar_sdma (void) { static unsigned int done = 0; volatile char ch; unsigned int len = 0, idx = 0, temp; volatile unsigned int *p; do { p = &rx_desc_base[rx_desc_index * 8]; INVALIDATE_DCACHE (&p[0], &p[1]); /* Wait for character */ while (p[1] & DESC_OWNER_BIT) { udelay (100); INVALIDATE_DCACHE (&p[0], &p[1]); } /* Handle error case */ if (p[1] & (1 << 15)) { printf ("oops, error: %08x\n", p[1]); temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (CHANNEL * GALMPSC_REG_GAP)); temp |= (1 << 23); GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (CHANNEL * GALMPSC_REG_GAP), temp); /* Can't poll on abort bit, so we just wait. */ udelay (100); galsdma_enable_rx (); } /* Number of bytes left in this descriptor */ len = p[0] & 0xffff; if (len) { /* Where to look */ idx = 5; if (done > 3) idx = 4; if (done > 7) idx = 7; if (done > 11) idx = 6; INVALIDATE_DCACHE (&p[idx], &p[idx + 1]); ch = p[idx] & 0xff; done++; } if (done < len) { /* this descriptor has more bytes still * shift down the char we just read, and leave the * buffer in place for the next time around */ p[idx] = p[idx] >> 8; FLUSH_DCACHE (&p[idx], &p[idx + 1]); } if (done == len) { /* nothing left in this descriptor. * go to next one */ p[1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST; p[0] = 0x00100000; FLUSH_DCACHE (&p[0], &p[1]); /* Next descriptor */ rx_desc_index = (rx_desc_index + 1) % RX_DESC; done = 0; } } while (len == 0); /* galileo bug.. len might be zero */
/************************************************************************** PROBE - Look for an adapter, this routine's visible to the outside ***************************************************************************/ int gt6426x_eth_probe(void *v, bd_t *bis) { struct eth_device *wp = (struct eth_device *)v; struct eth_dev_s *p = (struct eth_dev_s *)wp->priv; int dev = p->dev; unsigned int reg_base = p->reg_base; unsigned long temp; int i; if (( dev < 0 ) || ( dev >= GAL_ETH_DEVS )) { /* This should never happen */ printf("%s: Invalid device %d\n", __FUNCTION__, dev ); return 0; } #ifdef DEBUG printf ("%s: initializing %s\n", __FUNCTION__, wp->name ); printf ("\nCOMM_CONTROL = %08x , COMM_CONF = %08x\n", GTREGREAD(COMM_UNIT_ARBITER_CONTROL), GTREGREAD(COMM_UNIT_ARBITER_CONFIGURATION_REGISTER)); #endif /* clear MIB counters */ for(i=0;i<255; i++) temp=GTREGREAD(ETHERNET0_MIB_COUNTER_BASE + reg_base +i); #ifdef CONFIG_INTEL_LXT97X /* for intel LXT972 */ /* led 1: 0x1=txact led 2: 0xc=link/rxact led 3: 0x2=rxact (N/C) strch: 0,2=30 ms, enable */ miiphy_write(GT6426x_MII_DEVNAME,ether_port_phy_addr[p->dev], 20, 0x1c22); /* 2.7ns port rise time */ /*miiphy_write(ether_port_phy_addr[p->dev], 30, 0x0<<10); */ #else /* already set up in mpsc.c */ /*GT_REG_WRITE(MAIN_ROUTING_REGISTER, 0x7ffe38); / b400 */ /* already set up in sdram_init.S... */ /* MPSC0, MPSC1, RMII */ /*GT_REG_WRITE(SERIAL_PORT_MULTIPLEX, 0x1102); / f010 */ #endif GT_REG_WRITE(ETHERNET_PHY_ADDRESS_REGISTER, ether_port_phy_addr[0] | (ether_port_phy_addr[1]<<5) | (ether_port_phy_addr[2]<<10)); /* 2000 */ /* 13:12 - 10: 4x64bit burst (cache line size = 32 bytes) * 9 - 1: RIFB - interrupt on frame boundaries only * 6:7 - 00: big endian rx and tx * 5:2 - 1111: 15 retries */ GT_REG_WRITE(ETHERNET0_SDMA_CONFIGURATION_REGISTER + reg_base, (2<<12) | (1<<9) | (0xf<<2) ); /* 2440 */ #ifndef USE_SOFTWARE_CACHE_MANAGEMENT /* enable rx/tx desc/buffer cache snoop */ GT_REG_READ(ETHERNET_0_ADDRESS_CONTROL_LOW + dev*0x20, &temp); /* f200 */ temp|= (1<<6)| (1<<14)| (1<<22)| (1<<30); GT_REG_WRITE(ETHERNET_0_ADDRESS_CONTROL_LOW + dev*0x20, temp); #endif /* 31 28 27 24 23 20 19 16 * 0000 0000 0000 0000 [0004] * 15 12 11 8 7 4 3 0 * 1000 1101 0000 0000 [4d00] * 20 - 0=MII 1=RMII * 19 - 0=speed autoneg * 15:14 - framesize 1536 (GT6426x_ETH_BUF_SIZE) * 11 - no force link pass * 10 - 1=disable fctl autoneg * 8 - override prio ?? */ temp = 0x00004d00; #ifndef CONFIG_ETHER_PORT_MII temp |= (1<<20); /* RMII */ #endif /* set En */ GT_REG_WRITE(ETHERNET0_PORT_CONFIGURATION_EXTEND_REGISTER + reg_base, temp); /* 2408 */ /* hardcode E1 also? */ /* -- according to dox, this is safer due to extra pulldowns? */ if (dev<2) { GT_REG_WRITE(ETHERNET0_PORT_CONFIGURATION_EXTEND_REGISTER + (dev+1) * 0x400, temp); /* 2408 */ } /* wake up MAC */ /* 2400 */ GT_REG_READ(ETHERNET0_PORT_CONFIGURATION_REGISTER + reg_base, &temp); temp |= (1<<7); /* enable port */ #ifdef CONFIG_GT_USE_MAC_HASH_TABLE temp |= (1<<12); /* hash size 1/2k */ #else temp |= 1; /* promisc */ #endif GT_REG_WRITE(ETHERNET0_PORT_CONFIGURATION_REGISTER + reg_base, temp); /* 2400 */ #ifdef RESTART_AUTONEG check_phy_state(p); #endif printf("%s: Waiting for link up..\n", wp->name); temp = 10 * 1000; /* wait for link back up */ while(!(GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + reg_base) & 8) && (--temp > 0)){ udelay(1000); /* wait 1 ms */ } if ( temp == 0) { printf("%s: Failed!\n", wp->name); return (0); } printf("%s: OK!\n", wp->name); p->tdn = 0; p->rdn = 0; p->eth_tx_desc[p->tdn].command_status = 0; /* Initialize Rx Side */ for (temp = 0; temp < NR; temp++) { p->eth_rx_desc[temp].buff_pointer = (uchar *)p->eth_rx_buffer[temp]; p->eth_rx_desc[temp].buff_size_byte_count = GT6426x_ETH_BUF_SIZE<<16; /* GT96100 Owner */ p->eth_rx_desc[temp].command_status = 0x80000000; p->eth_rx_desc[temp].next_desc = (struct eth0_rx_desc_struct *) &p->eth_rx_desc[(temp+1)%NR].buff_size_byte_count; } FLUSH_DCACHE((unsigned int)&p->eth_tx_desc[0], (unsigned int)&p->eth_tx_desc[NR]); FLUSH_DCACHE((unsigned int)&p->eth_rx_desc[0], (unsigned int)&p->eth_rx_desc[NR]); GT_REG_WRITE(ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER0 + reg_base, (unsigned int) p->eth_tx_desc); GT_REG_WRITE(ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER0 + reg_base, (unsigned int) p->eth_rx_desc); GT_REG_WRITE(ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER0 + reg_base, (unsigned int) p->eth_rx_desc); #ifdef DEBUG printf ("\nRx descriptor pointer is %08x %08x\n", GTREGREAD(ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER0 + reg_base), GTREGREAD(ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER0 + reg_base)); printf ("\n\n%08x %08x\n", (unsigned int)p->eth_rx_desc,p->eth_rx_desc[0].command_status); printf ("Descriptor dump:\n"); printf ("cmd status: %08x\n",p->eth_rx_desc[0].command_status); printf ("byte_count: %08x\n",p->eth_rx_desc[0].buff_size_byte_count); printf ("buff_ptr: %08x\n",(unsigned int)p->eth_rx_desc[0].buff_pointer); printf ("next_desc: %08x\n\n",(unsigned int)p->eth_rx_desc[0].next_desc); printf ("%08x\n",*(unsigned int *) ((unsigned int)p->eth_rx_desc + 0x0)); printf ("%08x\n",*(unsigned int *) ((unsigned int)p->eth_rx_desc + 0x4)); printf ("%08x\n",*(unsigned int *) ((unsigned int)p->eth_rx_desc + 0x8)); printf ("%08x\n\n", *(unsigned int *) ((unsigned int)p->eth_rx_desc + 0xc)); #endif #ifdef DEBUG gt6426x_dump_mii(bis,ether_port_phy_addr[p->dev]); #endif #ifdef CONFIG_GT_USE_MAC_HASH_TABLE { unsigned int hashtable_base; u8 *b = (u8 *)(wp->enetaddr); u32 macH, macL; /* twist the MAC up into the way the discovery wants it */ macH= (b[0]<<8) | b[1]; macL= (b[2]<<24) | (b[3]<<16) | (b[4]<<8) | b[5]; /* mode 0, size 0x800 */ hashtable_base =initAddressTable(dev,0,1); if(!hashtable_base) { printf("initAddressTable failed\n"); return 0; } addAddressTableEntry(dev, macH, macL, 1, 0); GT_REG_WRITE(ETHERNET0_HASH_TABLE_POINTER_REGISTER + reg_base, hashtable_base); } #endif /* Start Rx*/ GT_REG_WRITE(ETHERNET0_SDMA_COMMAND_REGISTER + reg_base, 0x00000080); printf("%s: gt6426x eth device %d init success \n", wp->name, dev ); return 1; }
/************************************************************************** TRANSMIT - Transmit a frame ***************************************************************************/ int gt6426x_eth_transmit(void *v, char *p, unsigned int s) { struct eth_device *wp = (struct eth_device *)v; struct eth_dev_s *dev = (struct eth_dev_s *)wp->priv; #ifdef DEBUG unsigned int old_command_stat,old_psr; #endif eth0_tx_desc_single *tx = &dev->eth_tx_desc[dev->tdn]; /* wait for tx to be ready */ INVALIDATE_DCACHE((unsigned int)tx,(unsigned int)(tx+1)); while (tx->command_status & 0x80000000) { int i; for(i=0;i<1000;i++); INVALIDATE_DCACHE((unsigned int)tx,(unsigned int)(tx+1)); } GT_REG_WRITE (ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER0 + dev->reg_base, (unsigned int)tx); #ifdef DEBUG printf("copying to tx_buffer [%p], length %x, desc = %p\n", dev->eth_tx_buffer, s, dev->eth_tx_desc); #endif memcpy(dev->eth_tx_buffer, (char *) p, s); tx->buff_pointer = (uchar *)dev->eth_tx_buffer; tx->bytecount_reserved = ((__u16)s) << 16; /* 31 - own * 22 - gencrc * 18:16 - pad, last, first */ tx->command_status = (1<<31) | (1<<22) | (7<<16); #if 0 /* FEr #18 */ tx->next_desc = NULL; #else tx->next_desc = (struct eth0_tx_desc_struct *) &dev->eth_tx_desc[(dev->tdn+1)%NT].bytecount_reserved; /* cpu owned */ dev->eth_tx_desc[(dev->tdn+1)%NT].command_status = (7<<16); /* pad, last, first */ #endif #ifdef DEBUG old_command_stat=tx->command_status, old_psr=GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + dev->reg_base); #endif FLUSH_DCACHE((unsigned int)tx, (unsigned int)&dev->eth_tx_desc[(dev->tdn+2)%NT]); FLUSH_DCACHE((unsigned int)dev->eth_tx_buffer,(unsigned int)dev->eth_tx_buffer+s); GT_REG_WRITE(ETHERNET0_SDMA_COMMAND_REGISTER + dev->reg_base, 0x01000000); #ifdef DEBUG { unsigned int command_stat=0; printf("cmd_stat: %08x PSR: %08x\n", old_command_stat, old_psr); /* wait for tx to be ready */ do { unsigned int psr=GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + dev->reg_base); command_stat=tx->command_status; if(command_stat!=old_command_stat || psr !=old_psr) { printf("cmd_stat: %08x PSR: %08x\n", command_stat, psr); old_command_stat = command_stat; old_psr = psr; } /* gt6426x_eth0_poll(); */ } while (command_stat & 0x80000000); printf("sent %d byte frame\n", s); if((command_stat & (3<<15)) == 3) { printf("frame had error (stat=%08x)\n", command_stat); } } #endif return 0; }