AGESA_STATUS
GnbCreateIvrsEntryTN (
IN GNB_HANDLE *GnbHandle,
IN IVRS_BLOCK_TYPE Type,
IN VOID *Ivrs,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
IVRS_IVHD_ENTRY *Ivhd;
UINT8 IommuCapabilityOffset;
UINT32 Value;
IDS_HDT_CONSOLE (GNB_TRACE, "GnbFmCreateIvrsEntry Entry\n");
if (Type == IvrsIvhdBlock || Type == IvrsIvhdrBlock) {
// Update IVINFO
IommuCapabilityOffset = GnbLibFindPciCapability (MAKE_SBDFO (0, 0, 0, 2, 0), IOMMU_CAP_ID, StdHeader);
GnbLibPciRead (MAKE_SBDFO (0, 0, 0, 2, IommuCapabilityOffset + 0x10), AccessWidth32, &Value, StdHeader);
((IOMMU_IVRS_HEADER *) Ivrs)->IvInfo = Value & (IVINFO_HTATSRESV_MASK | IVINFO_VASIZE_MASK | IVINFO_GASIZE_MASK | IVINFO_PASIZE_MASK);
// Address of IVHD entry
Ivhd = (IVRS_IVHD_ENTRY*) ((UINT8 *)Ivrs + ((IOMMU_IVRS_HEADER *) Ivrs)->TableLength);
GnbCreateIvhdHeaderTN (Type, Ivhd, StdHeader);
if (Type == IvrsIvhdBlock) {
GnbCreateIvhdTN (Ivhd, StdHeader);
} else {
GnbCreateIvhdrTN (Ivhd, StdHeader);
}
((IOMMU_IVRS_HEADER *) Ivrs)->TableLength = ((IOMMU_IVRS_HEADER *) Ivrs)->TableLength + Ivhd->Length;
}
IDS_HDT_CONSOLE (GNB_TRACE, "GnbFmCreateIvrsEntry Exit\n");
return AGESA_SUCCESS;
}
/**
* Create IVRS entry
*
*
* @param[in] Type Block type
* @param[in] Ivhd IVHD header pointer
* @param[in] StdHeader Standard configuration header
*
*/
VOID
GnbCreateIvhdHeaderTN (
IN IVRS_BLOCK_TYPE Type,
OUT IVRS_IVHD_ENTRY *Ivhd,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 Value;
Ivhd->Type = (UINT8) Type;
Ivhd->Flags = IVHD_FLAG_COHERENT | IVHD_FLAG_IOTLBSUP | IVHD_FLAG_ISOC | IVHD_FLAG_RESPASSPW | IVHD_FLAG_PASSPW | IVHD_FLAG_PPRSUB | IVHD_FLAG_PREFSUP;
Ivhd->Length = sizeof (IVRS_IVHD_ENTRY);
Ivhd->DeviceId = 0x2;
Ivhd->CapabilityOffset = GnbLibFindPciCapability (MAKE_SBDFO (0, 0, 0, 2, 0), IOMMU_CAP_ID, StdHeader);
Ivhd->PciSegment = 0;
GnbLibPciRead (MAKE_SBDFO (0, 0, 0, 2, Ivhd->CapabilityOffset + 0x4), AccessWidth32, &Ivhd->BaseAddress, StdHeader);
GnbLibPciRead (MAKE_SBDFO (0, 0, 0, 2, Ivhd->CapabilityOffset + 0x8), AccessWidth32, (UINT8 *) &Ivhd->BaseAddress + 4, StdHeader);
Ivhd->BaseAddress = Ivhd->BaseAddress & 0xfffffffffffffffe;
ASSERT (Ivhd->BaseAddress != 0x0);
GnbLibPciRead (MAKE_SBDFO (0, 0, 0, 2, Ivhd->CapabilityOffset + 0x10), AccessWidth32, &Value, StdHeader);
Ivhd->IommuInfo = (UINT16) (Value & 0x1f) | (0x13 << IVHD_INFO_UNITID_OFFSET);
Ivhd->IommuEfr = (0 << IVHD_EFR_XTSUP_OFFSET) | (0 << IVHD_EFR_NXSUP_OFFSET) | (1 << IVHD_EFR_GTSUP_OFFSET) |
(0 << IVHD_EFR_GLXSUP_OFFSET) | (1 << IVHD_EFR_IASUP_OFFSET) | (0 << IVHD_EFR_GASUP_OFFSET) |
(0 << IVHD_EFR_HESUP_OFFSET) | (0x8 << IVHD_EFR_PASMAX_OFFSET) | (0 << IVHD_EFR_MSINUMPPR_OFFSET) |
(4 << IVHD_EFR_PNCOUNTERS_OFFSET) | (2 << IVHD_EFR_PNBANKS_OFFSET);
}
/*----------------------------------------------------------------------------------------*/
VOID
PcieRetrain (
IN PCI_ADDR Function,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 PcieCapPtr;
UINT32 Value;
PcieCapPtr = GnbLibFindPciCapability (Function.AddressValue, PCIE_CAP_ID, StdHeader);
Value = BIT27;
if (PcieCapPtr != 0) {
GnbLibPciRMW (
Function.AddressValue | (PcieCapPtr + PCIE_LINK_CTRL_REGISTER),
AccessS3SaveWidth32,
~(UINT32) (BIT5),
BIT5,
StdHeader
);
IDS_HDT_CONSOLE (GNB_TRACE, " PcieRetrain link on Device = %d:%d:%d\n", Function.Address.Bus, Function.Address.Device, Function.Address.Function);
do {
GnbLibPciRead (
Function.AddressValue | (PcieCapPtr + PCIE_LINK_CTRL_REGISTER),
AccessS3SaveWidth32,
&Value,
StdHeader);
} while ((Value & BIT27) != 0);
}
}
/*----------------------------------------------------------------------------------------*/
BOOLEAN
IsPcieCommClk (
IN PCI_ADDR Device,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 PcieCapPtr;
UINT32 Value;
PcieCapPtr = GnbLibFindPciCapability (Device.AddressValue, PCIE_CAP_ID, StdHeader);
if (PcieCapPtr == 0) {
return FALSE;
}
GnbLibPciRead (
Device.AddressValue | (PcieCapPtr + PCIE_LINK_CTRL_REGISTER),
AccessWidth32,
&Value,
StdHeader
);
if ((Value & BIT28) != 0) {
return TRUE;
}
return FALSE;
}
/*----------------------------------------------------------------------------------------*/
STATIC BOOLEAN
PcieClkPmCheckDeviceCapability (
IN PCI_ADDR Device,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 MaxFunc;
UINT8 CurrentFunc;
UINT8 PcieCapPtr;
UINT32 Value;
MaxFunc = GnbLibPciIsMultiFunctionDevice (Device.AddressValue, StdHeader) ? 7 : 0;
for (CurrentFunc = 0; CurrentFunc <= MaxFunc; CurrentFunc++) {
Device.Address.Function = CurrentFunc;
if (GnbLibPciIsDevicePresent (Device.AddressValue, StdHeader)) {
PcieCapPtr = GnbLibFindPciCapability (Device.AddressValue, PCIE_CAP_ID, StdHeader);
if (PcieCapPtr == 0) {
return FALSE;
}
GnbLibPciRead (
Device.AddressValue | (PcieCapPtr + PCIE_LINK_CAP_REGISTER),
AccessWidth32,
&Value,
StdHeader
);
if ((Value & BIT18) == 0) {
return FALSE;
}
}
}
return TRUE;
}
/**
* Check a PCIE device to see if it supports phantom functions
*
* @param[in] Device Device pci address
* @param[in] StdHeader Standard configuration header
* @return TRUE Current device supports phantom functions
*/
STATIC BOOLEAN
GnbCheckPhantomFuncSupport (
IN PCI_ADDR Device,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 PcieCapPtr;
UINT32 Value;
Value = 0;
PcieCapPtr = GnbLibFindPciCapability (Device.AddressValue, PCIE_CAP_ID, StdHeader);
if (PcieCapPtr != 0) {
GnbLibPciRead (Device.AddressValue | (PcieCapPtr + 4), AccessWidth32, &Value, StdHeader);
}
return ((Value & (BIT3 | BIT4)) != 0) ? TRUE : FALSE;
}
/*----------------------------------------------------------------------------------------*/
STATIC VOID
PcieClkPmEnableOnFunction (
IN PCI_ADDR Function,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 PcieCapPtr;
PcieCapPtr = GnbLibFindPciCapability (Function.AddressValue, PCIE_CAP_ID, StdHeader);
if (PcieCapPtr != 0) {
GnbLibPciRMW (
Function.AddressValue | (PcieCapPtr + PCIE_LINK_CTRL_REGISTER),
AccessS3SaveWidth32,
(UINT32)~(BIT8),
BIT8,
StdHeader
);
}
}
/*----------------------------------------------------------------------------------------*/
VOID
PcieProgramCommClkCfgOnFunction (
IN PCI_ADDR Function,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 PcieCapPtr;
PcieCapPtr = GnbLibFindPciCapability (Function.AddressValue, PCIE_CAP_ID, StdHeader);
if (PcieCapPtr != 0) {
IDS_HDT_CONSOLE (GNB_TRACE, " Program Common Clock configuration for Device = %d:%d:%d\n", Function.Address.Bus, Function.Address.Device, Function.Address.Function);
GnbLibPciRMW (
Function.AddressValue | (PcieCapPtr + PCIE_LINK_CTRL_REGISTER),
AccessS3SaveWidth32,
~(UINT32) (BIT6),
BIT6,
StdHeader
);
}
}
VOID
PcieNbAspmEnable (
IN PCI_ADDR Function,
IN PCIE_ASPM_TYPE Aspm,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 PcieCapPtr;
PcieCapPtr = GnbLibFindPciCapability (Function.AddressValue, PCIE_CAP_ID, StdHeader);
if (PcieCapPtr != 0) {
GnbLibPciRMW (
Function.AddressValue | (PcieCapPtr + PCIE_LINK_CTRL_REGISTER) ,
AccessS3SaveWidth8,
~(UINT32)(BIT0 | BIT1),
Aspm,
StdHeader
);
}
}
PCIE_ASPM_TYPE
excel950_fun1 (
IN PCI_ADDR Device,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 PcieCapPtr;
UINT32 Value;
PcieCapPtr = GnbLibFindPciCapability (Device.AddressValue, PCIE_CAP_ID, StdHeader);
if (PcieCapPtr == 0) {
return 0;
}
GnbLibPciRead (
Device.AddressValue | (PcieCapPtr + PCIE_LINK_CAP_REGISTER),
AccessWidth32,
&Value,
StdHeader
);
return (Value >> 10) & 3;
}
