AGESA_STATUS
GnbSmuFirmwareLoadV4 (
IN PCI_ADDR GnbPciAddress,
IN FIRMWARE_HEADER_V4 *Firmware,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 Index;
D0F0xBC_xE00030A4_STRUCT D0F0xBC_xE00030A4;
D0F0xBC_xE0000004_STRUCT D0F0xBC_xE0000004;
D0F0xBC_xE0003088_STRUCT D0F0xBC_xE0003088;
D0F0xBC_x80010000_STRUCT D0F0xBC_x80010000;
D0F0xBC_x1F380_STRUCT D0F0xBC_x1F380;
IDS_HDT_CONSOLE (GNB_TRACE, "GnbSmuFirmwareLoadV4 Enter\n");
IDS_HDT_CONSOLE (NB_MISC, " Firmware version 0x%x\n", Firmware->Version);
IDS_OPTION_HOOK (IDS_REPORT_SMU_FW_VERSION, &(Firmware->Version), StdHeader);
// Step 2, 10, make sure Rom firmware sequence is done
do {
GnbLibPciIndirectRead (GnbPciAddress.AddressValue | D0F0xB8_ADDRESS, D0F0xBC_xE0000004_ADDRESS, AccessWidth32, &D0F0xBC_xE0000004.Value, StdHeader);
} while (D0F0xBC_xE0000004.Field.boot_seq_done == 0);
// Step 1, check if firmware running in protected mode
GnbLibPciIndirectRead (GnbPciAddress.AddressValue | D0F0xB8_ADDRESS, D0F0xBC_xE00030A4_ADDRESS, AccessWidth32, &D0F0xBC_xE00030A4.Value, StdHeader);
if (D0F0xBC_xE00030A4.Field.SmuProtectedMode == 0) {
// Step3, Clear firmware interrupt flags
GnbLibPciIndirectRMW (
GnbPciAddress.AddressValue | D0F0xB8_ADDRESS,
D0F0xBC_x1F380_ADDRESS,
AccessWidth32,
0x0,
0x0,
StdHeader
);
}
//Step 4, 11, Assert LM32 reset
GnbLibPciIndirectRMW (
GnbPciAddress.AddressValue | D0F0xB8_ADDRESS,
D0F0xBC_x80000000_ADDRESS,
AccessWidth32,
(UINT32) ~(D0F0xBC_x80000000_lm32_rst_reg_MASK),
1 << D0F0xBC_x80000000_lm32_rst_reg_OFFSET,
StdHeader
);
// Step5, 12, Load firmware
for (Index = 0; Index < (Firmware->FirmwareLength + Firmware->HeaderLength); Index++) {
GnbLibPciIndirectWrite (GnbPciAddress.AddressValue | D0F0xB8_ADDRESS, SMC_RAM_START_ADDR + (Index * 4), AccessWidth32, &((UINT32 *) Firmware)[Index], StdHeader);
}
if (D0F0xBC_xE00030A4.Field.SmuProtectedMode == 0) {
//Step 6, Write jmp to RAM firmware
GnbLibPciIndirectRMW (
GnbPciAddress.AddressValue | D0F0xB8_ADDRESS,
0x0,
AccessWidth32,
0x0,
0xE0000000 + ((SMC_RAM_START_ADDR + Firmware->HeaderLength * 4) >> 2),
StdHeader
);
} else {
VOID
NbInitOnPowerOnRecovery (
IN PCI_ADDR NbPciAddress,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINTN Index;
// Init NBCONFIG
for (Index = 0; Index < (sizeof (NbPciInitRecoveryTable) / sizeof (NB_REGISTER_RECOVERY_ENTRY)); Index++) {
GnbLibPciRMW (
NbPciAddress.AddressValue | NbPciInitRecoveryTable[Index].Reg,
AccessWidth32,
NbPciInitRecoveryTable[Index].Mask,
NbPciInitRecoveryTable[Index].Data,
StdHeader
);
}
// Init MISCIND
for (Index = 0; Index < (sizeof (NbMiscInitRecoveryTable) / sizeof (NB_REGISTER_RECOVERY_ENTRY)); Index++) {
GnbLibPciIndirectRMW (
NbPciAddress.AddressValue | D0F0x60_ADDRESS,
NbMiscInitRecoveryTable[Index].Reg | IOC_WRITE_ENABLE,
AccessWidth32,
NbMiscInitRecoveryTable[Index].Mask,
NbMiscInitRecoveryTable[Index].Data,
StdHeader
);
}
return;
}
VOID
STATIC
PcieSiliconEnablePortsV5 (
IN PCIe_SILICON_CONFIG *Silicon,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
PCIe_ENGINE_CONFIG *EngineList;
EngineList = PcieConfigGetChildEngine (Silicon);
while (EngineList != NULL) {
if (PcieConfigIsPcieEngine (EngineList)) {
if (!PcieConfigIsSbPcieEngine (EngineList) &&
(PcieConfigCheckPortStatus (EngineList, INIT_STATUS_PCIE_TRAINING_SUCCESS) ||
((EngineList->Type.Port.PortData.LinkHotplug != HotplugDisabled) &&
(EngineList->Type.Port.PortData.LinkHotplug != HotplugInboard)))) {
GnbLibPciIndirectRMW (
Silicon->Address.AddressValue | D0F0xC8_ADDRESS,
D0F0xCC_x01_ADDRESS | ((EngineList->Type.Port.PortData.DeviceNumber << 3 | EngineList->Type.Port.PortData.FunctionNumber) << D0F0xC8_NB_DEV_IND_SEL_OFFSET),
AccessS3SaveWidth32,
(UINT32)~(D0F0xCC_x01_BridgeDis_MASK | D0F0xCC_x01_CfgDis_MASK | D0F0xCC_x01_CsrEnable_MASK | D0F0xCC_x01_SetPowEn_MASK),
((1 << D0F0xCC_x01_CsrEnable_OFFSET) | (1 << D0F0xCC_x01_SetPowEn_OFFSET)),
GnbLibGetHeader (Pcie)
);
}
}
EngineList = (PCIe_ENGINE_CONFIG *) PcieConfigGetNextTopologyDescriptor (EngineList, DESCRIPTOR_TERMINATE_GNB);
}
}
VOID
STATIC
PcieSiliconControlPortsV5 (
IN PCIE_PORT_VISIBILITY Control,
IN PCIe_SILICON_CONFIG *Silicon,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
PCIe_ENGINE_CONFIG *EngineList;
UINT32 Value;
Value = (Control == HidePorts) ? ((1 << D0F0xCC_x01_BridgeDis_OFFSET) | (1 << D0F0xCC_x01_CfgDis_OFFSET)) : 0;
Value |= (1 << D0F0xCC_x01_CsrEnable_OFFSET) | (1 << D0F0xCC_x01_SetPowEn_OFFSET);
EngineList = PcieConfigGetChildEngine (Silicon);
while (EngineList != NULL) {
if (PcieConfigIsPcieEngine (EngineList)) {
GnbLibPciIndirectRMW (
Silicon->Address.AddressValue | D0F0xC8_ADDRESS,
D0F0xCC_x01_ADDRESS | ((EngineList->Type.Port.NativeDevNumber << 3 | EngineList->Type.Port.NativeFunNumber) << D0F0xC8_NB_DEV_IND_SEL_OFFSET),
AccessS3SaveWidth32,
(UINT32)~(D0F0xCC_x01_BridgeDis_MASK | D0F0xCC_x01_CfgDis_MASK | D0F0xCC_x01_CsrEnable_MASK | D0F0xCC_x01_SetPowEn_MASK),
Value,
GnbLibGetHeader (Pcie)
);
}
EngineList = (PCIe_ENGINE_CONFIG *) PcieConfigGetNextTopologyDescriptor (EngineList, DESCRIPTOR_TERMINATE_GNB);
}
}
/**
* Execute/clean up reconfiguration
*
*
* @param[in] Wrapper Pointer to wrapper config descriptor
* @param[in] Pcie Pointer to global PCIe configuration
*/
VOID
PcieTopologyExecuteReconfigV4 (
IN PCIe_WRAPPER_CONFIG *Wrapper,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
D0F0xE4_WRAP_8062_STRUCT D0F0xE4_WRAP_8062;
PCIe_SILICON_CONFIG *Silicon;
if (PcieLibIsPcieWrapper (Wrapper)) {
IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyExecuteReconfigV4 Enter\n");
PcieTopologyInitSrbmReset (FALSE, Wrapper, Pcie);
D0F0xE4_WRAP_8062.Value = PcieRegisterRead (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS),
Pcie
);
D0F0xE4_WRAP_8062.Field.ReconfigureEn = 0x1;
PcieRegisterWrite (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS),
D0F0xE4_WRAP_8062.Value,
FALSE,
Pcie
);
Silicon = PcieConfigGetParentSilicon (Wrapper);
GnbLibPciIndirectRMW (
Silicon->Address.AddressValue | D0F0xB8_ADDRESS,
D0F0xBC_x1F630_ADDRESS,
AccessWidth32,
(UINT32) ~D0F0xBC_x1F630_RECONF_WRAPPER_MASK,
Wrapper->WrapId << D0F0xBC_x1F630_RECONF_WRAPPER_OFFSET,
GnbLibGetHeader (Pcie)
);
GnbSmuServiceRequestV4 (
Silicon->Address,
SMC_MSG_RECONFIGURE,
0,
GnbLibGetHeader (Pcie)
);
D0F0xE4_WRAP_8062.Field.ConfigXferMode = 0x1;
D0F0xE4_WRAP_8062.Field.ReconfigureEn = 0x0;
PcieRegisterWrite (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS),
D0F0xE4_WRAP_8062.Value,
FALSE,
Pcie
);
PcieTopologyInitSrbmReset (TRUE, Wrapper, Pcie);
IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyExecuteReconfigV4 Exit\n");
}
}
VOID
PcieSiliconHidePorts (
IN PCIe_SILICON_CONFIG *Silicon,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
D0F0x64_x0C_STRUCT D0F0x64_x0C;
PCIe_WRAPPER_CONFIG *WrapperList;
D0F0x64_x0C.Value = 0;
IDS_HDT_CONSOLE (GNB_TRACE, "PcieSiliconHidePorts Enter\n");
D0F0x64_x0C.Value = BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7;
WrapperList = PcieConfigGetChildWrapper (Silicon);
while (WrapperList != NULL) {
PCIe_ENGINE_CONFIG *EngineList;
EngineList = PcieConfigGetChildEngine (WrapperList);
while (EngineList != NULL) {
if (PcieConfigIsPcieEngine (EngineList)) {
if (PcieConfigIsActivePcieEngine (EngineList) && !PcieConfigIsSbPcieEngine (EngineList)) {
D0F0x64_x0C.Value &= ~(1 << EngineList->Type.Port.Address.Address.Device);
}
}
EngineList = PcieLibGetNextDescriptor (EngineList);
}
WrapperList = PcieLibGetNextDescriptor (WrapperList);
}
GnbLibPciIndirectRMW (
Silicon->Address.AddressValue | D0F0x60_ADDRESS,
D0F0x64_x0C_ADDRESS | IOC_WRITE_ENABLE,
AccessS3SaveWidth32,
(UINT32)~(BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7),
D0F0x64_x0C.Value,
GnbLibGetHeader (Pcie)
);
GnbLibPciIndirectRMW (
Silicon->Address.AddressValue | D0F0x60_ADDRESS,
D0F0x64_x00_ADDRESS | IOC_WRITE_ENABLE,
AccessS3SaveWidth32,
(UINT32)~BIT6,
0x0,
GnbLibGetHeader (Pcie)
);
IDS_HDT_CONSOLE (GNB_TRACE, "Write D0F0x64_x0C.Value = %x\n", D0F0x64_x0C.Value);
IDS_HDT_CONSOLE (GNB_TRACE, "PcieSiliconHidePorts Exit\n");
}
VOID
PcieSiliconHidePorts (
IN PCIe_SILICON_CONFIG *Silicon,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
D0F0x64_x0C_STRUCT D0F0x64_x0C;
PCIe_WRAPPER_CONFIG *WrapperList;
D0F0x64_x0C.Value = 0;
WrapperList = PcieSiliconGetWrapperList (Silicon);
while (WrapperList != NULL) {
PCIe_ENGINE_CONFIG *EngineList;
EngineList = PcieWrapperGetEngineList (WrapperList);
while (EngineList != NULL) {
if (EngineList->EngineData.EngineType == PciePortEngine) {
if (!PcieConfigCheckPortStatus (EngineList, INIT_STATUS_PCIE_TRAINING_SUCCESS) &&
((EngineList->Type.Port.PortData.LinkHotplug == HotplugDisabled) || (EngineList->Type.Port.PortData.LinkHotplug == HotplugInboard)) &&
!EngineList->Type.Port.IsSB) {
D0F0x64_x0C.Value |= 1 << EngineList->Type.Port.NativeDevNumber;
}
}
EngineList = PcieLibGetNextDescriptor (EngineList);
}
WrapperList = PcieLibGetNextDescriptor (WrapperList);
}
GnbLibPciIndirectRMW (
Silicon->Address.AddressValue | D0F0x60_ADDRESS,
D0F0x64_x0C_ADDRESS | IOC_WRITE_ENABLE,
AccessS3SaveWidth32,
~(UINT32)(BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7),
D0F0x64_x0C.Value,
GnbLibGetHeader (Pcie)
);
GnbLibPciIndirectRMW (
Silicon->Address.AddressValue | D0F0x60_ADDRESS,
D0F0x64_x00_ADDRESS | IOC_WRITE_ENABLE,
AccessS3SaveWidth32,
~(UINT32)BIT6,
0x0,
GnbLibGetHeader (Pcie)
);
}
VOID
PcieSiliconUnHidePorts (
IN PCIe_SILICON_CONFIG *Silicon,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
GnbLibPciIndirectRMW (
Silicon->Address.AddressValue | D0F0x60_ADDRESS,
D0F0x64_x0C_ADDRESS | IOC_WRITE_ENABLE,
AccessS3SaveWidth32,
(UINT32)~(BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7),
0x0,
GnbLibGetHeader (Pcie)
);
GnbLibPciIndirectRMW (
Silicon->Address.AddressValue | D0F0x60_ADDRESS,
D0F0x64_x00_ADDRESS | IOC_WRITE_ENABLE,
AccessS3SaveWidth32,
(UINT32)~BIT6,
BIT6,
GnbLibGetHeader (Pcie)
);
}
VOID
PcieFmEnableSlotPowerLimit (
IN PCIe_ENGINE_CONFIG *Engine,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
ASSERT (Engine->EngineData.EngineType == PciePortEngine);
if (PcieLibIsEngineAllocated (Engine) && Engine->Type.Port.PortData.PortPresent != PortDisabled && !Engine->Type.Port.IsSB) {
IDS_HDT_CONSOLE (PCIE_MISC, " Enable Slot Power Limit for Port % d\n", Engine->Type.Port.Address.Address.Device);
GnbLibPciIndirectRMW (
MAKE_SBDFO (0, 0, 0, 0, D0F0x60_ADDRESS),
(D0F0x64_x55_ADDRESS + (Engine->Type.Port.Address.Address.Device - 4) * 2) | IOC_WRITE_ENABLE,
AccessS3SaveWidth32,
0xffffffff,
1 << D0F0x64_x55_SetPowEn_OFFSET,
GnbLibGetHeader (Pcie)
);
}
}
/**
* Satic init for various registers.
*
*
*
* @param[in] Pcie Pointer to global PCIe configuration
*/
VOID
STATIC
PcieEarlyStaticInitTN (
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
UINTN Index;
for (Index = 0; Index < PcieInitEarlyTableTN.Length; Index++) {
GnbLibPciIndirectRMW (
MAKE_SBDFO (0,0,0,0, D0F0xE0_ADDRESS),
PcieInitEarlyTableTN.Table[Index].Reg,
AccessWidth32,
(UINT32)~PcieInitEarlyTableTN.Table[Index].Mask,
PcieInitEarlyTableTN.Table[Index].Data,
GnbLibGetHeader (Pcie)
);
}
}
VOID
PcieEnableSlotPowerLimitV5 (
IN PCIe_ENGINE_CONFIG *Engine,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
PCIe_SILICON_CONFIG *Silicon;
if (PcieLibIsEngineAllocated (Engine) && Engine->Type.Port.PortData.PortPresent != PortDisabled && !PcieConfigIsSbPcieEngine (Engine)) {
IDS_HDT_CONSOLE (PCIE_MISC, " Enable Slot Power Limit for Port % d\n", Engine->Type.Port.Address.Address.Device);
Silicon = PcieConfigGetParentSilicon (Engine);
GnbLibPciIndirectRMW (
Silicon->Address.AddressValue | D0F0xC8_ADDRESS,
D0F0xCC_x01_ADDRESS | ((Engine->Type.Port.PortData.DeviceNumber << 3 | Engine->Type.Port.PortData.FunctionNumber) << D0F0xC8_NB_DEV_IND_SEL_OFFSET),
AccessS3SaveWidth32,
0xffffffff,
1 << D0F0xCC_x01_SetPowEn_OFFSET,
GnbLibGetHeader (Pcie)
);
}
}
AGESA_STATUS
PcieFmMapPortPciAddress (
IN PCIe_ENGINE_CONFIG *Engine,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
PCIe_WRAPPER_CONFIG *Wrapper;
UINT64 ConfigurationSignature;
Wrapper = PcieEngineGetParentWrapper (Engine);
if (Wrapper->WrapId == GPP_WRAP_ID) {
ConfigurationSignature = PcieConfigGetConfigurationSignature (Wrapper, Engine->Type.Port.CoreId);
if ((ConfigurationSignature == GPP_CORE_x4x2x1x1_ST) || (ConfigurationSignature == GPP_CORE_x4x2x2_ST)) {
//Enable device remapping
GnbLibPciIndirectRMW (
MAKE_SBDFO (0, 0, 0, 0, D0F0x60_ADDRESS),
0x20 | IOC_WRITE_ENABLE,
AccessS3SaveWidth32,
~(UINT32) (1 << 1),
0x0,
GnbLibGetHeader (Pcie)
);
}
}
if (Engine->Type.Port.PortData.DeviceNumber == 0 && Engine->Type.Port.PortData.FunctionNumber == 0) {
Engine->Type.Port.PortData.DeviceNumber = Engine->Type.Port.NativeDevNumber;
Engine->Type.Port.PortData.FunctionNumber = Engine->Type.Port.NativeFunNumber;
return AGESA_SUCCESS;
}
if (Engine->Type.Port.PortData.DeviceNumber == Engine->Type.Port.NativeDevNumber &&
Engine->Type.Port.PortData.FunctionNumber == Engine->Type.Port.NativeFunNumber) {
return AGESA_SUCCESS;
}
return AGESA_ERROR;
}
/**
* Per wrapper Pcie Init prior training.
*
*
* @param[in] Wrapper Pointer to wrapper configuration descriptor
* @param[in] Buffer Pointer buffer
* @param[in] Pcie Pointer to global PCIe configuration
*/
AGESA_STATUS
STATIC
PcieEarlyInitCallbackCZ (
IN PCIe_WRAPPER_CONFIG *Wrapper,
IN OUT VOID *Buffer,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
AGESA_STATUS Status;
BOOLEAN CoreConfigChanged;
BOOLEAN PllConfigChanged;
BOOLEAN AriSupportEnable;
GNB_BUILD_OPTIONS_CZ *GnbBuildOptionData;
IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyInitCallbackCZ Enter\n");
CoreConfigChanged = FALSE;
PllConfigChanged = FALSE;
GnbBuildOptionData = GnbLocateHeapBuffer (AMD_GNB_BUILD_OPTIONS_HANDLE, GnbLibGetHeader (Pcie));
ASSERT (GnbBuildOptionData != NULL);
AriSupportEnable = GnbBuildOptionData->CfgAriSupport;
if (AriSupportEnable == TRUE) {
// Enable Alternative Routing-ID Interpretation
GnbLibPciIndirectRMW (
MAKE_SBDFO (0,0,0,0, D0F0x60_ADDRESS),
D0F0x64_x46_ADDRESS,
AccessWidth32,
(UINT32)~D0F0x64_x46_IocAriSupported_MASK,
(1 << D0F0x64_x46_IocAriSupported_OFFSET),
GnbLibGetHeader (Pcie)
);
PcieRegisterRMW (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_0000_ADDRESS),
D0F0xE4_WRAP_0000_StrapBif2AriEn_MASK,
(1 << D0F0xE4_WRAP_0000_StrapBif2AriEn_OFFSET),
TRUE,
Pcie
);
}
if (GnbBuildOptionData->CfgACSEnable == TRUE) {
// Enable Access Control Services
PcieRegisterRMW (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_000A_ADDRESS),
0xFFFFFFF8,
(BIT0 | BIT1 | BIT2),
TRUE,
Pcie
);
}
IDS_OPTION_HOOK (IDS_BEFORE_RECONFIGURATION, Pcie, (AMD_CONFIG_PARAMS *)Pcie->StdHeader);
PcieTopologyPrepareForReconfigCZ (Wrapper, Pcie); //step 2
Status = PcieTopologySetCoreConfigCZ (Wrapper, &CoreConfigChanged, Pcie); //step 3
ASSERT (Status == AGESA_SUCCESS);
PcieTopologyApplyLaneMuxCZ (Wrapper, Pcie); //step 4
// PciePifSetRxDetectPowerMode (Wrapper, Pcie);
// PciePifSetLs2ExitTime (Wrapper, Pcie);
// PciePifApplyGanging (Wrapper, Pcie);
// PciePhyApplyGangingCZ (Wrapper, Pcie);
PcieTopologySelectMasterPllCZ (Wrapper, &PllConfigChanged, Pcie); //step 5
if (CoreConfigChanged) {
PcieTopologyExecuteReconfigCZ (Wrapper, Pcie); // step 6
}
PcieEarlyWrapperTxPresetLoadingSequenceCZ (Wrapper, Pcie);
PcieTopologyCleanUpReconfigCZ (Wrapper, Pcie); // step 7
PcieTopologySetLinkReversalV4 (Wrapper, Pcie); // step 8
// PciePifPllConfigureCZ (Wrapper, Pcie);
PcieTopologyLaneControlCZ (
DisableLanes,
PcieUtilGetWrapperLaneBitMap (LANE_TYPE_CORE_ALL, LANE_TYPE_PCIE_CORE_ALLOC, Wrapper),
Wrapper,
Pcie
); //step 9
// PciePollPifForCompeletion (Wrapper, Pcie);
// PciePhyAvertClockPickersCZ (Wrapper, Pcie);
PcieEarlyCoreInitCZ (Wrapper, Pcie);
PcieSetSsidCZ (UserOptions.CfgGnbPcieSSID, Wrapper, Pcie);
PcieHwInitPowerGatingCZ (Wrapper, Pcie);
IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyInitCallbackCZ Exit [%x]\n", Status);
return Status;
}
AGESA_STATUS
NbInitOnPowerOn (
IN GNB_PLATFORM_CONFIG *Gnb
)
{
UINTN Index;
FCRxFF30_0398_STRUCT FCRxFF30_0398;
UINT32 Value;
// Init NBCONFIG
for (Index = 0; Index < (sizeof (NbPciInitTable) / sizeof (NB_REGISTER_ENTRY)); Index++) {
GnbLibPciRMW (
Gnb->GnbPciAddress.AddressValue | NbPciInitTable[Index].Reg,
AccessWidth32,
NbPciInitTable[Index].Mask,
NbPciInitTable[Index].Data,
Gnb->StdHeader
);
}
// Init MISCIND
for (Index = 0; Index < (sizeof (NbMiscInitTable) / sizeof (NB_REGISTER_ENTRY)); Index++) {
GnbLibPciIndirectRMW (
Gnb->GnbPciAddress.AddressValue | D0F0x60_ADDRESS,
NbMiscInitTable[Index].Reg | IOC_WRITE_ENABLE,
AccessWidth32,
NbMiscInitTable[Index].Mask,
NbMiscInitTable[Index].Data,
Gnb->StdHeader
);
}
// Init ORB
for (Index = 0; Index < (sizeof (NbOrbInitTable) / sizeof (NB_REGISTER_ENTRY)); Index++) {
GnbLibPciIndirectRMW (
Gnb->GnbPciAddress.AddressValue | D0F0x94_ADDRESS,
NbOrbInitTable[Index].Reg | (1 << D0F0x94_OrbIndWrEn_OFFSET),
AccessWidth32,
NbOrbInitTable[Index].Mask,
NbOrbInitTable[Index].Data,
Gnb->StdHeader
);
}
if (!GfxLibIsControllerPresent (Gnb->StdHeader)) {
FCRxFF30_0398.Value = (1 << FCRxFF30_0398_SoftResetGrbm_OFFSET) | (1 << FCRxFF30_0398_SoftResetMc_OFFSET) |
(1 << FCRxFF30_0398_SoftResetDc_OFFSET) | (1 << FCRxFF30_0398_SoftResetRlc_OFFSET) |
(1 << FCRxFF30_0398_SoftResetUvd_OFFSET);
NbSmuSrbmRegisterWrite (FCRxFF30_0398_ADDRESS, &FCRxFF30_0398.Value, FALSE, Gnb->StdHeader);
}
Value = 0;
for (Index = 0x8400; Index <= 0x85AC; Index = Index + 4) {
NbSmuRcuRegisterWrite (
(UINT16) Index,
&Value,
1,
FALSE,
Gnb->StdHeader
);
}
NbSmuRcuRegisterWrite (
0x9000,
&Value,
1,
FALSE,
Gnb->StdHeader
);
NbSmuRcuRegisterWrite (
0x9004,
&Value,
1,
FALSE,
Gnb->StdHeader
);
return AGESA_SUCCESS;
}
SCAN_STATUS
PcieAspmCallback (
IN PCI_ADDR Device,
IN OUT GNB_PCI_SCAN_DATA *ScanData
)
{
SCAN_STATUS ScanStatus;
PCIE_ASPM_DATA *PcieAspmData;
PCIE_DEVICE_TYPE DeviceType;
ScanStatus = SCAN_SUCCESS;
IDS_HDT_CONSOLE (GNB_TRACE, " PcieAspmCallback for Device = %d:%d:%d\n",
Device.Address.Bus,
Device.Address.Device,
Device.Address.Function
);
PcieAspmData = (PCIE_ASPM_DATA *) ScanData;
ScanStatus = SCAN_SUCCESS;
DeviceType = GnbLibGetPcieDeviceType (Device, ScanData->StdHeader);
switch (DeviceType) {
case PcieDeviceRootComplex:
case PcieDeviceDownstreamPort:
PcieAspmData->DownstreamPort = Device;
//PcieExitLatencyData->LinkCount++;
GnbLibPciRMW (Device.AddressValue | 0x18, AccessS3SaveWidth32, 0xffffffffull, 0x0, ScanData->StdHeader);
GnbLibPciScanSecondaryBus (Device, &PcieAspmData->ScanData);
//PcieExitLatencyData->LinkCount--;
//Pcie ASPM Black List for L0s with HW method change
if ((DeviceType == PcieDeviceRootComplex) && (PcieAspmData->AspmL0sBlackList == TRUE)) {
IDS_HDT_CONSOLE (GNB_TRACE, " Black List L0s disabled = %d:%d:%d\n", Device.Address.Bus, Device.Address.Device, Device.Address.Function);
GnbLibPciIndirectRMW (Device.AddressValue | 0xE0, 0xA0, AccessS3SaveWidth32, 0xfffff0ff, 0, ScanData->StdHeader);
}
break;
case PcieDeviceUpstreamPort:
excel950_fun0 (
PcieAspmData->DownstreamPort,
Device,
PcieAspmData->Aspm,
&PcieAspmData->AspmL0sBlackList,
ScanData->StdHeader
);
GnbLibPciRMW (Device.AddressValue | 0x18, AccessS3SaveWidth32, 0xffffffffull, 0x0, ScanData->StdHeader);
GnbLibPciScanSecondaryBus (Device, &PcieAspmData->ScanData);
ScanStatus = SCAN_SKIP_FUNCTIONS | SCAN_SKIP_DEVICES | SCAN_SKIP_BUSES;
break;
case PcieDeviceEndPoint:
case PcieDeviceLegacyEndPoint:
excel950_fun0 (
PcieAspmData->DownstreamPort,
Device,
PcieAspmData->Aspm,
&PcieAspmData->AspmL0sBlackList,
ScanData->StdHeader
);
ScanStatus = SCAN_SKIP_FUNCTIONS | SCAN_SKIP_DEVICES | SCAN_SKIP_BUSES;
break;
default:
break;
}
return ScanStatus;
}
