/**************************************************************************************************
* @fn halKeyPort0Isr
*
* @brief Port0 ISR
*
* @param
*
* @return
**************************************************************************************************/
HAL_ISR_FUNCTION( halKeyPort0Isr, P0INT_VECTOR )
{
HAL_ENTER_ISR();
if ((HAL_KEY_LINK_PXIFG & HAL_KEY_LINK_BIT))
{
halProcessKeyInterrupt();
}
/*
Clear the CPU interrupt flag for Port_0
PxIFG has to be cleared before PxIF
*/
HAL_KEY_LINK_PXIFG = 0;
HAL_KEY_LINK_CPU_PORT_0_IF = 0;
CLEAR_SLEEP_MODE();
HAL_EXIT_ISR();
}
/**************************************************************************************************
* @fn halKeyPort1Isr
*
* @brief Port1 ISR
*
* @param
*
* @return
**************************************************************************************************/
HAL_ISR_FUNCTION( ButtonDownIsr, P1INT_VECTOR )
{
HAL_ENTER_ISR();
if(P1IFG & 0x04)
{
P1IFG &= 0xFB; //clear interrupt flag
IRCON2 &= 0xF7; //clear CPU interrupt flag
osal_start_timerEx (MiniBeacon_TaskID, SBP_BUTTON_DOWN_EVT, 25);
}
CLEAR_SLEEP_MODE();
HAL_EXIT_ISR();
return;
}
/**************************************************************************************************
* @fn halKeyPort2Isr
*
* @brief Port2 ISR
*
* @param
*
* @return
**************************************************************************************************/
HAL_ISR_FUNCTION( halKeyPort2Isr, P2INT_VECTOR )
{
HAL_ENTER_ISR();
if (HAL_KEY_JOY_MOVE_PXIFG & HAL_KEY_JOY_MOVE_BIT)
{
halProcessKeyInterrupt();
}
/*
Clear the CPU interrupt flag for Port_2
PxIFG has to be cleared before PxIF
Notes: P2_1 and P2_2 are debug lines.
*/
HAL_KEY_JOY_MOVE_PXIFG = 0;
HAL_KEY_CPU_PORT_2_IF = 0;
CLEAR_SLEEP_MODE();
HAL_EXIT_ISR();
}
HAL_ISR_FUNCTION(halUart1TxIsr, UTX1_VECTOR)
#endif
{
HAL_ENTER_ISR();
if (dmaCfg.txHead == dmaCfg.txTail) {
IEN2 &= ~UTXxIE;
dmaCfg.txMT = 1;
} else {
UTXxIF = 0;
UxDBUF = dmaCfg.txBuf[dmaCfg.txHead++];
if ((HAL_UART_DMA_TX_MAX != 256) && (dmaCfg.txHead >= HAL_UART_DMA_TX_MAX))
{
dmaCfg.txHead = 0;
}
}
HAL_EXIT_ISR();
}
/******************************************************************************
* @fn HalDMAInit
*
* @brief DMA Interrupt Service Routine
*
* @param None
*
* @return None
*****************************************************************************/
HAL_ISR_FUNCTION( halDmaIsr, DMA_VECTOR )
{
extern void HalUARTIsrDMA(void);
HAL_ENTER_ISR();
DMAIF = 0;
#if HAL_UART_DMA
if (HAL_DMA_CHECK_IRQ(HAL_DMA_CH_TX))
{
HalUARTIsrDMA();
}
#endif // HAL_UART_DMA
#if (defined HAL_SPI) && (HAL_SPI == TRUE)
if ( HAL_DMA_CHECK_IRQ( HAL_DMA_CH_RX ) )
{
HAL_DMA_CLEAR_IRQ( HAL_DMA_CH_RX );
HalSpiRxIsr();
}
if ( HAL_DMA_CHECK_IRQ( HAL_DMA_CH_TX ) )
{
HAL_DMA_CLEAR_IRQ( HAL_DMA_CH_TX );
HalSpiTxIsr();
}
#endif // (defined HAL_SPI) && (HAL_SPI == TRUE)
#if (defined HAL_IRGEN) && (HAL_IRGEN == TRUE)
if ( HAL_IRGEN == TRUE && HAL_DMA_CHECK_IRQ( HAL_IRGEN_DMA_CH ) )
{
HAL_DMA_CLEAR_IRQ( HAL_IRGEN_DMA_CH );
HalIrGenDmaIsr();
}
#endif // (defined HAL_IRGEN) && (HAL_IRGEN == TRUE)
CLEAR_SLEEP_MODE();
HAL_EXIT_ISR();
}
/*
******************************************************************************
* @fn halKeyPort1Isr
*
* @brief Port1 ISR
******************************************************************************
*/
HAL_ISR_FUNCTION(halKeyPort1Isr, P1INT_VECTOR)
{
HAL_ENTER_ISR();
// if ((HAL_KEY_SW_2_PXIFG & HAL_KEY_SW_2_BIT) || (HAL_KEY_SW_3_PXIFG & HAL_KEY_SW_3_BIT)) {
// halProcessKeyInterrupt();
// }
if (BATCD_PXIFG & BATCD_BV) {
batt_isr();
}
#ifdef POWER_SAVING
CLEAR_SLEEP_MODE();
#endif
/*
* Clear the CPU interrupt flag for Port_1
* PxIFG has to be cleared before PxIF
*/
P1IFG = 0;
P1IF = 0;
HAL_EXIT_ISR();
}
HAL_ISR_FUNCTION(port1Isr, P1INT_VECTOR)
#endif
{
HAL_ENTER_ISR();
PxIFG = 0;
PxIF = 0;
dmaRdyIsr = 1;
#ifdef POWER_SAVING
CLEAR_SLEEP_MODE();
osal_pwrmgr_task_state(Hal_TaskID, PWRMGR_HOLD);
#if HAL_UART_TX_BY_ISR
if (dmaCfg.txHead == dmaCfg.txTail) {
HAL_UART_DMA_CLR_RDY_OUT();
}
#endif
#endif
HAL_EXIT_ISR();
}
HAL_ISR_FUNCTION(port0Isr, P0INT_VECTOR)
{
unsigned char status;
unsigned char i;
HAL_ENTER_ISR();
status = P0IFG;
status &= P0IEN;
if (status)
{
P0IFG = ~status;
P0IF = 0;
#if HAL_UART_DMA == 1
extern uint8 Hal_TaskID;
extern volatile uint8 dmaRdyIsr;
dmaRdyIsr = 1;
CLEAR_SLEEP_MODE();
osal_pwrmgr_task_state(Hal_TaskID, PWRMGR_HOLD);
#if HAL_UART_TX_BY_ISR
if (dmaCfg.txHead == dmaCfg.txTail)
{
HAL_UART_DMA_CLR_RDY_OUT();
}
#endif
#endif // HAL_UART_DMA
for (i = 0; i < OS_MAX_INTERRUPT; i++)
{
if (PIN_MAJOR(blueBasic_interrupts[i].pin) == 0 && (status & (1 << PIN_MINOR(blueBasic_interrupts[i].pin))))
{
osal_set_event(blueBasic_TaskID, BLUEBASIC_EVENT_INTERRUPT << i);
}
}
}
HAL_EXIT_ISR();
}
HAL_ISR_FUNCTION( halUart1TxIsr, UTX1_VECTOR )
#endif
{
HAL_ENTER_ISR();
if (isrCfg.txHead == isrCfg.txTail)
{
IEN2 &= ~UTXxIE;
isrCfg.txMT = 1;
}
else
{
UTXxIF = 0;
UxDBUF = isrCfg.txBuf[isrCfg.txHead++];
if (isrCfg.txHead >= HAL_UART_ISR_TX_MAX)
{
isrCfg.txHead = 0;
}
}
HAL_EXIT_ISR();
}
HAL_ISR_FUNCTION( halUart1RxIsr, URX1_VECTOR )
#endif
{
HAL_ENTER_ISR();
uint8 tmp = UxDBUF;
isrCfg.rxBuf[isrCfg.rxTail] = tmp;
// Re-sync the shadow on any 1st byte received.
if (isrCfg.rxHead == isrCfg.rxTail)
{
isrCfg.rxShdw = ST0;
}
if (++isrCfg.rxTail >= HAL_UART_ISR_RX_MAX)
{
isrCfg.rxTail = 0;
}
isrCfg.rxTick = HAL_UART_ISR_IDLE;
HAL_EXIT_ISR();
}
