void
do_caches(int argc, char *argv[])
{
unsigned long oldints;
int dcache_on=0, icache_on=0;
if (argc == 2) {
if (strcasecmp(argv[1], "on") == 0) {
HAL_DISABLE_INTERRUPTS(oldints);
HAL_ICACHE_ENABLE();
HAL_DCACHE_ENABLE();
HAL_RESTORE_INTERRUPTS(oldints);
} else if (strcasecmp(argv[1], "off") == 0) {
HAL_DISABLE_INTERRUPTS(oldints);
HAL_DCACHE_SYNC();
HAL_ICACHE_DISABLE();
HAL_DCACHE_DISABLE();
HAL_DCACHE_SYNC();
HAL_ICACHE_INVALIDATE_ALL();
HAL_DCACHE_INVALIDATE_ALL();
HAL_RESTORE_INTERRUPTS(oldints);
} else {
diag_printf("Invalid cache mode: %s\n", argv[1]);
}
} else {
#ifdef HAL_DCACHE_IS_ENABLED
HAL_DCACHE_IS_ENABLED(dcache_on);
#endif
#ifdef HAL_ICACHE_IS_ENABLED
HAL_ICACHE_IS_ENABLED(icache_on);
#endif
diag_printf("Data cache: %s, Instruction cache: %s\n",
dcache_on?"On":"Off", icache_on?"On":"Off");
}
}
void hal_hardware_init(void)
{
hal_xscale_core_init();
*PXA2X0_ICMR = 0; // IRQ Mask
*PXA2X0_ICLR = 0; // Route interrupts to IRQ
*PXA2X0_ICCR = 1;
*PXA2X0_GRER0 = 0; // Disable rising edge detect
*PXA2X0_GRER1 = 0;
*PXA2X0_GRER2 = 0;
*PXA2X0_GFER0 = 0; // Disable falling edge detect
*PXA2X0_GFER1 = 0;
*PXA2X0_GFER2 = 0;
*PXA2X0_GEDR0 = 0xffffffff; // Clear edge detect status
*PXA2X0_GEDR1 = 0xffffffff;
*PXA2X0_GEDR2 = 0x0001ffff;
plf_hardware_init(); // Perform any platform specific initializations
*PXA2X0_OSCR = 0; // Let the "OS" counter run
*PXA2X0_OSMR0 = 0;
hal_if_init(); // Set up eCos/ROM interfaces
HAL_DCACHE_ENABLE(); // Enable caches
HAL_ICACHE_ENABLE();
}
void
hal_hardware_init(void)
{
hal_xscale_core_init();
// all interrupt sources to IRQ and disabled
*IXP425_INTR_SEL = 0;
*IXP425_INTR_EN = 0;
// Enable caches
HAL_DCACHE_ENABLE();
HAL_ICACHE_ENABLE();
// Let the timer run at a default rate (for delays)
hal_clock_initialize(CYGNUM_HAL_RTC_PERIOD);
// Set up eCos/ROM interfaces
hal_if_init();
// Perform any platform specific initializations
plf_hardware_init();
#ifdef CYGPKG_IO_PCI
cyg_hal_plf_pci_init();
#endif
}
void hal_hardware_init(void)
{
#if 0
// Clear and initialize instruction cache
HAL_ICACHE_INVALIDATE_ALL();
HAL_ICACHE_ENABLE();
#endif
// Any hardware/platform initialization that needs to be done.
// Reset all interrupt masks (disable all interrupt sources)
*(volatile cyg_uint8 *)CMA230_IMRw = 0;
*(volatile cyg_uint8 *)CMA230_CLR = 0xFF; // Clear all current interrupts
// Set up eCos/ROM interfaces
hal_if_init();
}
void
hal_platform_init(void)
{
HAL_WRITE_UINT32(AR531X_WDC, 0);
hal_ar5312_flash_setup();
// Set up eCos/ROM interfaces
hal_if_init();
HAL_ICACHE_INVALIDATE_ALL();
HAL_ICACHE_ENABLE();
HAL_DCACHE_INVALIDATE_ALL();
HAL_DCACHE_ENABLE();
}
void hal_hardware_init(void)
{
hal_xscale_core_init();
*PXA2X0_ICMR = 0; // IRQ Mask
*PXA2X0_ICLR = 0; // Route interrupts to IRQ
*PXA2X0_ICCR = 1;
*PXA2X0_GRER0 = 0; // Disable rising edge detect
*PXA2X0_GRER1 = 0;
*PXA2X0_GRER2 = 0;
*PXA2X0_GFER0 = 0; // Disable falling edge detect
*PXA2X0_GFER1 = 0;
*PXA2X0_GFER2 = 0;
#if defined(CYGOPT_HAL_ARM_XSCALE_PXA2X0_VARIANT_PXA25X)
*PXA2X0_GEDR0 = 0xffffffff; // Clear edge detect status
*PXA2X0_GEDR1 = 0xffffffff;
*PXA2X0_GEDR2 = 0x0001ffff;
#elif defined(CYGOPT_HAL_ARM_XSCALE_PXA2X0_VARIANT_PXA27X)
*PXA2X0_ICMR2 = 0;
*PXA2X0_ICLR2 = 0;
*PXA2X0_GRER3 = 0;
*PXA2X0_GFER3 = 0;
*PXA2X0_GEDR0 = 0xfffff71b;
*PXA2X0_GEDR1 = 0xffffffff;
*PXA2X0_GEDR2 = 0xffffffff;
*PXA2X0_GEDR3 = 0x1fffffff;
#endif
plf_hardware_init(); // Perform any platform specific initializations
*PXA2X0_OSCR = 0; // Let the "OS" counter run
*PXA2X0_OSMR0 = 0;
#ifdef CYGSEM_HAL_ENABLE_DCACHE_ON_STARTUP
HAL_DCACHE_ENABLE(); // Enable caches
#endif
#ifdef CYGSEM_HAL_ENABLE_ICACHE_ON_STARTUP
HAL_ICACHE_ENABLE();
#endif
}
void hal_variant_init( void )
{
hal_update_clock_var();
#if defined CYGPKG_HAL_KINETIS_CACHE
# ifndef CYG_HAL_STARTUP_RAM
hal_cortexm_kinetis_conf_cache_regions(CYGHWR_HAL_KINETIS_LMEM_PS_P,
sizeof(cache_reg_modes)/sizeof(cache_reg_modes[0]),
cache_reg_modes);
hal_cortexm_kinetis_conf_cache_regions(CYGHWR_HAL_KINETIS_LMEM_PC_P,
sizeof(cache_reg_modes)/sizeof(cache_reg_modes[0]),
cache_reg_modes);
# endif
# ifdef ENABLE_CACHE_ON_STARTUP
HAL_DCACHE_ENABLE();
HAL_ICACHE_ENABLE();
# endif
#endif // defined CYGPKG_HAL_KINETIS_CACHE
#ifdef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
hal_if_init();
#endif
}
void hal_platform_init(void)
{
// Note that the hardware seems to come up with the
// caches containing random data. Hence they must be
// invalidated before being enabled.
HAL_ICACHE_INVALIDATE_ALL();
HAL_ICACHE_ENABLE();
HAL_DCACHE_INVALIDATE_ALL();
HAL_DCACHE_ENABLE();
#if defined(CYGPKG_KERNEL) && \
defined(CYGFUN_HAL_COMMON_KERNEL_SUPPORT) && \
defined(CYGSEM_HAL_USE_ROM_MONITOR_CygMon)
{
extern CYG_ADDRESS hal_virtual_vector_table[32];
extern void patch_dbg_syscalls(void * vector);
patch_dbg_syscalls( (void *)(&hal_virtual_vector_table[0]) );
}
#endif
}
int
flash_hwr_init(void)
{
struct FLASH_query data, *qp;
extern char flash_query, flash_query_end;
typedef int code_fun(unsigned char *);
code_fun *_flash_query;
int code_len, stat, num_regions, region_size, icache_isenabled;
// Copy 'program' code to RAM for execution
code_len = (unsigned long)&flash_query_end - (unsigned long)&flash_query;
_flash_query = (code_fun *)flash_info.work_space;
memcpy(_flash_query, &flash_query, code_len);
HAL_ICACHE_IS_ENABLED(icache_isenabled);
HAL_DCACHE_SYNC(); // Should guarantee this code will run
HAL_ICACHE_DISABLE(); // is also required to avoid old contents
memset(&data,0,sizeof(data));
stat = (*_flash_query)((void*)&data);
if (icache_isenabled)
HAL_ICACHE_ENABLE();
qp = &data;
if (/*(qp->manuf_code == FLASH_Intel_code) && */
(strncmp(qp->id, "QRY", 3) == 0)) {
num_regions = _si(qp->num_regions)+1;
region_size = _si(qp->region_size)*256;
flash_info.block_size = region_size;
flash_info.blocks = num_regions;
flash_info.start = (void *)0x00000000;
flash_info.end = (void *)(0x00000000+(num_regions*region_size));
return FLASH_ERR_OK;
} else {
(*flash_info.pf)("Can't identify FLASH sorry\n");
diag_dump_buf(data, sizeof(data));
return FLASH_ERR_HWR;
}
}
int
flash_hwr_init(void)
{
unsigned char data[96];
extern char flash_query, flash_query_end;
typedef int code_fun(unsigned char *);
code_fun *_flash_query;
int code_len, stat, num_regions, region_size, icache_isenabled;
// Copy 'program' code to RAM for execution
code_len = (unsigned long)&flash_query_end - (unsigned long)&flash_query;
_flash_query = (code_fun *)flash_info.work_space;
memcpy(_flash_query, &flash_query, code_len);
HAL_ICACHE_IS_ENABLED(icache_isenabled);
HAL_DCACHE_SYNC(); // Should guarantee this code will run
HAL_ICACHE_DISABLE(); // is also required to avoid old contents
stat = (*_flash_query)(data);
if (icache_isenabled)
HAL_ICACHE_ENABLE();
if ((data[0] == FLASH_Intel_code) &&
(data[4] == FLASH_28F016SV_low) &&
(data[5] == FLASH_28F016SV_hi)) {
num_regions = 32;
region_size = 0x20000;
flash_info.block_size = region_size;
flash_info.blocks = num_regions;
flash_info.start = (void *)0x08000000;
flash_info.end = (void *)(0x08000000+(num_regions*region_size));
return FLASH_ERR_OK;
} else {
(*flash_info.pf)("Can't identify FLASH, sorry\n");
diag_dump_buf(data, sizeof(data));
return FLASH_ERR_HWR;
}
}
static void entry0( cyg_addrword_t data )
{
register CYG_INTERRUPT_STATE oldints;
#ifdef HAL_CACHE_UNIFIED
HAL_DISABLE_INTERRUPTS(oldints);
HAL_DCACHE_PURGE_ALL(); // rely on above definition
HAL_UCACHE_INVALIDATE_ALL();
HAL_UCACHE_DISABLE();
HAL_RESTORE_INTERRUPTS(oldints);
CYG_TEST_INFO("Cache off");
time1();
HAL_DISABLE_INTERRUPTS(oldints);
HAL_DCACHE_PURGE_ALL(); // rely on above definition
HAL_UCACHE_INVALIDATE_ALL();
HAL_UCACHE_ENABLE();
HAL_RESTORE_INTERRUPTS(oldints);
CYG_TEST_INFO("Cache on");
time1();
#ifdef HAL_DCACHE_INVALIDATE_ALL
HAL_DISABLE_INTERRUPTS(oldints);
HAL_DCACHE_PURGE_ALL();
HAL_UCACHE_INVALIDATE_ALL();
HAL_UCACHE_ENABLE();
HAL_RESTORE_INTERRUPTS(oldints);
CYG_TEST_INFO("Cache on: invalidate Cache (expect bogus timing)");
time1DI();
#endif
#else // HAL_CACHE_UNIFIED
HAL_DISABLE_INTERRUPTS(oldints);
HAL_DCACHE_PURGE_ALL();
HAL_ICACHE_INVALIDATE_ALL();
HAL_DCACHE_INVALIDATE_ALL();
HAL_ICACHE_DISABLE();
HAL_DCACHE_DISABLE();
HAL_RESTORE_INTERRUPTS(oldints);
CYG_TEST_INFO("Dcache off Icache off");
time1();
HAL_DISABLE_INTERRUPTS(oldints);
HAL_DCACHE_PURGE_ALL();
HAL_ICACHE_INVALIDATE_ALL();
HAL_DCACHE_INVALIDATE_ALL();
HAL_ICACHE_DISABLE();
HAL_DCACHE_ENABLE();
HAL_RESTORE_INTERRUPTS(oldints);
CYG_TEST_INFO("Dcache on Icache off");
time1();
HAL_DISABLE_INTERRUPTS(oldints);
HAL_DCACHE_PURGE_ALL();
HAL_ICACHE_INVALIDATE_ALL();
HAL_DCACHE_INVALIDATE_ALL();
HAL_ICACHE_ENABLE();
HAL_DCACHE_DISABLE();
HAL_RESTORE_INTERRUPTS(oldints);
CYG_TEST_INFO("Dcache off Icache on");
time1();
HAL_DISABLE_INTERRUPTS(oldints);
HAL_DCACHE_PURGE_ALL();
HAL_ICACHE_INVALIDATE_ALL();
HAL_DCACHE_INVALIDATE_ALL();
HAL_ICACHE_ENABLE();
HAL_DCACHE_ENABLE();
HAL_RESTORE_INTERRUPTS(oldints);
CYG_TEST_INFO("Dcache on Icache on");
time1();
HAL_DISABLE_INTERRUPTS(oldints);
HAL_DCACHE_PURGE_ALL();
HAL_ICACHE_INVALIDATE_ALL();
HAL_DCACHE_INVALIDATE_ALL();
HAL_ICACHE_DISABLE();
HAL_DCACHE_DISABLE();
HAL_RESTORE_INTERRUPTS(oldints);
CYG_TEST_INFO("Dcache off Icache off (again)");
time1();
#if defined(HAL_DCACHE_INVALIDATE_ALL) || defined(HAL_ICACHE_INVALIDATE_ALL)
HAL_DISABLE_INTERRUPTS(oldints);
HAL_DCACHE_PURGE_ALL();
HAL_ICACHE_INVALIDATE_ALL();
HAL_DCACHE_INVALIDATE_ALL();
HAL_ICACHE_ENABLE();
HAL_DCACHE_ENABLE();
HAL_RESTORE_INTERRUPTS(oldints);
CYG_TEST_INFO("Dcache on Icache on (again)");
time1();
#if defined(CYGPKG_HAL_MIPS)
// In some architectures, the time taken for the next two tests is
// very long, partly because HAL_XCACHE_INVALIDATE_ALL() is implemented
// with a loop over the cache. Hence these tests take longer than the
// testing infrastructure is prepared to wait. The simplest way to get
// these tests to run quickly is to make them think they are running
// under a simulator.
// If the target actually is a simulator, skip the below - it's very
// slow on the simulator, even with reduced loop counts.
if (cyg_test_is_simulator)
CYG_TEST_PASS_FINISH("End of test");
#if defined(CYGPKG_HAL_MIPS_TX49)
// The TX49 has a large cache, and even with reduced loop count,
// 90+ seconds elapses between each INFO output.
CYG_TEST_PASS_FINISH("End of test");
#endif
cyg_test_is_simulator = 1;
#endif
#ifdef HAL_ICACHE_INVALIDATE_ALL
HAL_DISABLE_INTERRUPTS(oldints);
HAL_DCACHE_PURGE_ALL();
HAL_ICACHE_INVALIDATE_ALL();
HAL_DCACHE_INVALIDATE_ALL();
HAL_ICACHE_ENABLE();
HAL_DCACHE_ENABLE();
HAL_RESTORE_INTERRUPTS(oldints);
CYG_TEST_INFO("Dcache on Icache on: invalidate ICache each time");
time1II();
#endif
#ifdef HAL_DCACHE_INVALIDATE_ALL
HAL_DISABLE_INTERRUPTS(oldints);
HAL_DCACHE_PURGE_ALL();
HAL_ICACHE_INVALIDATE_ALL();
HAL_DCACHE_INVALIDATE_ALL();
HAL_ICACHE_ENABLE();
HAL_DCACHE_ENABLE();
HAL_RESTORE_INTERRUPTS(oldints);
CYG_TEST_INFO("Dcache on Icache on: invalidate DCache (expect bogus times)");
time1DI();
#endif
#endif // either INVALIDATE_ALL macro
#endif // HAL_CACHE_UNIFIED
CYG_TEST_PASS_FINISH("End of test");
}
static void entry0( void )
{
register CYG_INTERRUPT_STATE oldints;
#ifdef HAL_CACHE_UNIFIED
HAL_DISABLE_INTERRUPTS(oldints);
HAL_DCACHE_PURGE_ALL(); // rely on above definition
HAL_UCACHE_INVALIDATE_ALL();
HAL_UCACHE_DISABLE();
HAL_RESTORE_INTERRUPTS(oldints);
CYG_TEST_INFO("Cache off");
time1();
HAL_DISABLE_INTERRUPTS(oldints);
HAL_DCACHE_PURGE_ALL(); // rely on above definition
HAL_UCACHE_INVALIDATE_ALL();
HAL_UCACHE_ENABLE();
HAL_RESTORE_INTERRUPTS(oldints);
CYG_TEST_INFO("Cache on");
time1();
#else // HAL_CACHE_UNIFIED
HAL_DISABLE_INTERRUPTS(oldints);
HAL_DCACHE_PURGE_ALL();
HAL_ICACHE_INVALIDATE_ALL();
HAL_DCACHE_INVALIDATE_ALL();
HAL_ICACHE_DISABLE();
HAL_DCACHE_DISABLE();
HAL_RESTORE_INTERRUPTS(oldints);
CYG_TEST_INFO("Dcache off Icache off");
time1();
HAL_DISABLE_INTERRUPTS(oldints);
HAL_DCACHE_PURGE_ALL();
HAL_ICACHE_INVALIDATE_ALL();
HAL_DCACHE_INVALIDATE_ALL();
HAL_ICACHE_DISABLE();
HAL_DCACHE_ENABLE();
HAL_RESTORE_INTERRUPTS(oldints);
CYG_TEST_INFO("Dcache on Icache off");
time1();
HAL_DISABLE_INTERRUPTS(oldints);
HAL_DCACHE_PURGE_ALL();
HAL_ICACHE_INVALIDATE_ALL();
HAL_DCACHE_INVALIDATE_ALL();
HAL_ICACHE_ENABLE();
HAL_DCACHE_DISABLE();
HAL_RESTORE_INTERRUPTS(oldints);
CYG_TEST_INFO("Dcache off Icache on");
time1();
HAL_DISABLE_INTERRUPTS(oldints);
HAL_DCACHE_PURGE_ALL();
HAL_ICACHE_INVALIDATE_ALL();
HAL_DCACHE_INVALIDATE_ALL();
HAL_ICACHE_ENABLE();
HAL_DCACHE_ENABLE();
HAL_RESTORE_INTERRUPTS(oldints);
CYG_TEST_INFO("Dcache on Icache on");
time1();
HAL_DISABLE_INTERRUPTS(oldints);
HAL_DCACHE_PURGE_ALL();
HAL_ICACHE_INVALIDATE_ALL();
HAL_DCACHE_INVALIDATE_ALL();
HAL_ICACHE_DISABLE();
HAL_DCACHE_DISABLE();
HAL_RESTORE_INTERRUPTS(oldints);
CYG_TEST_INFO("Dcache off Icache off");
time1();
#endif // HAL_CACHE_UNIFIED
CYG_TEST_PASS_FINISH("End of test");
}
/**
*
* Hardware initialization.
*
* @return none
*
*****************************************************************************/
void hal_hardware_init(void)
{
cyg_uint32 dw_i, dwCPUID;
// -------- Ininializing GIC -------------------------------------------
// Connect GIC to CORE0
dwCPUID = 1;
HAL_WRITE_UINT32(XC7Z_SCUGIC_DIST_BASEADDR + XSCUGIC_DIST_EN_OFFSET, 0UL);
// For the Shared Peripheral Interrupts INT_ID[MAX..32], set:
//
// 1. The trigger mode in the int_config register
// Only write to the SPI interrupts, so start at 32
//
for (dw_i = 32; dw_i < XSCUGIC_MAX_NUM_INTR_INPUTS; dw_i += 16) {
//
// Each INT_ID uses two bits, or 16 INT_ID per register
// Set them all to be level sensitive, active HIGH.
//
HAL_WRITE_UINT32(XC7Z_SCUGIC_DIST_BASEADDR +
XSCUGIC_INT_CFG_OFFSET_CALC(dw_i),
0UL);
}
for (dw_i = 0; dw_i < XSCUGIC_MAX_NUM_INTR_INPUTS; dw_i += 4) {
//
// 2. The priority using int the priority_level register
// The priority_level and spi_target registers use one byte per
// INT_ID.
// Write a default value that can be changed elsewhere.
//
HAL_WRITE_UINT32(XC7Z_SCUGIC_DIST_BASEADDR +
XSCUGIC_PRIORITY_OFFSET_CALC(dw_i),
DEFAULT_PRIORITY);
}
for (dw_i = 32; dw_i < XSCUGIC_MAX_NUM_INTR_INPUTS; dw_i += 4) {
//
// 3. The CPU interface in the spi_target register
// Only write to the SPI interrupts, so start at 32
//
dwCPUID |= dwCPUID << 8;
dwCPUID |= dwCPUID << 16;
HAL_WRITE_UINT32(XC7Z_SCUGIC_DIST_BASEADDR +
XSCUGIC_SPI_TARGET_OFFSET_CALC(dw_i),
dwCPUID);
}
for (dw_i = 0; dw_i < XSCUGIC_MAX_NUM_INTR_INPUTS; dw_i += 32) {
//
// 4. Enable the SPI using the enable_set register. Leave all
// disabled for now.
//
HAL_WRITE_UINT32(XC7Z_SCUGIC_DIST_BASEADDR +
XSCUGIC_ENABLE_DISABLE_OFFSET_CALC(XSCUGIC_DISABLE_OFFSET, dw_i),
0xFFFFFFFFUL);
}
HAL_WRITE_UINT32(XC7Z_SCUGIC_DIST_BASEADDR + XSCUGIC_DIST_EN_OFFSET,
XSCUGIC_EN_INT_MASK);
//
// Program the priority mask of the CPU using the Priority mask register
//
HAL_WRITE_UINT32(XC7Z_SCUGIC_CPU_BASEADDR + XSCUGIC_CPU_PRIOR_OFFSET, 0xF0);
//
// If the CPU operates in both security domains, set parameters in the
// control_s register.
// 1. Set FIQen=1 to use FIQ for secure interrupts,
// 2. Program the AckCtl bit
// 3. Program the SBPR bit to select the binary pointer behavior
// 4. Set EnableS = 1 to enable secure interrupts
// 5. Set EnbleNS = 1 to enable non secure interrupts
//
//
// If the CPU operates only in the secure domain, setup the
// control_s register.
// 1. Set FIQen=1,
// 2. Set EnableS=1, to enable the CPU interface to signal secure interrupts.
// Only enable the IRQ output unless secure interrupts are needed.
//
HAL_WRITE_UINT32(XC7Z_SCUGIC_CPU_BASEADDR + XSCUGIC_CONTROL_OFFSET, 0x07);
#ifdef HAL_PLF_HARDWARE_INIT
// Perform any platform specific initializations
HAL_PLF_HARDWARE_INIT();
#endif
#ifdef CYGSEM_HAL_ENABLE_DCACHE_ON_STARTUP
HAL_DCACHE_ENABLE(); // Enable DCache
#endif
#ifdef CYGSEM_HAL_ENABLE_ICACHE_ON_STARTUP
HAL_ICACHE_ENABLE(); // Enable ICache
#endif
// Set up eCos/ROM interfaces
hal_if_init();
HAL_CLOCK_INITIALIZE(CYGNUM_HAL_RTC_PERIOD);
#ifdef CYGPKG_HAL_SMP_SUPPORT
cyg_uint32 reg;
/* Disable the distributor */
HAL_READ_UINT32(XC7Z_ICD_DCR_BASEADDR, reg);
reg &= ~(0x2);
HAL_WRITE_UINT32(XC7Z_ICD_DCR_BASEADDR, reg);
/* Clear pending interrupts */
HAL_WRITE_UINT32(XC7Z_ICD_ICPR0_BASEADDR, 0xffffffff);
HAL_WRITE_UINT32(XC7Z_ICD_ICPR1_BASEADDR, 0xffffffff);
HAL_WRITE_UINT32(XC7Z_ICD_ICPR2_BASEADDR, 0xffffffff);
/* Re-enable the distributor */
HAL_READ_UINT32(XC7Z_ICD_DCR_BASEADDR, reg);
reg |= 0x2;
HAL_WRITE_UINT32(XC7Z_ICD_DCR_BASEADDR, reg);
/* Start the cpu */
cyg_hal_smp_init();
hal_interrupt_init_cpu();
cyg_hal_smp_cpu_start_first();
#endif
}
void
do_go(int argc, char *argv[])
{
int i, cur, num_options;
unsigned long entry;
unsigned long oldints;
bool wait_time_set;
int wait_time, res;
bool cache_enabled = false;
#ifdef CYGPKG_IO_ETH_DRIVERS
bool stop_net = false;
#endif
struct option_info opts[3];
char line[8];
hal_virtual_comm_table_t *__chan;
__mem_fault_handler = 0; // Let GDB handle any faults directly
entry = entry_address; // Default from last 'load' operation
init_opts(&opts[0], 'w', true, OPTION_ARG_TYPE_NUM,
(void *)&wait_time, (bool *)&wait_time_set, "wait timeout");
init_opts(&opts[1], 'c', false, OPTION_ARG_TYPE_FLG,
(void *)&cache_enabled, (bool *)0, "go with caches enabled");
num_options = 2;
#ifdef CYGPKG_IO_ETH_DRIVERS
init_opts(&opts[2], 'n', false, OPTION_ARG_TYPE_FLG,
(void *)&stop_net, (bool *)0, "go with network driver stopped");
num_options++;
#endif
CYG_ASSERT(num_options <= NUM_ELEMS(opts), "Too many options");
if (!scan_opts(argc, argv, 1, opts, num_options, (void *)&entry, OPTION_ARG_TYPE_NUM, "starting address"))
{
return;
}
if (entry == (unsigned long)NO_MEMORY) {
diag_printf("No entry point known - aborted\n");
return;
}
if (wait_time_set) {
int script_timeout_ms = wait_time * 1000;
#ifdef CYGSEM_REDBOOT_FLASH_CONFIG
unsigned char *hold_script = script;
script = (unsigned char *)0;
#endif
diag_printf("About to start execution at %p - abort with ^C within %d seconds\n",
(void *)entry, wait_time);
while (script_timeout_ms >= CYGNUM_REDBOOT_CLI_IDLE_TIMEOUT) {
res = _rb_gets(line, sizeof(line), CYGNUM_REDBOOT_CLI_IDLE_TIMEOUT);
if (res == _GETS_CTRLC) {
#ifdef CYGSEM_REDBOOT_FLASH_CONFIG
script = hold_script; // Re-enable script
#endif
return;
}
script_timeout_ms -= CYGNUM_REDBOOT_CLI_IDLE_TIMEOUT;
}
}
// Mask interrupts on all channels
cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
for (i = 0; i < CYGNUM_HAL_VIRTUAL_VECTOR_NUM_CHANNELS; i++) {
CYGACC_CALL_IF_SET_CONSOLE_COMM(i);
__chan = CYGACC_CALL_IF_CONSOLE_PROCS();
CYGACC_COMM_IF_CONTROL( *__chan, __COMMCTL_IRQ_DISABLE );
}
CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
__chan = CYGACC_CALL_IF_CONSOLE_PROCS();
CYGACC_COMM_IF_CONTROL(*__chan, __COMMCTL_ENABLE_LINE_FLUSH);
#ifdef CYGPKG_IO_ETH_DRIVERS
if (stop_net)
eth_drv_stop();
#endif
HAL_DISABLE_INTERRUPTS(oldints);
HAL_DCACHE_SYNC();
if (!cache_enabled) {
HAL_ICACHE_DISABLE();
HAL_DCACHE_DISABLE();
HAL_DCACHE_SYNC();
}
HAL_ICACHE_INVALIDATE_ALL();
HAL_DCACHE_INVALIDATE_ALL();
// set up a temporary context that will take us to the trampoline
HAL_THREAD_INIT_CONTEXT((CYG_ADDRESS)workspace_end, entry, trampoline, 0);
// switch context to trampoline
HAL_THREAD_SWITCH_CONTEXT(&saved_context, &workspace_end);
// we get back here by way of return_to_redboot()
// undo the changes we made before switching context
if (!cache_enabled) {
HAL_ICACHE_ENABLE();
HAL_DCACHE_ENABLE();
}
CYGACC_COMM_IF_CONTROL(*__chan, __COMMCTL_DISABLE_LINE_FLUSH);
HAL_RESTORE_INTERRUPTS(oldints);
diag_printf("\nProgram completed with status %d\n", return_status);
}
void
do_go(int argc, char *argv[])
{
unsigned long entry;
unsigned long oldints;
bool wait_time_set;
int wait_time, res;
bool cache_enabled = false;
struct option_info opts[2];
char line[8];
hal_virtual_comm_table_t *__chan = CYGACC_CALL_IF_CONSOLE_PROCS();
entry = entry_address; // Default from last 'load' operation
init_opts(&opts[0], 'w', true, OPTION_ARG_TYPE_NUM,
(void **)&wait_time, (bool *)&wait_time_set, "wait timeout");
init_opts(&opts[1], 'c', false, OPTION_ARG_TYPE_FLG,
(void **)&cache_enabled, (bool *)0, "go with caches enabled");
if (!scan_opts(argc, argv, 1, opts, 2, (void *)&entry, OPTION_ARG_TYPE_NUM, "starting address"))
{
return;
}
if (wait_time_set) {
int script_timeout_ms = wait_time * 1000;
#ifdef CYGSEM_REDBOOT_FLASH_CONFIG
unsigned char *hold_script = script;
script = (unsigned char *)0;
#endif
diag_printf("About to start execution at %p - abort with ^C within %d seconds\n",
(void *)entry, wait_time);
while (script_timeout_ms >= CYGNUM_REDBOOT_CLI_IDLE_TIMEOUT) {
res = _rb_gets(line, sizeof(line), CYGNUM_REDBOOT_CLI_IDLE_TIMEOUT);
if (res == _GETS_CTRLC) {
#ifdef CYGSEM_REDBOOT_FLASH_CONFIG
script = hold_script; // Re-enable script
#endif
return;
}
script_timeout_ms -= CYGNUM_REDBOOT_CLI_IDLE_TIMEOUT;
}
}
CYGACC_COMM_IF_CONTROL(*__chan, __COMMCTL_ENABLE_LINE_FLUSH);
HAL_DISABLE_INTERRUPTS(oldints);
HAL_DCACHE_SYNC();
if (!cache_enabled) {
HAL_ICACHE_DISABLE();
HAL_DCACHE_DISABLE();
HAL_DCACHE_SYNC();
}
HAL_ICACHE_INVALIDATE_ALL();
HAL_DCACHE_INVALIDATE_ALL();
// set up a temporary context that will take us to the trampoline
HAL_THREAD_INIT_CONTEXT((CYG_ADDRESS)workspace_end, entry, go_trampoline, 0);
// switch context to trampoline
HAL_THREAD_SWITCH_CONTEXT(&go_saved_context, &workspace_end);
// we get back here by way of return_to_redboot()
// undo the changes we made before switching context
if (!cache_enabled) {
HAL_ICACHE_ENABLE();
HAL_DCACHE_ENABLE();
}
CYGACC_COMM_IF_CONTROL(*__chan, __COMMCTL_DISABLE_LINE_FLUSH);
HAL_RESTORE_INTERRUPTS(oldints);
diag_printf("\nProgram completed with status %d\n", go_return_status);
}
int
flash_hwr_init(void)
{
struct FLASH_query data, *qp;
extern char flash_query[], flash_query_end[];
typedef int code_fun(unsigned char *);
code_fun *_flash_query;
int code_len, stat, num_regions, region_size, buffer_size;
int icache_on, dcache_on;
HAL_DCACHE_IS_ENABLED(dcache_on);
HAL_ICACHE_IS_ENABLED(icache_on);
// Copy 'program' code to RAM for execution
code_len = (unsigned long)&flash_query_end - (unsigned long)&flash_query;
_flash_query = (code_fun *)flash_info.work_space;
memcpy(_flash_query, &flash_query, code_len);
if (dcache_on) {
HAL_DCACHE_SYNC(); // Should guarantee this code will run
}
if (icache_on) {
HAL_ICACHE_DISABLE(); // is also required to avoid old contents
}
stat = (*_flash_query)((unsigned char *)&data);
if (icache_on) {
HAL_ICACHE_ENABLE();
}
qp = &data;
if ( (qp->manuf_code == FLASH_Intel_code)
#ifdef CYGOPT_FLASH_IS_BOOTBLOCK
// device types go as follows: 0x90 for 16-bits, 0xD0 for 8-bits,
// plus 0 or 1 for -T (Top Boot) or -B (Bottom Boot)
// [FIXME: whatever that means :FIXME]
// [I think it means the boot blocks are top/bottom of addr space]
// plus the following size codes:
// 0: 16Mbit 2: 8Mbit 4: 4Mbit
// 6: 32Mbit 8: 64Mbit
#if 16 == CYGNUM_FLASH_WIDTH
&& (0x90 == (0xF0 & qp->device_code)) // 16-bit devices
#elif 8 == CYGNUM_FLASH_WIDTH
&& (0xD0 == (0xF0 & qp->device_code)) // 8-bit devices
#else
&& 0
#error Only understand 16 and 8-bit bootblock flash types
#endif
) {
int lookup[] = { 16, 8, 4, 32, 64 };
#define BLOCKSIZE (0x10000)
region_size = BLOCKSIZE;
num_regions = qp->device_code & 0x0F;
num_regions >>= 1;
if ( num_regions > 4 )
goto flash_type_unknown;
num_regions = lookup[num_regions];
num_regions *= 1024 * 1024; // to bits
num_regions /= 8; // to bytes
num_regions /= BLOCKSIZE; // to blocks
buffer_size = 0;
#else // CYGOPT_FLASH_IS_BOOTBLOCK
&& (strncmp(qp->id, "QRY", 3) == 0)) {
num_regions = _si(qp->num_regions)+1;
region_size = _si(qp->region_size)*256;
if (_si(qp->buffer_size)) {
buffer_size = CYGNUM_FLASH_DEVICES << _si(qp->buffer_size);
} else {
buffer_size = 0;
}
#endif // Not CYGOPT_FLASH_IS_BOOTBLOCK
flash_info.block_size = region_size*CYGNUM_FLASH_DEVICES;
flash_info.buffer_size = buffer_size;
flash_info.blocks = num_regions;
flash_info.start = (void *)CYGNUM_FLASH_BASE;
flash_info.end = (void *)(CYGNUM_FLASH_BASE +
(num_regions*region_size*CYGNUM_FLASH_DEVICES));
#ifdef CYGNUM_FLASH_BASE_MASK
// Then this gives us a maximum size for the (visible) device.
// This is to cope with oversize devices fitted, with some high
// address lines ignored.
if ( ((unsigned int)flash_info.start & CYGNUM_FLASH_BASE_MASK) !=
(((unsigned int)flash_info.end - 1) & CYGNUM_FLASH_BASE_MASK ) ) {
// then the size of the device appears to span >1 device-worth!
unsigned int x;
x = (~(CYGNUM_FLASH_BASE_MASK)) + 1; // expected device size
x += (unsigned int)flash_info.start;
if ( x < (unsigned int)flash_info.end ) { // 2nd sanity check
(*flash_info.pf)("\nFLASH: Oversized device! End addr %p changed to %p\n",
flash_info.end, (void *)x );
flash_info.end = (void *)x;
// Also adjust the block count else unlock crashes!
x = ((cyg_uint8 *)flash_info.end - (cyg_uint8 *)flash_info.start)
/ flash_info.block_size;
flash_info.blocks = x;
}
}
#endif // CYGNUM_FLASH_BASE_MASK
return FLASH_ERR_OK;
}
#ifdef CYGOPT_FLASH_IS_BOOTBLOCK
flash_type_unknown:
#endif
(*flash_info.pf)("Can't identify FLASH, sorry, man %x, dev %x, id [%4s] stat %x\n",
qp->manuf_code, qp->device_code, qp->id, stat );
diag_dump_buf(qp, sizeof(data));
return FLASH_ERR_HWR;
}
