void
hal_plf_pci_init(void)
{
#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
HAL_PCI_RESET_ASSERT();
HAL_PCI_CLOCK_DISABLE();
// Set GPIO line direction
HAL_GPIO_OUTPUT_ENABLE(PCI_CLK_GPIO);
HAL_GPIO_OUTPUT_ENABLE(PCI_RESET_GPIO);
HAL_GPIO_OUTPUT_DISABLE(PCI_INTA_GPIO);
HAL_GPIO_OUTPUT_DISABLE(PCI_INTB_GPIO);
HAL_GPIO_OUTPUT_DISABLE(PCI_INTC_GPIO);
HAL_GPIO_OUTPUT_DISABLE(PCI_INTD_GPIO);
// configure PCI interrupt lines for active low irq
HAL_INTERRUPT_CONFIGURE(INTA, 1, 0);
HAL_INTERRUPT_CONFIGURE(INTB, 1, 0);
HAL_INTERRUPT_CONFIGURE(INTC, 1, 0);
HAL_INTERRUPT_CONFIGURE(INTD, 1, 0);
// wait 1ms to satisfy "minimum reset assertion time" of the PCI spec.
HAL_DELAY_US(1000);
HAL_PCI_CLOCK_CONFIG();
HAL_PCI_CLOCK_ENABLE();
// wait 100us to satisfy "minimum reset assertion time from clock stable"
// requirement of the PCI spec.
HAL_DELAY_US(100);
HAL_PCI_RESET_DEASSERT();
#endif
}
// input is the active phase of the chosen interrupt. It is assumed that
// the source is normally level-sensititve rather than edge-sensitive.
static void interferewith( int which, int input )
{
int level, up, hipri, mask, req;
// Interfere with interrupt 'which'
HAL_INTERRUPT_CONFIGURE( which, 1, input ); // should be no change
checkallbut( 0 ); // so don't exclude any of them
HAL_INTERRUPT_CONFIGURE( which, 1, !input ); // make it other-sensitive
DELAY( DLA );
HAL_INTERRUPT_ACKNOWLEDGE( which );
DELAY( DLA );
HAL_INTERRUPT_QUERY_INFO( which, level, up, hipri, mask, req);
CYG_TEST_CHECK( 0 != level , "Int not level-sensitive (-ve level)" );
if ( input )
CYG_TEST_CHECK( 0 == up, "Int high level (-ve level)" );
else
CYG_TEST_CHECK( 0 != up, "Int low level (-ve level)" );
CYG_TEST_CHECK( 0 != mask , "Int unmasked (-ve level)" );
CYG_TEST_CHECK( 0 != req , "Int not requesting (-ve level)" );
checkallbut( which ); // don't check #which, we're messing with it
HAL_INTERRUPT_CONFIGURE( which, 0, input ); // edge, default sense
DELAY( DLA );
HAL_INTERRUPT_ACKNOWLEDGE( which );
DELAY( DLA );
HAL_INTERRUPT_QUERY_INFO( which, level, up, hipri, mask, req);
CYG_TEST_CHECK( 0 == level , "Int not edge-sensitive (+ve edge)" );
if ( input )
CYG_TEST_CHECK( 0 != up, "Int low edge (+ve edge)" );
else
CYG_TEST_CHECK( 0 == up, "Int high edge (+ve edge)" );
CYG_TEST_CHECK( 0 != mask , "Int unmasked (+ve edge)" );
CYG_TEST_CHECK( 0 == req , "Int requesting (+ve edge)" );
checkallbut( which ); // don't check #which, we're messing with it
HAL_INTERRUPT_CONFIGURE( which, 0, !input ); // edge, opposite sense
DELAY( DLA );
HAL_INTERRUPT_ACKNOWLEDGE( which );
DELAY( DLA );
HAL_INTERRUPT_QUERY_INFO( which, level, up, hipri, mask, req);
CYG_TEST_CHECK( 0 == level , "Int not edge-sensitive (-ve edge)" );
if ( input )
CYG_TEST_CHECK( 0 == up, "Int high edge (-ve edge)" );
else
CYG_TEST_CHECK( 0 != up, "Int low edge (-ve edge)" );
CYG_TEST_CHECK( 0 != mask , "Int unmasked (-ve edge)" );
CYG_TEST_CHECK( 0 == req , "Int requesting (-ve edge)" );
checkallbut( which ); // don't check #which, we're messing with it
HAL_INTERRUPT_CONFIGURE( which, 1, input ); // back to original value
DELAY( DLA );
HAL_INTERRUPT_ACKNOWLEDGE( which );
DELAY( DLA );
checkallbut( 0 ); // so don't exclude any of them
}
//
// Platform specific initialization
//
void
plf_hardware_init(void)
{
// GPIO(15) used for ENET clock
HAL_GPIO_OUTPUT_ENABLE(15);
*IXP425_GPCLKR |= GPCLKR_CLK1_ENABLE;
*IXP425_GPCLKR |= GPCLKR_CLK1_PCLK2;
HAL_GPIO_OUTPUT_SET(GPIO_EEPROM_SCL);
HAL_GPIO_OUTPUT_ENABLE(GPIO_EEPROM_SCL);
HAL_GPIO_OUTPUT_SET(GPIO_EEPROM_SDA);
HAL_GPIO_OUTPUT_ENABLE(GPIO_EEPROM_SDA);
// ENET-0 IRQ line
HAL_GPIO_OUTPUT_DISABLE(GPIO_ENET0_INT_N);
HAL_INTERRUPT_CONFIGURE(CYGNUM_HAL_INTERRUPT_ETH0, 1, 0);
// ENET-1 IRQ line
HAL_GPIO_OUTPUT_DISABLE(GPIO_ENET1_INT_N);
HAL_INTERRUPT_CONFIGURE(CYGNUM_HAL_INTERRUPT_ETH1, 1, 0);
// HSS IRQ lines
HAL_GPIO_OUTPUT_DISABLE(GPIO_HSS0_INT_N);
HAL_INTERRUPT_CONFIGURE(CYGNUM_HAL_INTERRUPT_HSS0, 1, 0);
HAL_GPIO_OUTPUT_DISABLE(GPIO_HSS1_INT_N);
HAL_INTERRUPT_CONFIGURE(CYGNUM_HAL_INTERRUPT_HSS1, 1, 0);
// DSL IRQ line
HAL_GPIO_OUTPUT_DISABLE(GPIO_DSL_INT_N);
HAL_INTERRUPT_CONFIGURE(CYGNUM_HAL_INTERRUPT_DSL, 1, 0);
*IXP425_EXP_CS4 = (EXP_ADDR_T(3) | EXP_SETUP_T(3) | EXP_STROBE_T(15) | EXP_HOLD_T(3) | \
EXP_RECOVERY_T(15) | EXP_SZ_512 | EXP_WR_EN | EXP_CS_EN);
*IXP425_EXP_CS5 = (EXP_ADDR_T(3) | EXP_SETUP_T(3) | EXP_STROBE_T(15) | EXP_HOLD_T(3) | \
EXP_RECOVERY_T(15) | EXP_SZ_512 | EXP_WR_EN | EXP_CS_EN);
#ifdef CYGPKG_IO_PCI
extern void hal_plf_pci_init(void);
hal_plf_pci_init();
#endif
}
externC void
_csb281_pci_init(void)
{
static int _init = 0;
cyg_uint8 next_bus;
cyg_uint32 cmd_state;
if (_init) return;
_init = 1;
// Initialize PCI support
cyg_pci_init();
// Setup for bus mastering
HAL_PCI_CFG_READ_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
CYG_PCI_CFG_COMMAND, cmd_state);
if ((cmd_state & CYG_PCI_CFG_COMMAND_MEMORY) == 0) {
// Force PCI-side window to 0
HAL_PCI_CFG_WRITE_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
CYG_PCI_CFG_BAR_0, 0x01);
// Enable bus mastering from host
HAL_PCI_CFG_WRITE_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
CYG_PCI_CFG_COMMAND,
CYG_PCI_CFG_COMMAND_MEMORY |
CYG_PCI_CFG_COMMAND_MASTER |
CYG_PCI_CFG_COMMAND_PARITY |
CYG_PCI_CFG_COMMAND_SERR);
// Setup latency timer field
HAL_PCI_CFG_WRITE_UINT8(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
CYG_PCI_CFG_LATENCY_TIMER, 32);
// Configure PCI bus.
next_bus = 1;
cyg_pci_configure_bus(0, &next_bus);
}
// Configure interrupts (high level)?
HAL_INTERRUPT_CONFIGURE(CYGNUM_HAL_INTERRUPT_PCI0, 1, 1);
HAL_INTERRUPT_CONFIGURE(CYGNUM_HAL_INTERRUPT_PCI1, 1, 1);
HAL_INTERRUPT_CONFIGURE(CYGNUM_HAL_INTERRUPT_LAN, 1, 1);
}
void
plf_hardware_init(void)
{
// POWER_FAIL IRQ
HAL_GPIO_OUTPUT_DISABLE(GPIO_PWR_FAIL_IRQ_N);
HAL_INTERRUPT_CONFIGURE(CYGNUM_HAL_INTERRUPT_PWR_FAIL, 1, 0);
// DSL IRQ
HAL_GPIO_OUTPUT_DISABLE(GPIO_DSL_IRQ_N);
HAL_INTERRUPT_CONFIGURE(CYGNUM_HAL_INTERRUPT_DSL, 1, 0);
// SLIC_A IRQ
HAL_GPIO_OUTPUT_DISABLE(GPIO_SLIC_A_IRQ_N);
HAL_INTERRUPT_CONFIGURE(CYGNUM_HAL_INTERRUPT_SLIC_A, 1, 0);
// SLIC_B IRQ
HAL_GPIO_OUTPUT_DISABLE(GPIO_SLIC_B_IRQ_N);
HAL_INTERRUPT_CONFIGURE(CYGNUM_HAL_INTERRUPT_SLIC_B, 1, 0);
// DSP IRQ
HAL_GPIO_OUTPUT_DISABLE(GPIO_DSP_IRQ_N);
HAL_INTERRUPT_CONFIGURE(CYGNUM_HAL_INTERRUPT_DSP, 1, 0);
// IDE IRQ
HAL_GPIO_OUTPUT_DISABLE(GPIO_IDE_IRQ_N);
HAL_INTERRUPT_CONFIGURE(CYGNUM_HAL_INTERRUPT_IDE, 1, 0);
// IO RESET_N (DSP/SLICs)
HAL_GPIO_OUTPUT_SET(GPIO_IO_RESET_N);
HAL_GPIO_OUTPUT_ENABLE(GPIO_IO_RESET_N);
// SPI_CS1_N
HAL_GPIO_OUTPUT_SET(GPIO_SPI_CS1_N);
HAL_GPIO_OUTPUT_ENABLE(GPIO_SPI_CS1_N); // Eth PHY
// SPI_CS0_N
HAL_GPIO_OUTPUT_SET(GPIO_SPI_CS0_N);
HAL_GPIO_OUTPUT_ENABLE(GPIO_SPI_CS0_N); // SLICs
// SPI_SCK
HAL_GPIO_OUTPUT_CLEAR(GPIO_SPI_SCK);
HAL_GPIO_OUTPUT_ENABLE(GPIO_SPI_SCK);
// SPI_SDI
HAL_GPIO_OUTPUT_CLEAR(GPIO_SPI_SDI);
HAL_GPIO_OUTPUT_ENABLE(GPIO_SPI_SDI);
// SPI_SDI
HAL_GPIO_OUTPUT_DISABLE(GPIO_SPI_SDI);
#ifdef CYGPKG_IO_PCI
extern void hal_plf_pci_init(void);
hal_plf_pci_init();
#endif
}
externC void cyg_drv_interrupt_configure(
cyg_vector_t vector,
cyg_bool_t level,
cyg_bool_t up
)
{
CYG_REPORT_FUNCTION();
CYG_REPORT_FUNCARG3("vector = %d, level = %d, up = %d", vector, level,
up);
CYG_ASSERT( vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector");
CYG_ASSERT( vector <= CYGNUM_HAL_ISR_MAX, "Invalid vector");
HAL_INTERRUPT_CONFIGURE( vector, level, up );
CYG_REPORT_RETURN();
}
//--------------------------------------------------------------------------
// Platform init code.
void
hal_platform_init(void)
{
cyg_uint32 bcsr, gcr, frr, eicr, iack;
int vec;
// Initialize I/O interfaces
hal_if_init();
// Reset interrupt controller/state
HAL_READ_UINT32LE(_CSB281_EPIC_GCR, gcr);
HAL_READ_UINT32LE(_CSB281_EPIC_FRR, frr);
HAL_WRITE_UINT32LE(_CSB281_EPIC_GCR, gcr | _CSB281_EPIC_GCR_R);
do {
HAL_READ_UINT32LE(_CSB281_EPIC_GCR, gcr);
} while ((gcr & _CSB281_EPIC_GCR_R) != 0);
HAL_WRITE_UINT32LE(_CSB281_EPIC_GCR, gcr | _CSB281_EPIC_GCR_M);
HAL_READ_UINT32LE(_CSB281_EPIC_EICR, eicr); // Force direct interrupts
eicr &= ~_CSB281_EPIC_EICR_SIE;
HAL_WRITE_UINT32LE(_CSB281_EPIC_EICR, eicr);
for (vec = CYGNUM_HAL_INTERRUPT_IRQ0; vec <= CYGNUM_HAL_ISR_MAX; vec++) {
HAL_INTERRUPT_CONFIGURE(vec, 0, 0); // Default to low-edge
HAL_INTERRUPT_SET_LEVEL(vec, 0x0F); // Priority
}
vec = (frr & 0x0FFF0000) >> 16; // Number of interrupt sources
while (vec-- > 0) {
HAL_READ_UINT32LE(_CSB281_EPIC_IACK, iack);
HAL_WRITE_UINT32LE(_CSB281_EPIC_EOI, 0);
}
HAL_WRITE_UINT32LE(_CSB281_EPIC_PCTPR, 1); // Enables interrupts
#ifndef CYGSEM_HAL_USE_ROM_MONITOR
// Reset peripherals
HAL_READ_UINT32(_CSB281_BCSR, bcsr);
HAL_WRITE_UINT32(_CSB281_BCSR, _zero_bit(bcsr, _CSB281_BCSR_PRESET));
HAL_WRITE_UINT32(_CSB281_BCSR, _one_bit(bcsr, _CSB281_BCSR_PRESET));
_csb281_i2c_init();
_csb281_fs6377_init(0);
#endif
#ifdef CYGSEM_CSB281_LCD_COMM
lcd_comm_init();
#endif
_csb281_pci_init();
}
externC void
_csb281_pci_init(void)
{
static int _init = 0;
cyg_uint8 next_bus;
cyg_uint32 cmd_state;
if (_init) return;
_init = 1;
// Initialize PCI support
cyg_pci_init();
// Setup for bus mastering
HAL_PCI_CFG_READ_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
CYG_PCI_CFG_COMMAND, cmd_state);
if ((cmd_state & CYG_PCI_CFG_COMMAND_MEMORY) == 0) {
// Force PCI-side window to 0
HAL_PCI_CFG_WRITE_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
CYG_PCI_CFG_BAR_0, 0x01);
// Enable bus mastering from host
HAL_PCI_CFG_WRITE_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
CYG_PCI_CFG_COMMAND,
CYG_PCI_CFG_COMMAND_MEMORY |
CYG_PCI_CFG_COMMAND_MASTER |
CYG_PCI_CFG_COMMAND_PARITY |
CYG_PCI_CFG_COMMAND_SERR);
// Setup latency timer field
HAL_PCI_CFG_WRITE_UINT8(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
CYG_PCI_CFG_LATENCY_TIMER, 32);
// Configure PCI bus.
next_bus = 1;
cyg_pci_configure_bus(0, &next_bus);
}
if (0){
cyg_uint8 devfn;
cyg_pci_device_id devid;
cyg_pci_device dev_info;
int i;
devid = CYG_PCI_DEV_MAKE_ID(next_bus-1, 0) | CYG_PCI_NULL_DEVFN;
while (cyg_pci_find_next(devid, &devid)) {
devfn = CYG_PCI_DEV_GET_DEVFN(devid);
cyg_pci_get_device_info(devid, &dev_info);
diag_printf("\n");
diag_printf("Bus: %d\n", CYG_PCI_DEV_GET_BUS(devid));
diag_printf("PCI Device: %d\n", CYG_PCI_DEV_GET_DEV(devfn));
diag_printf("PCI Func : %d\n", CYG_PCI_DEV_GET_FN(devfn));
diag_printf("Vendor Id : 0x%08X\n", dev_info.vendor);
diag_printf("Device Id : 0x%08X\n", dev_info.device);
for (i = 0; i < dev_info.num_bars; i++) {
diag_printf(" BAR[%d] 0x%08x /", i, dev_info.base_address[i]);
diag_printf(" probed size 0x%08x / CPU addr 0x%08x\n",
dev_info.base_size[i], dev_info.base_map[i]);
}
}
}
// Configure interrupts (high level)?
HAL_INTERRUPT_CONFIGURE(CYGNUM_HAL_INTERRUPT_PCI0, 1, 1);
HAL_INTERRUPT_CONFIGURE(CYGNUM_HAL_INTERRUPT_PCI1, 1, 1);
HAL_INTERRUPT_CONFIGURE(CYGNUM_HAL_INTERRUPT_LAN, 1, 1);
}
