uint32_t uart_get_baudrate(pyb_uart_obj_t *self) {
uint32_t uart_clk = 0;
#if defined(STM32F0)
uart_clk = HAL_RCC_GetPCLK1Freq();
#elif defined(STM32F7)
switch ((RCC->DCKCFGR2 >> ((self->uart_id - 1) * 2)) & 3) {
case 0:
if (self->uart_id == 1 || self->uart_id == 6) {
uart_clk = HAL_RCC_GetPCLK2Freq();
} else {
uart_clk = HAL_RCC_GetPCLK1Freq();
}
break;
case 1:
uart_clk = HAL_RCC_GetSysClockFreq();
break;
case 2:
uart_clk = HSI_VALUE;
break;
case 3:
uart_clk = LSE_VALUE;
break;
}
#elif defined(STM32H7)
uint32_t csel;
if (self->uart_id == 1 || self->uart_id == 6) {
csel = RCC->D2CCIP2R >> 3;
} else {
void platform_early_init(void)
{
// Do general system init
SystemInit();
SystemClock_Config();
// Enable the flash ART controller
__HAL_FLASH_ART_ENABLE();
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
/* read the unique id */
stm32_unique_id[0] = *REG32(0x1ff0f420);
stm32_unique_id[1] = *REG32(0x1ff0f424);
stm32_unique_id[2] = *REG32(0x1ff0f428);
/* seed the random number generator based on this */
srand(stm32_unique_id[0] ^ stm32_unique_id[1] ^ stm32_unique_id[2]);
// Start the systick timer
uint32_t sysclk = HAL_RCC_GetSysClockFreq();
arm_cm_systick_init(sysclk);
stm32_timer_early_init();
stm32_gpio_early_init();
stm32_flash_early_init();
stm32_rng_init();
/* clear the reboot reason */
RCC->CSR |= (1<<24);
// ITM_SendChar('1');
}
/******************************************************//**
* @brief Start the step clock by using the given frequency
* @param[in] newFreq in Hz of the step clock
* @retval None
* @note The frequency is directly the current speed of the device
**********************************************************/
void BSP_MotorControlBoard_StartStepClock(uint16_t newFreq)
{
uint32_t sysFreq = HAL_RCC_GetSysClockFreq();
uint32_t period = (sysFreq/ (TIMER_PRESCALER * newFreq)) - 1;
__HAL_TIM_SetAutoreload(&hTimStepClock, period);
__HAL_TIM_SetCompare(&hTimStepClock, BSP_MOTOR_CONTROL_BOARD_CHAN_TIMER_STEP_CLOCK, period >> 1);
HAL_TIM_PWM_Start_IT(&hTimStepClock, BSP_MOTOR_CONTROL_BOARD_CHAN_TIMER_STEP_CLOCK);
}
/// \function freq()
/// Return a tuple of clock frequencies: (SYSCLK, HCLK, PCLK1, PCLK2).
// TODO should also be able to set frequency via this function
STATIC mp_obj_t pyb_freq(void) {
mp_obj_t tuple[4] = {
mp_obj_new_int(HAL_RCC_GetSysClockFreq()),
mp_obj_new_int(HAL_RCC_GetHCLKFreq()),
mp_obj_new_int(HAL_RCC_GetPCLK1Freq()),
mp_obj_new_int(HAL_RCC_GetPCLK2Freq()),
};
return mp_obj_new_tuple(4, tuple);
}
/**
* @brief Configure the IRDA peripheral
* @param hirda: irda handle
* @retval None
*/
static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda)
{
uint32_t tmpreg = 0x00000000;
IRDA_ClockSourceTypeDef clocksource = IRDA_CLOCKSOURCE_UNDEFINED;
HAL_StatusTypeDef ret = HAL_OK;
/* Check the communication parameters */
assert_param(IS_IRDA_BAUDRATE(hirda->Init.BaudRate));
assert_param(IS_IRDA_WORD_LENGTH(hirda->Init.WordLength));
assert_param(IS_IRDA_PARITY(hirda->Init.Parity));
assert_param(IS_IRDA_TX_RX_MODE(hirda->Init.Mode));
assert_param(IS_IRDA_PRESCALER(hirda->Init.Prescaler));
assert_param(IS_IRDA_POWERMODE(hirda->Init.PowerMode));
/*-------------------------- USART CR1 Configuration -----------------------*/
/* Configure the IRDA Word Length, Parity and transfer Mode:
Set the M bits according to hirda->Init.WordLength value
Set PCE and PS bits according to hirda->Init.Parity value
Set TE and RE bits according to hirda->Init.Mode value */
tmpreg = (uint32_t)hirda->Init.WordLength | hirda->Init.Parity | hirda->Init.Mode ;
MODIFY_REG(hirda->Instance->CR1, IRDA_CR1_FIELDS, tmpreg);
/*-------------------------- USART CR3 Configuration -----------------------*/
MODIFY_REG(hirda->Instance->CR3, USART_CR3_IRLP, hirda->Init.PowerMode);
/*-------------------------- USART GTPR Configuration ----------------------*/
MODIFY_REG(hirda->Instance->GTPR, USART_GTPR_PSC, hirda->Init.Prescaler);
/*-------------------------- USART BRR Configuration -----------------------*/
__HAL_IRDA_GETCLOCKSOURCE(hirda, clocksource);
switch (clocksource)
{
case IRDA_CLOCKSOURCE_PCLK1:
hirda->Instance->BRR = (uint16_t)(HAL_RCC_GetPCLK1Freq() / hirda->Init.BaudRate);
break;
case IRDA_CLOCKSOURCE_PCLK2:
hirda->Instance->BRR = (uint16_t)(HAL_RCC_GetPCLK2Freq() / hirda->Init.BaudRate);
break;
case IRDA_CLOCKSOURCE_HSI:
hirda->Instance->BRR = (uint16_t)(HSI_VALUE / hirda->Init.BaudRate);
break;
case IRDA_CLOCKSOURCE_SYSCLK:
hirda->Instance->BRR = (uint16_t)(HAL_RCC_GetSysClockFreq() / hirda->Init.BaudRate);
break;
case IRDA_CLOCKSOURCE_LSE:
hirda->Instance->BRR = (uint16_t)(LSE_VALUE / hirda->Init.BaudRate);
break;
case IRDA_CLOCKSOURCE_UNDEFINED:
default:
ret = HAL_ERROR;
break;
}
return ret;
}
void cycleCounterInit(void)
{
#ifdef USE_HAL_DRIVER
usTicks = HAL_RCC_GetSysClockFreq() / 1000000;
#else
RCC_ClocksTypeDef clocks;
RCC_GetClocksFreq(&clocks);
usTicks = clocks.SYSCLK_Frequency / 1000000;
#endif
}
/**
* print RCC freq information
*
* for example:
*
* SYSCLK_Frequency is 48000000HZ
* PCLK_Frequency is 48000000HZ
* HCLK_Frequency is 48000000HZ
* CECCLK_Frequency is 32786HZ
* ADCCLK_Frequency is 14000000HZ
* USART1CLK_Frequency is 48000000HZ
* I2C1CLK_Frequency is 8000000HZ
* SystemCoreClock is 48000000HZ
*
*/
void print_rcc_freq_info(void)
{
rt_uint32_t clkval;
clkval = HAL_RCC_GetSysClockFreq();//sysclk
rt_kprintf("\nSYSCLK_Frequency is %dHZ", clkval);
clkval = HAL_RCC_GetHCLKFreq(); //Hclk
rt_kprintf("\nHCLK_Frequency is %dHZ", clkval);
clkval = HAL_RCC_GetPCLK1Freq(); //pclk1
rt_kprintf("\nPCLK1_Frequency is %dHZ", clkval);
clkval = HAL_RCC_GetPCLK2Freq(); //pclk2
rt_kprintf("\nPCLK2_Frequency is %dHZ", clkval);
}
// delay for given number of microseconds
void sys_tick_udelay(uint32_t usec) {
if (query_irq() == IRQ_STATE_ENABLED) {
// IRQs enabled, so can use systick counter to do the delay
uint32_t start = sys_tick_get_microseconds();
while (sys_tick_get_microseconds() - start < usec) {
}
} else {
// IRQs disabled, so need to use a busy loop for the delay
// sys freq is always a multiple of 2MHz, so division here won't lose precision
const uint32_t ucount = HAL_RCC_GetSysClockFreq() / 2000000 * usec / 2;
for (uint32_t count = 0; ++count <= ucount;) {
}
}
}
void cycleCounterInit(void)
{
#if defined(USE_HAL_DRIVER)
usTicks = HAL_RCC_GetSysClockFreq() / 1000000;
#else
RCC_ClocksTypeDef clocks;
RCC_GetClocksFreq(&clocks);
usTicks = clocks.SYSCLK_Frequency / 1000000;
#endif
// Enable DWT for precision time measurement
CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk;
}
void platform_init(void)
{
printf("clocks:\n");
printf("\tsysclk %u\n", HAL_RCC_GetSysClockFreq());
printf("\thclk %u\n", HAL_RCC_GetHCLKFreq());
printf("\tpclk1 %u\n", HAL_RCC_GetPCLK1Freq());
printf("\tpclk2 %u\n", HAL_RCC_GetPCLK2Freq());
printf("unique id: 0x%08x%08x%08x\n", stm32_unique_id[0], stm32_unique_id[1], stm32_unique_id[2]);
stm32_timer_init();
stm32_flash_init();
// ITM_SendChar('2');
}
void initTimers()
{
TIM_HandleTypeDef TIM_Handle;
// 10 kHz timer.
#if defined STM32F1
__TIM8_CLK_ENABLE();
TIM_Handle.Instance = TIM8;
TIM_Handle.Init.Prescaler = (uint16_t)(HAL_RCC_GetPCLK2Freq() / 10000) - 1;
#elif defined STM32F2
__TIM4_CLK_ENABLE();
TIM_Handle.Instance = TIM4;
TIM_Handle.Init.Prescaler = (uint16_t)(HAL_RCC_GetPCLK2Freq() / 100000) - 1;
#elif defined STM32F4
__TIM3_CLK_ENABLE();
TIM_Handle.Instance = TIM3;
// TIM3 Clocked from SYSCLK = 168 MHz
TIM_Handle.Init.Prescaler = (uint16_t)(HAL_RCC_GetSysClockFreq() / 10000) - 1;
#endif
// 1 Hz blinking
TIM_Handle.Init.Period = 10000;
TIM_Handle.Init.ClockDivision = 0;
TIM_Handle.Init.CounterMode = TIM_COUNTERMODE_UP;
HAL_TIM_Base_Init(&TIM_Handle);
HAL_TIM_PWM_Init(&TIM_Handle);
TIM_OC_InitTypeDef TIM_OCConfig;
TIM_OCConfig.OCMode = TIM_OCMODE_PWM1;
// 5000 / 10000 = 50% duty cycle.
TIM_OCConfig.Pulse = 4999;
TIM_OCConfig.OCPolarity = TIM_OCPOLARITY_HIGH;
TIM_OCConfig.OCFastMode = TIM_OCFAST_DISABLE;
#if defined STM32F1
HAL_TIM_PWM_ConfigChannel(&TIM_Handle, &TIM_OCConfig, TIM_CHANNEL_3);
HAL_TIM_PWM_Start(&TIM_Handle, TIM_CHANNEL_3);
#elif defined STM32F2
HAL_TIM_PWM_ConfigChannel(&TIM_Handle, &TIM_OCConfig, TIM_CHANNEL_1);
HAL_TIM_PWM_Start(&TIM_Handle, TIM_CHANNEL_1);
#elif defined STM32F4
HAL_TIM_PWM_ConfigChannel(&TIM_Handle, &TIM_OCConfig, TIM_CHANNEL_1);
HAL_TIM_PWM_Start(&TIM_Handle, TIM_CHANNEL_1);
#endif
}
// We provide our own version of HAL_Delay that calls __WFI while waiting, in
// order to reduce power consumption.
void HAL_Delay(uint32_t Delay) {
if (query_irq() == IRQ_STATE_ENABLED) {
// IRQs enabled, so can use systick counter to do the delay
extern __IO uint32_t uwTick;
uint32_t start = uwTick;
// Wraparound of tick is taken care of by 2's complement arithmetic.
while (uwTick - start < Delay) {
// Enter sleep mode, waiting for (at least) the SysTick interrupt.
__WFI();
}
} else {
// IRQs disabled, so need to use a busy loop for the delay.
// To prevent possible overflow of the counter we use a double loop.
const uint32_t count_1ms = HAL_RCC_GetSysClockFreq() / 4000;
for (int i = 0; i < Delay; i++) {
for (uint32_t count = 0; ++count <= count_1ms;) {
}
}
}
}
//--------------------------------------------------------------
// Init vom System-Counter
// entweder im 1us-Takt oder 1ms-Takt
//--------------------------------------------------------------
void Systick_Init(void) {
// alle Variabeln zurücksetzen
Systick_Delay=0;
Systick_T1=0; // Timer1 STOP
Systick_T2=0; // Timer2 STOP
Systick_C1.faktor=0; // Counter1 STOP
Systick_C1.wert=0;
Systick_C2.faktor=0; // Counter2 STOP
Systick_C2.wert=0;
uint32_t clockfrequency = HAL_RCC_GetSysClockFreq();
#if SYSTICK_RESOLUTION==1
// Timer auf 1us einstellen
SysTick_Config(clockfrequency / 1000000);
#else
// Timer auf 1ms einstellen
SysTick_Config(clockfrequency / 1000);
#endif
}
static void extclk_config(int frequency)
{
/* TCLK (PCLK2 * 2) */
int tclk = HAL_RCC_GetPCLK2Freq() * 2;
/* SYSCLK/TCLK = No prescaler */
int prescaler = (uint16_t) (HAL_RCC_GetSysClockFreq()/ tclk) - 1;
/* Period should be even */
int period = (tclk / frequency)-1;
/* Timer base configuration */
TIMHandle.Instance = DCMI_TIM;
TIMHandle.Init.Period = period;
TIMHandle.Init.Prescaler = prescaler;
TIMHandle.Init.ClockDivision = 0;
TIMHandle.Init.CounterMode = TIM_COUNTERMODE_UP;
/* Timer channel configuration */
TIM_OC_InitTypeDef TIMOCHandle;
TIMOCHandle.Pulse = period/2;
TIMOCHandle.OCMode = TIM_OCMODE_PWM1;
TIMOCHandle.OCPolarity = TIM_OCPOLARITY_HIGH;
TIMOCHandle.OCFastMode = TIM_OCFAST_DISABLE;
TIMOCHandle.OCIdleState = TIM_OCIDLESTATE_RESET;
if (HAL_TIM_PWM_Init(&TIMHandle) != HAL_OK) {
/* Initialization Error */
BREAK();
}
if (HAL_TIM_PWM_ConfigChannel(&TIMHandle, &TIMOCHandle, DCMI_TIM_CHANNEL) != HAL_OK) {
BREAK();
}
if (HAL_TIM_PWM_Start(&TIMHandle, DCMI_TIM_CHANNEL) != HAL_OK) {
BREAK();
}
}
uint32_t cpufreq_get_cpuclk()
{
uint32_t cpuclk = HAL_RCC_GetSysClockFreq();
#if defined(STM32H7)
uint32_t flatency;
RCC_ClkInitTypeDef RCC_ClkInitStruct;
HAL_RCC_GetClockConfig(&RCC_ClkInitStruct, &flatency);
switch (RCC_ClkInitStruct.SYSCLKDivider) {
case RCC_SYSCLK_DIV1:
break;
case RCC_SYSCLK_DIV2:
cpuclk /= 2;
break;
case RCC_SYSCLK_DIV4:
cpuclk /= 4;
break;
default:
break;
}
#endif
return cpuclk;
}
/**
* @brief Configure the SMARTCARD associated USART peripheral
* @param hsc: SMARTCARD handle
* @retval None
*/
static void SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsc)
{
uint32_t tmpreg = 0x00000000;
uint32_t clocksource = 0x00000000;
/* Check the parameters */
assert_param(IS_SMARTCARD_INSTANCE(hsc->Instance));
assert_param(IS_SMARTCARD_BAUDRATE(hsc->Init.BaudRate));
assert_param(IS_SMARTCARD_WORD_LENGTH(hsc->Init.WordLength));
assert_param(IS_SMARTCARD_STOPBITS(hsc->Init.StopBits));
assert_param(IS_SMARTCARD_PARITY(hsc->Init.Parity));
assert_param(IS_SMARTCARD_MODE(hsc->Init.Mode));
assert_param(IS_SMARTCARD_POLARITY(hsc->Init.CLKPolarity));
assert_param(IS_SMARTCARD_PHASE(hsc->Init.CLKPhase));
assert_param(IS_SMARTCARD_LASTBIT(hsc->Init.CLKLastBit));
assert_param(IS_SMARTCARD_ONE_BIT_SAMPLE(hsc->Init.OneBitSampling));
assert_param(IS_SMARTCARD_NACK(hsc->Init.NACKState));
assert_param(IS_SMARTCARD_TIMEOUT(hsc->Init.TimeOutEnable));
assert_param(IS_SMARTCARD_AUTORETRY_COUNT(hsc->Init.AutoRetryCount));
/*-------------------------- USART CR1 Configuration -----------------------*/
/* In SmartCard mode, M and PCE are forced to 1 (8 bits + parity).
* Oversampling is forced to 16 (OVER8 = 0).
* Configure the Parity and Mode:
* set PS bit according to hsc->Init.Parity value
* set TE and RE bits according to hsc->Init.Mode value */
tmpreg = (uint32_t) hsc->Init.Parity | hsc->Init.Mode;
/* in case of TX-only mode, if NACK is enabled, the USART must be able to monitor
the bidirectional line to detect a NACK signal in case of parity error.
Therefore, the receiver block must be enabled as well (RE bit must be set). */
if((hsc->Init.Mode == SMARTCARD_MODE_TX) && (hsc->Init.NACKState == SMARTCARD_NACK_ENABLE))
{
tmpreg |= USART_CR1_RE;
}
tmpreg |= (uint32_t) hsc->Init.WordLength;
MODIFY_REG(hsc->Instance->CR1, USART_CR1_FIELDS, tmpreg);
/*-------------------------- USART CR2 Configuration -----------------------*/
/* Stop bits are forced to 1.5 (STOP = 11) */
tmpreg = hsc->Init.StopBits;
/* Synchronous mode is activated by default */
tmpreg |= (uint32_t) USART_CR2_CLKEN | hsc->Init.CLKPolarity;
tmpreg |= (uint32_t) hsc->Init.CLKPhase | hsc->Init.CLKLastBit;
tmpreg |= (uint32_t) hsc->Init.TimeOutEnable;
MODIFY_REG(hsc->Instance->CR2, USART_CR2_FIELDS, tmpreg);
/*-------------------------- USART CR3 Configuration -----------------------*/
/* Configure
* - one-bit sampling method versus three samples' majority rule
* according to hsc->Init.OneBitSampling
* - NACK transmission in case of parity error according
* to hsc->Init.NACKEnable
* - autoretry counter according to hsc->Init.AutoRetryCount */
tmpreg = (uint32_t) hsc->Init.OneBitSampling | hsc->Init.NACKState;
tmpreg |= (uint32_t) (hsc->Init.AutoRetryCount << SMARTCARD_CR3_SCARCNT_LSB_POS);
MODIFY_REG(hsc->Instance-> CR3,USART_CR3_FIELDS, tmpreg);
/*-------------------------- USART GTPR Configuration ----------------------*/
tmpreg = (uint32_t) (hsc->Init.Prescaler | (hsc->Init.GuardTime << SMARTCARD_GTPR_GT_LSB_POS));
MODIFY_REG(hsc->Instance->GTPR, (uint32_t)(USART_GTPR_GT|USART_GTPR_PSC), tmpreg);
/*-------------------------- USART RTOR Configuration ----------------------*/
tmpreg = (uint32_t) (hsc->Init.BlockLength << SMARTCARD_RTOR_BLEN_LSB_POS);
if(hsc->Init.TimeOutEnable == SMARTCARD_TIMEOUT_ENABLE)
{
assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsc->Init.TimeOutValue));
tmpreg |= (uint32_t) hsc->Init.TimeOutValue;
}
MODIFY_REG(hsc->Instance->RTOR, (USART_RTOR_RTO|USART_RTOR_BLEN), tmpreg);
/*-------------------------- USART BRR Configuration -----------------------*/
SMARTCARD_GETCLOCKSOURCE(hsc, clocksource);
switch (clocksource)
{
case SMARTCARD_CLOCKSOURCE_PCLK1:
hsc->Instance->BRR = (uint16_t)(HAL_RCC_GetPCLK1Freq() / hsc->Init.BaudRate);
break;
case SMARTCARD_CLOCKSOURCE_PCLK2:
hsc->Instance->BRR = (uint16_t)(HAL_RCC_GetPCLK2Freq() / hsc->Init.BaudRate);
break;
case SMARTCARD_CLOCKSOURCE_HSI:
hsc->Instance->BRR = (uint16_t)(HSI_VALUE / hsc->Init.BaudRate);
break;
case SMARTCARD_CLOCKSOURCE_SYSCLK:
hsc->Instance->BRR = (uint16_t)(HAL_RCC_GetSysClockFreq() / hsc->Init.BaudRate);
break;
case SMARTCARD_CLOCKSOURCE_LSE:
hsc->Instance->BRR = (uint16_t)(LSE_VALUE / hsc->Init.BaudRate);
break;
default:
break;
}
}
bool UART_config(uart *uart, u32_t baud, UART_databits databits,
UART_stopbits stopbits, UART_parity parity, UART_flowcontrol flowcontrol,
bool activate) {
UART_HW(uart)->CR1 &= ~USART_CR1_UE; // disable uart
if (activate) {
u32_t sdatabits = 0;
u32_t sstopbits = 0;
u32_t sparity = 0;
u32_t sflowcontrol = 0;
uint16_t usartdiv = 0x0000;
UART_ClockSourceTypeDef clocksource = UART_CLOCKSOURCE_UNDEFINED;
switch (databits) {
case UART_DATABITS_8: sdatabits = USART_WORDLENGTH_8B; break;
case UART_DATABITS_9: sdatabits = USART_WORDLENGTH_9B; break;
default: return FALSE;
}
switch (stopbits) {
case UART_STOPBITS_0_5: sstopbits = USART_STOPBITS_1; break;
case UART_STOPBITS_1: sstopbits = USART_STOPBITS_1; break;
case UART_STOPBITS_1_5: sstopbits = USART_STOPBITS_1_5; break;
case UART_STOPBITS_2: sstopbits = USART_STOPBITS_2; break;
default: return FALSE;
}
switch (parity) {
case UART_PARITY_NONE: sparity = USART_PARITY_NONE; break;
case UART_PARITY_EVEN: sparity = USART_PARITY_EVEN; break;
case UART_PARITY_ODD: sparity = USART_PARITY_ODD; break;
default: return FALSE;
}
switch (flowcontrol) {
case UART_FLOWCONTROL_NONE: sflowcontrol = UART_HWCONTROL_NONE; break;
case UART_FLOWCONTROL_CTS: sflowcontrol = UART_HWCONTROL_CTS; break;
case UART_FLOWCONTROL_RTS: sflowcontrol = UART_HWCONTROL_RTS; break;
case UART_FLOWCONTROL_RTS_CTS: sflowcontrol = UART_HWCONTROL_RTS_CTS; break;
default: return FALSE;
}
UART_HW(uart)->CR1 = 0;
UART_HW(uart)->CR2 = 0;
UART_HW(uart)->CR3 = 0;
/*-------------------------- USART CR1 Configuration -----------------------*/
MODIFY_REG(UART_HW(uart)->CR1, USART_CR1_FIELDS,
sdatabits | sparity | USART_CR1_OVER8 | USART_CR1_RE | USART_CR1_TE);
/*---------------------------- USART CR2 Configuration ---------------------*/
MODIFY_REG(UART_HW(uart)->CR2, USART_CR2_STOP,
sstopbits);
UART_HW(uart)->CR2 &= ~USART_CR2_LINEN;
/*-------------------------- USART CR3 Configuration -----------------------*/
MODIFY_REG(UART_HW(uart)->CR3, (USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT),
sflowcontrol);
_UART_GETCLOCKSOURCE(UART_HW(uart), clocksource);
switch (clocksource)
{
case UART_CLOCKSOURCE_PCLK1:
usartdiv = (uint16_t)(_UART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), baud));
break;
case UART_CLOCKSOURCE_PCLK2:
usartdiv = (uint16_t)(_UART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), baud));
break;
case UART_CLOCKSOURCE_HSI:
usartdiv = (uint16_t)(_UART_DIV_SAMPLING8(HSI_VALUE, baud));
break;
case UART_CLOCKSOURCE_SYSCLK:
usartdiv = (uint16_t)(_UART_DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), baud));
break;
case UART_CLOCKSOURCE_LSE:
usartdiv = (uint16_t)(_UART_DIV_SAMPLING8(LSE_VALUE, baud));
break;
case UART_CLOCKSOURCE_UNDEFINED:
default:
return FALSE;
break;
}
u32_t brrtemp = usartdiv & 0xFFF0;
brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000F) >> 1U);
UART_HW(uart)->BRR = brrtemp;
// enable usart interrupts
_UART_ENABLE_IT(UART_HW(uart), USART_IT_TC);
_UART_ENABLE_IT(UART_HW(uart), USART_IT_TXE);
_UART_ENABLE_IT(UART_HW(uart), USART_IT_RXNE);
UART_HW(uart)->CR1 |= USART_CR1_UE; // enable uart
} else {
/**
* @brief Initializes the I2S according to the specified parameters
* in the I2S_InitTypeDef and create the associated handle.
* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
{
uint32_t i2sdiv = 2, i2sodd = 0, packetlength = 1;
uint32_t tmp = 0, i2sclk = 0;
/* Check the I2S handle allocation */
if(hi2s == NULL)
{
return HAL_ERROR;
}
/* Check the I2S parameters */
assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
assert_param(IS_I2S_MODE(hi2s->Init.Mode));
assert_param(IS_I2S_STANDARD(hi2s->Init.Standard));
assert_param(IS_I2S_DATA_FORMAT(hi2s->Init.DataFormat));
assert_param(IS_I2S_MCLK_OUTPUT(hi2s->Init.MCLKOutput));
assert_param(IS_I2S_AUDIO_FREQ(hi2s->Init.AudioFreq));
assert_param(IS_I2S_CPOL(hi2s->Init.CPOL));
if(hi2s->State == HAL_I2S_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hi2s->Lock = HAL_UNLOCKED;
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
HAL_I2S_MspInit(hi2s);
}
hi2s->State = HAL_I2S_STATE_BUSY;
/* If the default value has to be written, reinitialize i2sdiv and i2sodd*/
if(hi2s->Init.AudioFreq == I2S_AUDIOFREQ_DEFAULT)
{
i2sodd = (uint32_t)0;
i2sdiv = (uint32_t)2;
}
/* If the requested audio frequency is not the default, compute the prescaler */
else
{
/* Check the frame length (For the Prescaler computing) *******************/
if(hi2s->Init.DataFormat == I2S_DATAFORMAT_16B)
{
/* Packet length is 16 bits */
packetlength = 1;
}
else
{
/* Packet length is 32 bits */
packetlength = 2;
}
/* Get the source clock value: based on System Clock value */
i2sclk = HAL_RCC_GetSysClockFreq();
/* Compute the Real divider depending on the MCLK output state, with a floating point */
if(hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE)
{
/* MCLK output is enabled */
tmp = (uint32_t)(((((i2sclk / 256) * 10) / hi2s->Init.AudioFreq)) + 5);
}
else
{
/* MCLK output is disabled */
tmp = (uint32_t)(((((i2sclk / (32 * packetlength)) *10 ) / hi2s->Init.AudioFreq)) + 5);
}
/* Remove the flatting point */
tmp = tmp / 10;
/* Check the parity of the divider */
i2sodd = (uint32_t)(tmp & (uint32_t)1);
/* Compute the i2sdiv prescaler */
i2sdiv = (uint32_t)((tmp - i2sodd) / 2);
/* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
i2sodd = (uint32_t) (i2sodd << 8);
}
/* Test if the divider is 1 or 0 or greater than 0xFF */
if((i2sdiv < 2) || (i2sdiv > 0xFF))
{
/* Set the default values */
i2sdiv = 2;
i2sodd = 0;
}
/*----------------------- SPIx I2SCFGR & I2SPR Configuration ----------------*/
/* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
/* And configure the I2S with the I2S_InitStruct values */
MODIFY_REG( hi2s->Instance->I2SCFGR, (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN |\
SPI_I2SCFGR_CKPOL | SPI_I2SCFGR_I2SSTD |\
SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG |\
SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD),\
(SPI_I2SCFGR_I2SMOD | hi2s->Init.Mode |\
hi2s->Init.Standard | hi2s->Init.DataFormat |\
hi2s->Init.CPOL));
/* Write to SPIx I2SPR register the computed value */
hi2s->Instance->I2SPR = (uint32_t)((uint32_t)i2sdiv | (uint32_t)(i2sodd | (uint32_t)hi2s->Init.MCLKOutput));
hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
hi2s->State= HAL_I2S_STATE_READY;
return HAL_OK;
}
/// \function freq([sys_freq])
///
/// If given no arguments, returns a tuple of clock frequencies:
/// (SYSCLK, HCLK, PCLK1, PCLK2).
///
/// If given an argument, sets the system frequency to that value in Hz.
/// Eg freq(120000000) gives 120MHz. Note that not all values are
/// supported and the largest supported frequency not greater than
/// the given sys_freq will be selected.
STATIC mp_obj_t pyb_freq(mp_uint_t n_args, const mp_obj_t *args) {
if (n_args == 0) {
// get
mp_obj_t tuple[4] = {
mp_obj_new_int(HAL_RCC_GetSysClockFreq()),
mp_obj_new_int(HAL_RCC_GetHCLKFreq()),
mp_obj_new_int(HAL_RCC_GetPCLK1Freq()),
mp_obj_new_int(HAL_RCC_GetPCLK2Freq()),
};
return mp_obj_new_tuple(4, tuple);
} else {
// set
mp_int_t wanted_sysclk = mp_obj_get_int(args[0]) / 1000000;
// search for a valid PLL configuration that keeps USB at 48MHz
for (; wanted_sysclk > 0; wanted_sysclk--) {
for (mp_uint_t p = 2; p <= 8; p += 2) {
if (wanted_sysclk * p % 48 != 0) {
continue;
}
mp_uint_t q = wanted_sysclk * p / 48;
if (q < 2 || q > 15) {
continue;
}
if (wanted_sysclk * p % (HSE_VALUE / 1000000) != 0) {
continue;
}
mp_uint_t n_by_m = wanted_sysclk * p / (HSE_VALUE / 1000000);
mp_uint_t m = 192 / n_by_m;
while (m < (HSE_VALUE / 2000000) || n_by_m * m < 192) {
m += 1;
}
if (m > (HSE_VALUE / 1000000)) {
continue;
}
mp_uint_t n = n_by_m * m;
if (n < 192 || n > 432) {
continue;
}
// found values!
// let the USB CDC have a chance to process before we change the clock
HAL_Delay(USBD_CDC_POLLING_INTERVAL + 2);
// set HSE as system clock source to allow modification of the PLL configuration
RCC_ClkInitTypeDef RCC_ClkInitStruct;
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSE;
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
goto fail;
}
// re-configure PLL
RCC_OscInitTypeDef RCC_OscInitStruct;
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
RCC_OscInitStruct.PLL.PLLM = m;
RCC_OscInitStruct.PLL.PLLN = n;
RCC_OscInitStruct.PLL.PLLP = p;
RCC_OscInitStruct.PLL.PLLQ = q;
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
goto fail;
}
// set PLL as system clock source
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) {
goto fail;
}
// re-init TIM3 for USB CDC rate
timer_tim3_init();
return mp_const_none;
void __fatal_error(const char *msg);
fail:
__fatal_error("can't change freq");
}
}
nlr_raise(mp_obj_new_exception_msg(&mp_type_ValueError, "can't make valid freq"));
}
}
/// \function info([dump_alloc_table])
/// Print out lots of information about the board.
STATIC mp_obj_t pyb_info(uint n_args, const mp_obj_t *args) {
// get and print unique id; 96 bits
{
byte *id = (byte*)0x1fff7a10;
printf("ID=%02x%02x%02x%02x:%02x%02x%02x%02x:%02x%02x%02x%02x\n", id[0], id[1], id[2], id[3], id[4], id[5], id[6], id[7], id[8], id[9], id[10], id[11]);
}
// get and print clock speeds
// SYSCLK=168MHz, HCLK=168MHz, PCLK1=42MHz, PCLK2=84MHz
{
printf("S=%lu\nH=%lu\nP1=%lu\nP2=%lu\n",
HAL_RCC_GetSysClockFreq(),
HAL_RCC_GetHCLKFreq(),
HAL_RCC_GetPCLK1Freq(),
HAL_RCC_GetPCLK2Freq());
}
// to print info about memory
{
printf("_etext=%p\n", &_etext);
printf("_sidata=%p\n", &_sidata);
printf("_sdata=%p\n", &_sdata);
printf("_edata=%p\n", &_edata);
printf("_sbss=%p\n", &_sbss);
printf("_ebss=%p\n", &_ebss);
printf("_estack=%p\n", &_estack);
printf("_ram_start=%p\n", &_ram_start);
printf("_heap_start=%p\n", &_heap_start);
printf("_heap_end=%p\n", &_heap_end);
printf("_ram_end=%p\n", &_ram_end);
}
// qstr info
{
uint n_pool, n_qstr, n_str_data_bytes, n_total_bytes;
qstr_pool_info(&n_pool, &n_qstr, &n_str_data_bytes, &n_total_bytes);
printf("qstr:\n n_pool=%u\n n_qstr=%u\n n_str_data_bytes=%u\n n_total_bytes=%u\n", n_pool, n_qstr, n_str_data_bytes, n_total_bytes);
}
// GC info
{
gc_info_t info;
gc_info(&info);
printf("GC:\n");
printf(" " UINT_FMT " total\n", info.total);
printf(" " UINT_FMT " : " UINT_FMT "\n", info.used, info.free);
printf(" 1=" UINT_FMT " 2=" UINT_FMT " m=" UINT_FMT "\n", info.num_1block, info.num_2block, info.max_block);
}
// free space on flash
{
DWORD nclst;
FATFS *fatfs;
f_getfree("0:", &nclst, &fatfs);
printf("LFS free: %u bytes\n", (uint)(nclst * fatfs->csize * 512));
}
if (n_args == 1) {
// arg given means dump gc allocation table
gc_dump_alloc_table();
}
return mp_const_none;
}
/**
* @brief Initializes the CPU, AHB and APB buses clocks according to the specified
* parameters in the RCC_ClkInitStruct.
* @param RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that
* contains the configuration information for the RCC peripheral.
* @param FLatency FLASH Latency
* The value of this parameter depend on device used within the same series
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
* and updated by @ref HAL_RCC_GetHCLKFreq() function called within this function
*
* @note The MSI is used (enabled by hardware) as system clock source after
* start-up from Reset, wake-up from STOP and STANDBY mode, or in case
* of failure of the HSE used directly or indirectly as system clock
* (if the Clock Security System CSS is enabled).
*
* @note A switch from one clock source to another occurs only if the target
* clock source is ready (clock stable after start-up delay or PLL locked).
* If a clock source which is not yet ready is selected, the switch will
* occur when the clock source will be ready.
* You can use @ref HAL_RCC_GetClockConfig() function to know which clock is
* currently used as system clock source.
* @note Depending on the device voltage range, the software has to set correctly
* HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
* (for more details refer to section above "Initialization/de-initialization functions")
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
uint32_t tickstart = 0;
/* Check the parameters */
assert_param(RCC_ClkInitStruct != NULL);
assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
assert_param(IS_FLASH_LATENCY(FLatency));
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
must be correctly programmed according to the frequency of the CPU clock
(HCLK) and the supply voltage of the device. */
/* Increasing the number of wait states because of higher CPU frequency */
if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
{
return HAL_ERROR;
}
}
/*-------------------------- HCLK Configuration --------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
{
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
}
/*------------------------- SYSCLK Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* HSE is selected as System Clock Source */
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
{
/* Check the HSE ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
{
return HAL_ERROR;
}
}
/* PLL is selected as System Clock Source */
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
{
/* Check the PLL ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
{
return HAL_ERROR;
}
}
/* HSI is selected as System Clock Source */
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI)
{
/* Check the HSI ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
{
return HAL_ERROR;
}
}
/* MSI is selected as System Clock Source */
else
{
/* Check the MSI ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == RESET)
{
return HAL_ERROR;
}
}
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
/* Get Start Tick */
tickstart = HAL_GetTick();
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
{
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
{
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
}
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
{
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
{
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
}
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI)
{
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
{
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
}
else
{
while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_MSI)
{
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
}
}
/* Decreasing the number of wait states because of lower CPU frequency */
if(FLatency < (FLASH->ACR & FLASH_ACR_LATENCY))
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
{
return HAL_ERROR;
}
}
/*-------------------------- PCLK1 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
}
/*-------------------------- PCLK2 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> POSITION_VAL(RCC_CFGR_HPRE)];
/* Configure the source of time base considering new system clocks settings*/
HAL_InitTick (TICK_INT_PRIORITY);
return HAL_OK;
}
return 0;
}
/**
* @brief Returns the HCLK frequency
* @note Each time HCLK changes, this function must be called to update the
* right HCLK value. Otherwise, any configuration based on this function will be incorrect.
*
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
* and updated within this function
*
* @retval HCLK frequency
*/
uint32_t HAL_RCC_GetHCLKFreq(void)
{
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> POSITION_VAL(RCC_CFGR_HPRE)];
return SystemCoreClock;
}
/**
* @brief Returns the PCLK1 frequency
* @note Each time PCLK1 changes, this function must be called to update the
* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK1 frequency
*/
uint32_t HAL_RCC_GetPCLK1Freq(void)
{
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq() >> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> POSITION_VAL(RCC_CFGR_PPRE1)]);
}
return HAL_ERROR;
}
/**
* @brief Returns the HCLK frequency
* @note Each time HCLK changes, this function must be called to update the
* right HCLK value. Otherwise, any configuration based on this function will be incorrect.
*
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
* and updated within this function
*
* @retval HCLK frequency
*/
uint32_t HAL_RCC_GetHCLKFreq(void)
{
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_BITNUMBER];
return SystemCoreClock;
}
/**
* @brief Returns the PCLK1 frequency
* @note Each time PCLK1 changes, this function must be called to update the
* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK1 frequency
*/
uint32_t HAL_RCC_GetPCLK1Freq(void)
{
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq() >> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE)>> RCC_CFGR_PPRE_BITNUMBER]);
}
int main(int argc, char* argv[])
{
uint32_t freq = HAL_RCC_GetSysClockFreq();
uint32_t pclk1 = HAL_RCC_GetPCLK1Freq();
uint32_t pclk2 = HAL_RCC_GetPCLK2Freq();
(void) argc;
(void) argv;
relocate_interrupt_table();
TimeStamp::init();
colibri::UartTrace::init(115200 * 2);
drone_state = new DroneState();
printf("Starting main_task:, CPU freq: %lu, PCLK1 freq: %lu, PCLK2 freq: %lu\n", freq, pclk1, pclk2);
/* Create tasks */
xTaskCreate(
main_task, /* Function pointer */
"main_task", /* Task name - for debugging only*/
4 * configMINIMAL_STACK_SIZE, /* Stack depth in words */
(void*) NULL, /* Pointer to tasks arguments (parameter) */
tskIDLE_PRIORITY + 3UL, /* Task priority*/
&main_task_handle /* Task handle */
);
xTaskCreate(
battery_task, /* Function pointer */
"battery_task", /* Task name - for debugging only*/
configMINIMAL_STACK_SIZE, /* Stack depth in words */
(void*) NULL, /* Pointer to tasks arguments (parameter) */
tskIDLE_PRIORITY + 1UL, /* Task priority*/
&battery_task_handle /* Task handle */
);
xTaskCreate(
gps_task, /* Function pointer */
"gps_task", /* Task name - for debugging only*/
configMINIMAL_STACK_SIZE, /* Stack depth in words */
(void*) NULL, /* Pointer to tasks arguments (parameter) */
tskIDLE_PRIORITY + 1UL, /* Task priority*/
&gps_task_handle /* Task handle */
);
#if ENABLE_UART_TASK
xTaskCreate(
uart_task, /* Function pointer */
"uart_task", /* Task name - for debugging only*/
configMINIMAL_STACK_SIZE, /* Stack depth in words */
(void*) NULL, /* Pointer to tasks arguments (parameter) */
tskIDLE_PRIORITY + 1UL, /* Task priority*/
&uart_task_handle /* Task handle */
);
#endif
/*
* Disable the SysTick_IRQn and clean the priority
* and let the scheduler configure and enable it.
*/
NVIC_DisableIRQ(SysTick_IRQn);
NVIC_SetPriority(SysTick_IRQn, 0);
vTaskStartScheduler(); // this call will never return
}
/// \function freq([sys_freq])
///
/// If given no arguments, returns a tuple of clock frequencies:
/// (SYSCLK, HCLK, PCLK1, PCLK2).
///
/// If given an argument, sets the system frequency to that value in Hz.
/// Eg freq(120000000) gives 120MHz. Note that not all values are
/// supported and the largest supported frequency not greater than
/// the given sys_freq will be selected.
STATIC mp_obj_t pyb_freq(mp_uint_t n_args, const mp_obj_t *args) {
if (n_args == 0) {
// get
mp_obj_t tuple[4] = {
mp_obj_new_int(HAL_RCC_GetSysClockFreq()),
mp_obj_new_int(HAL_RCC_GetHCLKFreq()),
mp_obj_new_int(HAL_RCC_GetPCLK1Freq()),
mp_obj_new_int(HAL_RCC_GetPCLK2Freq()),
};
return mp_obj_new_tuple(4, tuple);
} else {
// set
mp_int_t wanted_sysclk = mp_obj_get_int(args[0]) / 1000000;
// default PLL parameters that give 48MHz on PLL48CK
uint32_t m = HSE_VALUE / 1000000, n = 336, p = 2, q = 7;
uint32_t sysclk_source;
// the following logic assumes HSE < HSI
if (HSE_VALUE / 1000000 <= wanted_sysclk && wanted_sysclk < HSI_VALUE / 1000000) {
// use HSE as SYSCLK
sysclk_source = RCC_SYSCLKSOURCE_HSE;
} else if (HSI_VALUE / 1000000 <= wanted_sysclk && wanted_sysclk < 24) {
// use HSI as SYSCLK
sysclk_source = RCC_SYSCLKSOURCE_HSI;
} else {
// search for a valid PLL configuration that keeps USB at 48MHz
for (; wanted_sysclk > 0; wanted_sysclk--) {
for (p = 2; p <= 8; p += 2) {
// compute VCO_OUT
mp_uint_t vco_out = wanted_sysclk * p;
// make sure VCO_OUT is between 192MHz and 432MHz
if (vco_out < 192 || vco_out > 432) {
continue;
}
// make sure Q is an integer
if (vco_out % 48 != 0) {
continue;
}
// solve for Q to get PLL48CK at 48MHz
q = vco_out / 48;
// make sure Q is in range
if (q < 2 || q > 15) {
continue;
}
// make sure N/M is an integer
if (vco_out % (HSE_VALUE / 1000000) != 0) {
continue;
}
// solve for N/M
mp_uint_t n_by_m = vco_out / (HSE_VALUE / 1000000);
// solve for M, making sure VCO_IN (=HSE/M) is between 1MHz and 2MHz
m = 192 / n_by_m;
while (m < (HSE_VALUE / 2000000) || n_by_m * m < 192) {
m += 1;
}
if (m > (HSE_VALUE / 1000000)) {
continue;
}
// solve for N
n = n_by_m * m;
// make sure N is in range
if (n < 192 || n > 432) {
continue;
}
// found values!
sysclk_source = RCC_SYSCLKSOURCE_PLLCLK;
goto set_clk;
}
}
nlr_raise(mp_obj_new_exception_msg(&mp_type_ValueError, "can't make valid freq"));
}
set_clk:
//printf("%lu %lu %lu %lu %lu\n", sysclk_source, m, n, p, q);
// let the USB CDC have a chance to process before we change the clock
HAL_Delay(USBD_CDC_POLLING_INTERVAL + 2);
// desired system clock source is in sysclk_source
RCC_ClkInitTypeDef RCC_ClkInitStruct;
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
if (sysclk_source == RCC_SYSCLKSOURCE_PLLCLK) {
// set HSE as system clock source to allow modification of the PLL configuration
// we then change to PLL after re-configuring PLL
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSE;
} else {
// directly set the system clock source as desired
RCC_ClkInitStruct.SYSCLKSource = sysclk_source;
}
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
goto fail;
}
// re-configure PLL
// even if we don't use the PLL for the system clock, we still need it for USB, RNG and SDIO
RCC_OscInitTypeDef RCC_OscInitStruct;
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
RCC_OscInitStruct.PLL.PLLM = m;
RCC_OscInitStruct.PLL.PLLN = n;
RCC_OscInitStruct.PLL.PLLP = p;
RCC_OscInitStruct.PLL.PLLQ = q;
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
goto fail;
}
// set PLL as system clock source if wanted
if (sysclk_source == RCC_SYSCLKSOURCE_PLLCLK) {
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) {
goto fail;
}
}
// re-init TIM3 for USB CDC rate
timer_tim3_init();
return mp_const_none;
fail:;
void NORETURN __fatal_error(const char *msg);
__fatal_error("can't change freq");
}
}
static rt_err_t stm32_spi_init(struct stm32_spi *spi_drv, struct rt_spi_configuration *cfg)
{
RT_ASSERT(spi_drv != RT_NULL);
RT_ASSERT(cfg != RT_NULL);
SPI_HandleTypeDef *spi_handle = &spi_drv->handle;
if (cfg->mode & RT_SPI_SLAVE)
{
spi_handle->Init.Mode = SPI_MODE_SLAVE;
}
else
{
spi_handle->Init.Mode = SPI_MODE_MASTER;
}
if (cfg->mode & RT_SPI_3WIRE)
{
spi_handle->Init.Direction = SPI_DIRECTION_1LINE;
}
else
{
spi_handle->Init.Direction = SPI_DIRECTION_2LINES;
}
if (cfg->data_width == 8)
{
spi_handle->Init.DataSize = SPI_DATASIZE_8BIT;
spi_handle->TxXferSize = 8;
spi_handle->RxXferSize = 8;
}
else if (cfg->data_width == 16)
{
spi_handle->Init.DataSize = SPI_DATASIZE_16BIT;
}
else
{
return RT_EIO;
}
if (cfg->mode & RT_SPI_CPHA)
{
spi_handle->Init.CLKPhase = SPI_PHASE_2EDGE;
}
else
{
spi_handle->Init.CLKPhase = SPI_PHASE_1EDGE;
}
if (cfg->mode & RT_SPI_CPOL)
{
spi_handle->Init.CLKPolarity = SPI_POLARITY_HIGH;
}
else
{
spi_handle->Init.CLKPolarity = SPI_POLARITY_LOW;
}
if (cfg->mode & RT_SPI_NO_CS)
{
spi_handle->Init.NSS = SPI_NSS_SOFT;
}
else
{
spi_handle->Init.NSS = SPI_NSS_SOFT;
}
uint32_t SPI_APB_CLOCK;
#if defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0)
SPI_APB_CLOCK = HAL_RCC_GetPCLK1Freq();
#else
SPI_APB_CLOCK = HAL_RCC_GetPCLK2Freq();
#endif
if (cfg->max_hz >= SPI_APB_CLOCK / 2)
{
spi_handle->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
}
else if (cfg->max_hz >= SPI_APB_CLOCK / 4)
{
spi_handle->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_4;
}
else if (cfg->max_hz >= SPI_APB_CLOCK / 8)
{
spi_handle->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_8;
}
else if (cfg->max_hz >= SPI_APB_CLOCK / 16)
{
spi_handle->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_16;
}
else if (cfg->max_hz >= SPI_APB_CLOCK / 32)
{
spi_handle->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_32;
}
else if (cfg->max_hz >= SPI_APB_CLOCK / 64)
{
spi_handle->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_64;
}
else if (cfg->max_hz >= SPI_APB_CLOCK / 128)
{
spi_handle->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_128;
}
else
{
/* min prescaler 256 */
spi_handle->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_256;
}
LOG_D("sys freq: %d, pclk2 freq: %d, SPI limiting freq: %d, BaudRatePrescaler: %d",
HAL_RCC_GetSysClockFreq(),
SPI_APB_CLOCK,
cfg->max_hz,
spi_handle->Init.BaudRatePrescaler);
if (cfg->mode & RT_SPI_MSB)
{
spi_handle->Init.FirstBit = SPI_FIRSTBIT_MSB;
}
else
{
spi_handle->Init.FirstBit = SPI_FIRSTBIT_LSB;
}
spi_handle->Init.TIMode = SPI_TIMODE_DISABLE;
spi_handle->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
spi_handle->State = HAL_SPI_STATE_RESET;
#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0)
spi_handle->Init.NSSPMode = SPI_NSS_PULSE_DISABLE;
#endif
if (HAL_SPI_Init(spi_handle) != HAL_OK)
{
return RT_EIO;
}
#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) \
|| defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32G0)
SET_BIT(spi_handle->Instance->CR2, SPI_RXFIFO_THRESHOLD_HF);
#endif
/* DMA configuration */
if (spi_drv->spi_dma_flag & SPI_USING_RX_DMA_FLAG)
{
HAL_DMA_Init(&spi_drv->dma.handle_rx);
__HAL_LINKDMA(&spi_drv->handle, hdmarx, spi_drv->dma.handle_rx);
/* NVIC configuration for DMA transfer complete interrupt */
HAL_NVIC_SetPriority(spi_drv->config->dma_rx->dma_irq, 0, 0);
HAL_NVIC_EnableIRQ(spi_drv->config->dma_rx->dma_irq);
}
if (spi_drv->spi_dma_flag & SPI_USING_TX_DMA_FLAG)
{
HAL_DMA_Init(&spi_drv->dma.handle_tx);
__HAL_LINKDMA(&spi_drv->handle, hdmatx, spi_drv->dma.handle_tx);
/* NVIC configuration for DMA transfer complete interrupt */
HAL_NVIC_SetPriority(spi_drv->config->dma_tx->dma_irq, 0, 1);
HAL_NVIC_EnableIRQ(spi_drv->config->dma_tx->dma_irq);
}
__HAL_SPI_ENABLE(spi_handle);
LOG_D("%s init done", spi_drv->config->bus_name);
return RT_EOK;
}
static rt_err_t configure(struct rt_spi_device* device,
struct rt_spi_configuration* configuration)
{
struct rt_spi_bus * spi_bus = (struct rt_spi_bus *)device->bus;
struct gd32f4_spi *f4_spi = (struct gd32f4_spi *)spi_bus->parent.user_data;
spi_parameter_struct spi_init_struct;
uint32_t spi_periph = f4_spi->spi_periph;
RT_ASSERT(device != RT_NULL);
RT_ASSERT(configuration != RT_NULL);
/* data_width */
if(configuration->data_width <= 8)
{
spi_init_struct.frame_size = SPI_FRAMESIZE_8BIT;
}
else if(configuration->data_width <= 16)
{
spi_init_struct.frame_size = SPI_FRAMESIZE_16BIT;
}
else
{
return RT_EIO;
}
/* baudrate */
{
rcu_clock_freq_enum spi_src;
uint32_t spi_apb_clock;
uint32_t max_hz;
max_hz = configuration->max_hz;
DEBUG_PRINTF("sys freq: %d\n", HAL_RCC_GetSysClockFreq());
DEBUG_PRINTF("pclk2 freq: %d\n", HAL_RCC_GetPCLK2Freq());
DEBUG_PRINTF("max freq: %d\n", max_hz);
if (spi_periph == SPI1 || spi_periph == SPI2)
{
spi_src = CK_APB1;
}
else
{
spi_src = CK_APB2;
}
spi_apb_clock = rcu_clock_freq_get(spi_src);
if(max_hz >= spi_apb_clock/2)
{
spi_init_struct.prescale = SPI_PSC_2;
}
else if (max_hz >= spi_apb_clock/4)
{
spi_init_struct.prescale = SPI_PSC_4;
}
else if (max_hz >= spi_apb_clock/8)
{
spi_init_struct.prescale = SPI_PSC_8;
}
else if (max_hz >= spi_apb_clock/16)
{
spi_init_struct.prescale = SPI_PSC_16;
}
else if (max_hz >= spi_apb_clock/32)
{
spi_init_struct.prescale = SPI_PSC_32;
}
else if (max_hz >= spi_apb_clock/64)
{
spi_init_struct.prescale = SPI_PSC_64;
}
else if (max_hz >= spi_apb_clock/128)
{
spi_init_struct.prescale = SPI_PSC_128;
}
else
{
/* min prescaler 256 */
spi_init_struct.prescale = SPI_PSC_256;
}
} /* baudrate */
switch(configuration->mode)
{
case RT_SPI_MODE_0:
spi_init_struct.clock_polarity_phase = SPI_CK_PL_LOW_PH_1EDGE;
break;
case RT_SPI_MODE_1:
spi_init_struct.clock_polarity_phase = SPI_CK_PL_LOW_PH_2EDGE;
break;
case RT_SPI_MODE_2:
spi_init_struct.clock_polarity_phase = SPI_CK_PL_HIGH_PH_1EDGE;
break;
case RT_SPI_MODE_3:
spi_init_struct.clock_polarity_phase = SPI_CK_PL_HIGH_PH_2EDGE;
break;
}
/* MSB or LSB */
if(configuration->mode & RT_SPI_MSB)
{
spi_init_struct.endian = SPI_ENDIAN_MSB;
}
else
{
spi_init_struct.endian = SPI_ENDIAN_LSB;
}
spi_init_struct.trans_mode = SPI_TRANSMODE_FULLDUPLEX;
spi_init_struct.device_mode = SPI_MASTER;
spi_init_struct.nss = SPI_NSS_SOFT;
spi_crc_off(spi_periph);
/* init SPI */
spi_init(spi_periph, &spi_init_struct);
/* Enable SPI_MASTER */
spi_enable(spi_periph);
return RT_EOK;
};
