/* disable all device interrupts */
A_STATUS DevMaskInterrupts(AR6K_DEVICE *pDev)
{
/* mask the interrupt at the HIF layer, we don't want a stray interrupt taken while
* we zero out our shadow registers in DevDisableInterrupts()*/
HIFMaskInterrupt(pDev->HIFDevice);
return DevDisableInterrupts(pDev);
}
/* disable all device interrupts */
int DevMaskInterrupts(struct ar6k_device *pDev)
{
/* mask the interrupt at the HIF layer, we don't want a stray interrupt taken while
* we zero out our shadow registers in DevDisableInterrupts()*/
HIFMaskInterrupt(pDev->HIFDevice);
return DevDisableInterrupts(pDev);
}
void
HTCStop(HTC_TARGET *target)
{
A_UINT32 count;
A_STATUS status;
A_UINT32 address;
HIF_REQUEST request;
A_UINT32 window_data;
HTC_ENDPOINT *endPoint;
HTC_REG_REQUEST_LIST *regList;
HTC_REG_REQUEST_ELEMENT *element;
HTC_DATA_REQUEST_QUEUE *sendQueue;
HTC_DATA_REQUEST_QUEUE *recvQueue;
HTC_DEBUG_PRINTF(ATH_LOG_TRC, "HTCStop: Enter");
/* Disable all the dragon interrupts */
target->table.int_status_enable = 0;
target->table.cpu_int_status_enable = 0;
target->table.error_status_enable = 0;
target->table.counter_int_status_enable = 0;
HIF_FRAME_REQUEST(&request, HIF_WRITE, HIF_EXTENDED_IO, HIF_SYNCHRONOUS,
HIF_BYTE_BASIS, HIF_INCREMENTAL_ADDRESS);
address = getRegAddr(INT_STATUS_ENABLE_REG, ENDPOINT_UNUSED);
status = HIFReadWrite(target->device, address,
&target->table.int_status_enable, 4, &request, NULL);
AR_DEBUG_ASSERT(status == A_OK);
/* Disable the host controller interrupts */
HIFMaskInterrupt(target->device);
/* Flush all the queues and return the buffers to their owner */
for (count = ENDPOINT1; count <= ENDPOINT4; count ++) {
endPoint = &target->endPoint[count];
/* Decrement the number of credits consumed */
if (endPoint->txCreditsConsumed) {
HIF_FRAME_REQUEST(&request, HIF_WRITE, HIF_EXTENDED_IO,
HIF_SYNCHRONOUS, HIF_BYTE_BASIS,
HIF_FIXED_ADDRESS);
address = getRegAddr(TX_CREDIT_COUNTER_DECREMENT_REG, count);
#ifdef ONLY_16BIT
status = HIFReadWrite(target->device, address,
(A_UCHAR *)endPoint->txCreditsAvailable,
endPoint->txCreditsConsumed * 2, &request, NULL);
#else
status = HIFReadWrite(target->device, address,
endPoint->txCreditsAvailable,
endPoint->txCreditsConsumed, &request, NULL);
#endif
AR_DEBUG_ASSERT(status == A_OK);
}
SET_TX_CREDITS_AVAILABLE(endPoint, 0);
SET_TX_CREDITS_CONSUMED(endPoint, 0);
#ifdef DEBUG
txcreditsavailable[count] = GET_TX_CREDITS_AVAILABLE(endPoint);
txcreditsconsumed[count] = GET_TX_CREDITS_CONSUMED(endPoint);
#endif
endPoint->txCreditsIntrEnable = FALSE;
endPoint->rxLengthPending = 0;
endPoint->enabled = FALSE;
/* Flush the Pending Receive Queue */
HTC_DEBUG_PRINTF(ATH_LOG_INF,
"Flushing the recv queue & returning the buffers\n");
recvQueue = &endPoint->recvQueue;
flushMboxQueue(endPoint, recvQueue, HTC_BUFFER_RECEIVED);
/* Flush the Pending Send Queue */
HTC_DEBUG_PRINTF(ATH_LOG_INF,
"Flushing the send queue & returning the buffers\n");
sendQueue = &endPoint->sendQueue;
flushMboxQueue(endPoint, sendQueue, HTC_BUFFER_SENT);
}
/* Clear the tx counters */
memset(tx_attempt, 0, sizeof(tx_attempt));
memset(tx_post, 0, sizeof(tx_post));
memset(tx_complete, 0, sizeof(tx_complete));
/* Attempting a force reset of the target */
window_data = RESET_CONTROL_COLD_RST_MASK;
HIF_FRAME_REQUEST(&request, HIF_WRITE, HIF_EXTENDED_IO, HIF_SYNCHRONOUS,
HIF_BYTE_BASIS, HIF_INCREMENTAL_ADDRESS);
address = getRegAddr(WINDOW_DATA_REG, ENDPOINT_UNUSED);
status = HIFReadWrite(target->device, address, (A_UCHAR *)&window_data,
4, &request, NULL);
AR_DEBUG_ASSERT(status == A_OK);
_WRITE_WINDOW_ADDR(target, WINDOW_WRITE_ADDR_REG, RESET_CONTROL_ADDRESS);
/*
* Read back the RESET CAUSE register to ensure that the cold reset
* went through.
*/
A_MDELAY(2000); /* 2 Second delay to allow dragon to settle down */
_WRITE_WINDOW_ADDR(target, WINDOW_READ_ADDR_REG, RESET_CAUSE_ADDRESS);
window_data = 0;
HIF_FRAME_REQUEST(&request, HIF_READ, HIF_EXTENDED_IO, HIF_SYNCHRONOUS,
HIF_BYTE_BASIS, HIF_INCREMENTAL_ADDRESS);
address = getRegAddr(WINDOW_DATA_REG, ENDPOINT_UNUSED);
status = HIFReadWrite(target->device, address, (A_UCHAR *)&window_data,
4, &request, NULL);
AR_DEBUG_ASSERT(status == A_OK);
HTC_DEBUG_PRINTF(ATH_LOG_INF, "window data: %d\n", window_data);
window_data &= RESET_CAUSE_LAST_MASK;
if (window_data != 2) {
HTC_DEBUG_PRINTF(ATH_LOG_ERR, "Unable to cold reset the target\n");
}
/*
* Ensure that all the pending asynchronous register read/writes have
* been finished.
*/
regList = &target->regList;
for (count = 0; count < HTC_REG_REQUEST_LIST_SIZE; count ++) {
element = ®List->element[count];
AR_DEBUG_ASSERT(IS_ELEMENT_FREE(element));
}
/* Initialize the shadow copy of the target register table */
A_MEMZERO(&target->table, sizeof(HTC_REGISTER_TABLE));
target->ready = FALSE;
HTC_DEBUG_PRINTF(ATH_LOG_TRC, "HTCStop: Exit");
}
