void dma_transferblock_fromregister(uint32_t source, uint32_t dest, uint32_t count) { if (!dma_sanitycheck()) { return; } dma_basicsetup(dest); dma_register_counth = HIGHWORD(count); dma_register_countl = LOWWORD(count); dma_register_srch = HIGHWORD(source); dma_register_srcl = LOWWORD(source); dma_register_jumpafter = 0; dma_register_config = DMA_REGISTER_CONFIG_SIZE | DMA_REGISTER_CONFIG_MODE_BLOCK | DMA_REGISTER_CONFIG_DSTACT_INC; dma_bumpwindow(); }
void dma_transfer_nonlinearblock(uint32_t source, uint32_t dest, uint32_t count, uint16_t jumpafter, uint16_t jumplength) { if (!dma_sanitycheck()) { return; } dma_basicsetup(dest); dma_register_counth = HIGHWORD(count); dma_register_countl = LOWWORD(count); dma_register_srch = HIGHWORD(source); dma_register_srcl = LOWWORD(source); dma_register_jumpafter = jumpafter; dma_register_jumplength = jumplength; dma_register_config = DMA_REGISTER_CONFIG_SIZE | DMA_REGISTER_CONFIG_MODE_BLOCK | DMA_REGISTER_CONFIG_SRCACT_INC | DMA_REGISTER_CONFIG_DSTACT_INC; dma_bumpwindow(); }
/** Set RAM address \param pDev - pointer to the device interface \param ram - RAM flag : D_RAM or P_RAM \param StartAddr - RAM sector start address \param StopAddr - RAM sector end address \return IFX_SUCCESS or IFX_ERROR */ IFX_int32_t Dwld_setRAM(VINETIC_DEVICE *pDev, VINETIC_FW_RAM ram, IFX_uint32_t StartAddr, IFX_uint32_t StopAddr) { IFX_int32_t cnt = 0, err = IFX_ERROR; IFX_uint16_t pCmd[6] = {0}; /* set Cmd 1 */ pCmd[0] = CMD1_EOP | MEM_PAGE; /* Set Cmd 2 and Data words */ switch(ram) { case D_RAM: pCmd[1] = ECMD_SET_DRAM_ADR; pCmd[2] = LOWWORD(StartAddr); cnt = 1; if (StopAddr != 0) { pCmd[3] = LOWWORD(StopAddr); cnt = 2; } break; case P_RAM: pCmd[1] = ECMD_SET_PRAM_ADR; pCmd[2] = HIGHWORD(StartAddr); pCmd[3] = LOWWORD(StartAddr); cnt = 2; if (StopAddr != 0) { pCmd[4] = HIGHWORD(StopAddr); pCmd[5] = LOWWORD(StopAddr); cnt = 4; } break; } if (cnt != 0) err = CmdWrite (pDev, pCmd, cnt); return err; }
void dma_fillblock_nonlinear(uint32_t dest, uint16_t data, uint32_t count, uint16_t jumpafter, uint16_t jumplength) { if (!dma_sanitycheck()) { return; } dma_basicsetup(dest); dma_register_counth = HIGHWORD(count); dma_register_countl = LOWWORD(count); dma_register_datal = data & 0xFFFF; dma_register_jumpafter = jumpafter; dma_register_jumplength = jumplength; dma_register_config = DMA_REGISTER_CONFIG_MODE_FILL | DMA_REGISTER_CONFIG_SIZE | DMA_REGISTER_CONFIG_DSTACT_INC; dma_bumpwindow(); }
void dma_fillblock(uint32_t dest, uint16_t data, uint32_t count) { if (!dma_sanitycheck()) { return; } dma_basicsetup(dest); dma_register_counth = HIGHWORD(count); dma_register_countl = LOWWORD(count); dma_register_datal = data & 0xFFFF; dma_register_jumpafter = 0; //*dma_register_config |= DMA_REGISTER_CONFIG_START | DMA_REGISTER_CONFIG_SIZE | DMA_REGISTER_CONFIG_MODE // | DMA_REGISTER_CONFIG_DATAACT_INVERSE | DMA_REGISTER_CONFIG_DSTACT_INCTWO; dma_register_config = DMA_REGISTER_CONFIG_MODE_FILL | DMA_REGISTER_CONFIG_SIZE | DMA_REGISTER_CONFIG_DSTACT_INC; dma_bumpwindow(); }
/** Play a local tone on one or both tone generators. \param pCh - handle to a VINETIC channel structure \param vers - chip revision \param freqA - frequency A in mHz \param freqB - frequency B in mHz, or zero if not applicable \return IFX_SUCCESS or IFX_ERROR */ IFX_int32_t Tone_TG_SetCoeff (VINETIC_CHANNEL* pCh, IFX_uint8_t vers, IFX_int32_t freqA, IFX_int32_t freqB) { IFX_int32_t ret; #ifdef VIN_V14_SUPPORT COEFF_TAB_ENTRY tab_entry; IFX_uint16_t pData [4] = {0}; #endif /* VIN_V14_SUPPORT */ switch (vers) { #ifdef VIN_V14_SUPPORT case VINETIC_V1x: tab_entry.quantVal = freqA; /* now get the coefficient from global frequency / coefficient table. result is returned in pEntry */ ret = Cram_getUnitCoef (IOSET, &tab_entry, (COEFF_TAB_ENTRY *) VINETIC_CRAM_TGFreqQuantVal_Table); if (ret != IFX_SUCCESS) return IFX_ERROR; pData[0] = LOWWORD ((IFX_uint32_t)tab_entry.CRAMcoeff); pData[1] = HIGHWORD ((IFX_uint32_t)tab_entry.CRAMcoeff); /* c1 = tab_entry.CRAMcoeff; */ if (freqB) { tab_entry.quantVal = (IFX_int32_t)freqB; ret = Cram_getUnitCoef (IOSET, &tab_entry, (COEFF_TAB_ENTRY *) VINETIC_CRAM_TGFreqQuantVal_Table); if (ret != IFX_SUCCESS) return IFX_ERROR; pData[2] = LOWWORD ((IFX_uint32_t)tab_entry.CRAMcoeff); pData[3] = HIGHWORD ((IFX_uint32_t)tab_entry.CRAMcoeff); /* c2 = tab_entry.CRAMcoeff; */ ret = RegWrite (pCh->pParent, CMD1_COP | (pCh->nChannel - 1), pData, 4, CRAM_PTG1); } else { ret = RegWrite (pCh->pParent, CMD1_COP | (pCh->nChannel - 1), pData, 2, CRAM_PTG1); } break; #endif /* VIN_V14_SUPPORT */ #ifdef VIN_V21_SUPPORT case VINETIC_V2x: /* set the frequency for the first TG */ ret = setRegVal (pCh, TG1F_REG, freqA); if (ret == IFX_SUCCESS) ret = wrReg (pCh, TG1F_REG); /* set the frequency for the second TG */ if ((ret == IFX_SUCCESS) && (freqB != 0)) { ret = setRegVal (pCh, TG2F_REG, freqB); if (ret == IFX_SUCCESS) ret = wrReg (pCh, TG2F_REG); } break; #endif /* VIN_V21_SUPPORT */ default: return IFX_ERROR; } if (ret == IFX_SUCCESS) { DSCR.value &= ~(DSCR_TG2_EN); /* data to start tone generator 1 */ DSCR.value |= (DSCR_COR8 | DSCR_PTG | DSCR_TG1_EN); if (freqB) DSCR.value |= DSCR_TG2_EN; /* call target function to set tone generator(s) */ ret = wrReg (pCh, DSCR_REG); } return ret; }
static void dma_basicsetup(uint32_t dest) { dma_register_desth = HIGHWORD(dest); dma_register_destl = LOWWORD(dest); }
VOID HalpResetAllProcessors ( VOID ) /*++ Routine Description: This procedure is called by the HalpReboot routine. It is called in response to a system reset request. This routine generates a reboot request via the APIC's ICR. This routine will NOT return. --*/ { ULONG j; PKIDTENTRY IdtPtr; PKPRCB Prcb; #ifndef NT_UP HalpProcessorsNotHalted = HalpMpInfoTable.NtProcessors; #else // // Only this processor needs to be halted // HalpProcessorsNotHalted = 1; #endif // // Set all processors NMI handlers // for (j = 0; j < HalpMpInfoTable.NtProcessors; ++j) { IdtPtr = HalpProcessorPCR[j]->IDT; IdtPtr[IDT_NMI_VECTOR].Offset = LOWWORD(HalpApicRebootService); IdtPtr[IDT_NMI_VECTOR].ExtendedOffset = HIGHWORD(HalpApicRebootService); IdtPtr[IDT_NMI_VECTOR].Selector = KGDT_R0_CODE; IdtPtr[IDT_NMI_VECTOR].Access = D_INT032; } if (HalpProcessorsNotHalted > 1) { // // Wait for the ICR to become free // if (HalpWaitForPending (0xFFFF, pLocalApic + LU_INT_CMD_LOW/4)) { // // For P54c or better processors, reboot by sending all processors // NMIs. For pentiums we send interrupts, since there are some // pentium MP machines where the NMIs method does not work. // // The NMI method is better. // Prcb = KeGetCurrentPrcb(); j = Prcb->CpuType << 16 | (Prcb->CpuStep & 0xff00); if (j > 0x50100) { // // Get other processors attention with an NMI // pLocalApic[LU_INT_CMD_LOW/4] = (ICR_ALL_EXCL_SELF | DELIVER_NMI); // // Wait 5ms and see if any processors took the NMI. If not, // go do it the old way. // KeStallExecutionProcessor(5000); if (HalpProcessorsNotHalted != HalpMpInfoTable.NtProcessors) { // // Reboot local // HalpApicRebootService(); } } // // Signal other processors which also may be waiting to // reboot the machine, that it's time to go // HalpRebootNow = HalpResetThisProcessor; // // Send a reboot interrupt // pLocalApic[LU_INT_CMD_LOW/4] = (ICR_ALL_INCL_SELF | APIC_REBOOT_VECTOR); // // we're done - set TPR to zero so the reboot interrupt will happen // pLocalApic[LU_TPR/4] = 0; _asm sti ; for (; ;) ; } } // // Reset the old fashion way // WRITE_PORT_UCHAR(KEYBPORT, RESET); }
NTSTATUS KeI386FlatToGdtSelector( IN ULONG SelectorBase, IN USHORT Length, IN USHORT Selector ) /*++ Routine Description: This function converts a 32-bit flat address to a GDT selector-offset pair. The segment set up is always 16-bit ring 0 data segment. Arguments: SelectorBase - Supplies 32 bit flat address to be set as the base address of the desired selector. Length - Supplies the Length of the segment. The Length is a 16 bit value and zero means 64KB. Selector - Supplies the selector to be set up. Return Value: STATUS_SUCCESS - If the requested LID is released. STATUS_ABIOS_NOT_PRESENT - If there is no ABIOS support in the system. STATUS_ABIOS_INVALID_SELECTOR - If the selector supplied is invalid. --*/ { PKGDTENTRY GdtEntry, GdtEntry1; KIRQL OldIrql; ULONG i; if (!KiAbiosPresent) { return STATUS_ABIOS_NOT_PRESENT; } if (Selector < RESERVED_GDT_ENTRIES * sizeof(KGDTENTRY)) { return STATUS_ABIOS_INVALID_SELECTOR; } else { ExAcquireSpinLock(&KiAbiosGdtLock, &OldIrql); GdtEntry = (PKGDTENTRY)(KiAbiosGdt[0] + Selector); GdtEntry->LimitLow = (USHORT)(Length - 1); GdtEntry->BaseLow = LOWWORD(SelectorBase); GdtEntry->HighWord.Bytes.BaseMid = LOWBYTE(HIGHWORD(SelectorBase)); GdtEntry->HighWord.Bytes.BaseHi = HIGHBYTE(HIGHWORD(SelectorBase)); GdtEntry->HighWord.Bits.Pres = 1; GdtEntry->HighWord.Bits.Type = TYPE_DATA; GdtEntry->HighWord.Bits.Dpl = DPL_SYSTEM; for (i = 1; i < (ULONG)KeNumberProcessors; i++) { GdtEntry1 = (PKGDTENTRY)(KiAbiosGdt[i] + Selector); *GdtEntry1 = *GdtEntry; } ExReleaseSpinLock(&KiAbiosGdtLock, OldIrql); return STATUS_SUCCESS; } }