static short Hpi6000_SendHostCommand( struct hpi_adapter_obj *pao, u16 wDspIndex, u32 dwHostCmd ) { struct dsp_obj *pdo = &(*(struct hpi_hw_obj *)pao->priv).ado[wDspIndex]; u32 dwTimeout = TIMEOUT; /* set command */ do { HpiWriteWord(pdo, HPI_HIF_ADDR(dwHostCmd), dwHostCmd); /* flush the FIFO */ HpiSetAddress(pdo, HPI_HIF_ADDR(dwHostCmd)); } while (Hpi6000_Check_PCI2040_ErrorFlag(pao, H6WRITE) && --dwTimeout); /* reset the interrupt bit */ iowrite32(0x00040004, pdo->prHPIControl); if (dwTimeout) return 0; else return 1; }
static short hpi6000_get_data(struct hpi_adapter_obj *pao, u16 dsp_index, struct hpi_message *phm, struct hpi_response *phr) { struct hpi_hw_obj *phw = pao->priv; struct dsp_obj *pdo = &phw->ado[dsp_index]; u32 data_got = 0; u16 ack; u32 length, address; u32 *p_data = (u32 *)phm->u.d.u.data.pb_data; (void)phr; /* this parameter not used! */ /* round dwDataSize down to nearest 4 bytes */ while (data_got < (phm->u.d.u.data.data_size & ~3L)) { ack = hpi6000_wait_dsp_ack(pao, dsp_index, HPI_HIF_IDLE); if (ack & HPI_HIF_ERROR_MASK) return HPI6000_ERROR_GET_DATA_IDLE_TIMEOUT; if (hpi6000_send_host_command(pao, dsp_index, HPI_HIF_GET_DATA)) return HPI6000_ERROR_GET_DATA_CMD; hpi6000_send_dsp_interrupt(pdo); ack = hpi6000_wait_dsp_ack(pao, dsp_index, HPI_HIF_GET_DATA); if (ack & HPI_HIF_ERROR_MASK) return HPI6000_ERROR_GET_DATA_ACK; /* get the address and size */ do { address = hpi_read_word(pdo, HPI_HIF_ADDR(address)); length = hpi_read_word(pdo, HPI_HIF_ADDR(length)); } while (hpi6000_check_PCI2040_error_flag(pao, H6READ)); /* read the data */ { u32 len = length; u32 blk_len = 512; while (len) { if (len < blk_len) blk_len = len; if (hpi6000_dsp_block_read32(pao, dsp_index, address, p_data, blk_len)) return HPI6000_ERROR_GET_DATA_READ; address += blk_len * 4; p_data += blk_len; len -= blk_len; } } if (hpi6000_send_host_command(pao, dsp_index, HPI_HIF_IDLE)) return HPI6000_ERROR_GET_DATA_IDLECMD; hpi6000_send_dsp_interrupt(pdo); data_got += length * 4; } return 0; }
static short hpi6000_send_host_command(struct hpi_adapter_obj *pao, u16 dsp_index, u32 host_cmd) { struct hpi_hw_obj *phw = pao->priv; struct dsp_obj *pdo = &phw->ado[dsp_index]; u32 timeout = TIMEOUT; /* set command */ do { hpi_write_word(pdo, HPI_HIF_ADDR(host_cmd), host_cmd); /* flush the FIFO */ hpi_set_address(pdo, HPI_HIF_ADDR(host_cmd)); } while (hpi6000_check_PCI2040_error_flag(pao, H6WRITE) && --timeout); /* reset the interrupt bit */ iowrite32(0x00040004, pdo->prHPI_control); if (timeout) return 0; else return 1; }
static short Hpi6000_WaitDspAck( struct hpi_adapter_obj *pao, u16 wDspIndex, u32 dwAckValue ) { struct dsp_obj *pdo = &(*(struct hpi_hw_obj *)pao->priv).ado[wDspIndex]; u32 dwAck = 0L; u32 dwTimeout; u32 dwHPIC = 0L; /* wait for host interrupt to signal ack is ready */ dwTimeout = TIMEOUT; while (--dwTimeout) { dwHPIC = ioread32(pdo->prHPIControl); if (dwHPIC & 0x04) /* 0x04 = HINT from DSP */ break; } if (dwTimeout == 0) return HPI_HIF_ERROR_MASK; /* wait for dwAckValue */ dwTimeout = TIMEOUT; while (--dwTimeout) { /* read the ack mailbox */ dwAck = HpiReadWord(pdo, HPI_HIF_ADDR(dwDspAck)); if (dwAck == dwAckValue) break; if ((dwAck & HPI_HIF_ERROR_MASK) & !Hpi6000_Check_PCI2040_ErrorFlag(pao, H6READ)) break; /*for (i=0;i<1000;i++) */ /* dwPause=i+1; */ } if (dwAck & HPI_HIF_ERROR_MASK) /* indicates bad read from DSP - typically 0xffffff is read for some reason */ dwAck = HPI_HIF_ERROR_MASK; if (dwTimeout == 0) dwAck = HPI_HIF_ERROR_MASK; return (short)dwAck; }
static short hpi6000_wait_dsp_ack(struct hpi_adapter_obj *pao, u16 dsp_index, u32 ack_value) { struct hpi_hw_obj *phw = pao->priv; struct dsp_obj *pdo = &phw->ado[dsp_index]; u32 ack = 0L; u32 timeout; u32 hPIC = 0L; /* wait for host interrupt to signal ack is ready */ timeout = TIMEOUT; while (--timeout) { hPIC = ioread32(pdo->prHPI_control); if (hPIC & 0x04) /* 0x04 = HINT from DSP */ break; } if (timeout == 0) return HPI_HIF_ERROR_MASK; /* wait for dwAckValue */ timeout = TIMEOUT; while (--timeout) { /* read the ack mailbox */ ack = hpi_read_word(pdo, HPI_HIF_ADDR(dsp_ack)); if (ack == ack_value) break; if ((ack & HPI_HIF_ERROR_MASK) && !hpi6000_check_PCI2040_error_flag(pao, H6READ)) break; /*for (i=0;i<1000;i++) */ /* dwPause=i+1; */ } if (ack & HPI_HIF_ERROR_MASK) /* indicates bad read from DSP - typically 0xffffff is read for some reason */ ack = HPI_HIF_ERROR_MASK; if (timeout == 0) ack = HPI_HIF_ERROR_MASK; return (short)ack; }
static short hpi6000_adapter_boot_load_dsp(struct hpi_adapter_obj *pao, u32 *pos_error_code) { struct hpi_hw_obj *phw = pao->priv; short error; u32 timeout; u32 read = 0; u32 i = 0; u32 data = 0; u32 j = 0; u32 test_addr = 0x80000000; u32 test_data = 0x00000001; u32 dw2040_reset = 0; u32 dsp_index = 0; u32 endian = 0; u32 adapter_info = 0; u32 delay = 0; struct dsp_code dsp_code; u16 boot_load_family = 0; /* NOTE don't use wAdapterType in this routine. It is not setup yet */ switch (pao->pci.pci_dev->subsystem_device) { case 0x5100: case 0x5110: /* ASI5100 revB or higher with C6711D */ case 0x5200: /* ASI5200 PCIe version of ASI5100 */ case 0x6100: case 0x6200: boot_load_family = HPI_ADAPTER_FAMILY_ASI(0x6200); break; default: return HPI6000_ERROR_UNHANDLED_SUBSYS_ID; } /* reset all DSPs, indicate two DSPs are present * set RST3-=1 to disconnect HAD8 to set DSP in little endian mode */ endian = 0; dw2040_reset = 0x0003000F; iowrite32(dw2040_reset, phw->dw2040_HPICSR + HPI_RESET); /* read back register to make sure PCI2040 chip is functioning * note that bits 4..15 are read-only and so should always return zero, * even though we wrote 1 to them */ hpios_delay_micro_seconds(1000); delay = ioread32(phw->dw2040_HPICSR + HPI_RESET); if (delay != dw2040_reset) { HPI_DEBUG_LOG(ERROR, "INIT_PCI2040 %x %x\n", dw2040_reset, delay); return HPI6000_ERROR_INIT_PCI2040; } /* Indicate that DSP#0,1 is a C6X */ iowrite32(0x00000003, phw->dw2040_HPICSR + HPI_DATA_WIDTH); /* set Bit30 and 29 - which will prevent Target aborts from being * issued upon HPI or GP error */ iowrite32(0x60000000, phw->dw2040_HPICSR + INTERRUPT_MASK_SET); /* isolate DSP HAD8 line from PCI2040 so that * Little endian can be set by pullup */ dw2040_reset = dw2040_reset & (~(endian << 3)); iowrite32(dw2040_reset, phw->dw2040_HPICSR + HPI_RESET); phw->ado[0].c_dsp_rev = 'B'; /* revB */ phw->ado[1].c_dsp_rev = 'B'; /* revB */ /*Take both DSPs out of reset, setting HAD8 to the correct Endian */ dw2040_reset = dw2040_reset & (~0x00000001); /* start DSP 0 */ iowrite32(dw2040_reset, phw->dw2040_HPICSR + HPI_RESET); dw2040_reset = dw2040_reset & (~0x00000002); /* start DSP 1 */ iowrite32(dw2040_reset, phw->dw2040_HPICSR + HPI_RESET); /* set HAD8 back to PCI2040, now that DSP set to little endian mode */ dw2040_reset = dw2040_reset & (~0x00000008); iowrite32(dw2040_reset, phw->dw2040_HPICSR + HPI_RESET); /*delay to allow DSP to get going */ hpios_delay_micro_seconds(100); /* loop through all DSPs, downloading DSP code */ for (dsp_index = 0; dsp_index < phw->num_dsp; dsp_index++) { struct dsp_obj *pdo = &phw->ado[dsp_index]; /* configure DSP so that we download code into the SRAM */ /* set control reg for little endian, HWOB=1 */ iowrite32(0x00010001, pdo->prHPI_control); /* test access to the HPI address register (HPIA) */ test_data = 0x00000001; for (j = 0; j < 32; j++) { iowrite32(test_data, pdo->prHPI_address); data = ioread32(pdo->prHPI_address); if (data != test_data) { HPI_DEBUG_LOG(ERROR, "INIT_DSPHPI %x %x %x\n", test_data, data, dsp_index); return HPI6000_ERROR_INIT_DSPHPI; } test_data = test_data << 1; } /* if C6713 the setup PLL to generate 225MHz from 25MHz. * Since the PLLDIV1 read is sometimes wrong, even on a C6713, * we're going to do this unconditionally */ /* PLLDIV1 should have a value of 8000 after reset */ /* if (HpiReadWord(pdo,0x01B7C118) == 0x8000) */ { /* C6713 datasheet says we cannot program PLL from HPI, * and indeed if we try to set the PLL multiply from the * HPI, the PLL does not seem to lock, * so we enable the PLL and use the default of x 7 */ /* bypass PLL */ hpi_write_word(pdo, 0x01B7C100, 0x0000); hpios_delay_micro_seconds(100); /* ** use default of PLL x7 ** */ /* EMIF = 225/3=75MHz */ hpi_write_word(pdo, 0x01B7C120, 0x8002); hpios_delay_micro_seconds(100); /* peri = 225/2 */ hpi_write_word(pdo, 0x01B7C11C, 0x8001); hpios_delay_micro_seconds(100); /* cpu = 225/1 */ hpi_write_word(pdo, 0x01B7C118, 0x8000); /* ~2ms delay */ hpios_delay_micro_seconds(2000); /* PLL not bypassed */ hpi_write_word(pdo, 0x01B7C100, 0x0001); /* ~2ms delay */ hpios_delay_micro_seconds(2000); } /* test r/w to internal DSP memory * C6711 has L2 cache mapped to 0x0 when reset * * revB - because of bug 3.0.1 last HPI read * (before HPI address issued) must be non-autoinc */ /* test each bit in the 32bit word */ for (i = 0; i < 100; i++) { test_addr = 0x00000000; test_data = 0x00000001; for (j = 0; j < 32; j++) { hpi_write_word(pdo, test_addr + i, test_data); data = hpi_read_word(pdo, test_addr + i); if (data != test_data) { HPI_DEBUG_LOG(ERROR, "DSP mem %x %x %x %x\n", test_addr + i, test_data, data, dsp_index); return HPI6000_ERROR_INIT_DSPINTMEM; } test_data = test_data << 1; } } /* memory map of ASI6200 00000000-0000FFFF 16Kx32 internal program 01800000-019FFFFF Internal peripheral 80000000-807FFFFF CE0 2Mx32 SDRAM running @ 100MHz 90000000-9000FFFF CE1 Async peripherals: EMIF config ------------ Global EMIF control 0 - 1 - 2 - 3 CLK2EN = 1 CLKOUT2 enabled 4 CLK1EN = 0 CLKOUT1 disabled 5 EKEN = 1 <--!! C6713 specific, enables ECLKOUT 6 - 7 NOHOLD = 1 external HOLD disabled 8 HOLDA = 0 HOLDA output is low 9 HOLD = 0 HOLD input is low 10 ARDY = 1 ARDY input is high 11 BUSREQ = 0 BUSREQ output is low 12,13 Reserved = 1 */ hpi_write_word(pdo, 0x01800000, 0x34A8); /* EMIF CE0 setup - 2Mx32 Sync DRAM 31..28 Wr setup 27..22 Wr strobe 21..20 Wr hold 19..16 Rd setup 15..14 - 13..8 Rd strobe 7..4 MTYPE 0011 Sync DRAM 32bits 3 Wr hold MSB 2..0 Rd hold */ hpi_write_word(pdo, 0x01800008, 0x00000030); /* EMIF SDRAM Extension 31-21 0 20 WR2RD = 0 19-18 WR2DEAC = 1 17 WR2WR = 0 16-15 R2WDQM = 2 14-12 RD2WR = 4 11-10 RD2DEAC = 1 9 RD2RD = 1 8-7 THZP = 10b 6-5 TWR = 2-1 = 01b (tWR = 10ns) 4 TRRD = 0b = 2 ECLK (tRRD = 14ns) 3-1 TRAS = 5-1 = 100b (Tras=42ns = 5 ECLK) 1 CAS latency = 3 ECLK (for Micron 2M32-7 operating at 100Mhz) */ /* need to use this else DSP code crashes */ hpi_write_word(pdo, 0x01800020, 0x001BDF29); /* EMIF SDRAM control - set up for a 2Mx32 SDRAM (512x32x4 bank) 31 - - 30 SDBSZ 1 4 bank 29..28 SDRSZ 00 11 row address pins 27..26 SDCSZ 01 8 column address pins 25 RFEN 1 refersh enabled 24 INIT 1 init SDRAM 23..20 TRCD 0001 19..16 TRP 0001 15..12 TRC 0110 11..0 - - */ /* need to use this else DSP code crashes */ hpi_write_word(pdo, 0x01800018, 0x47117000); /* EMIF SDRAM Refresh Timing */ hpi_write_word(pdo, 0x0180001C, 0x00000410); /*MIF CE1 setup - Async peripherals @100MHz bus speed, each cycle is 10ns, 31..28 Wr setup = 1 27..22 Wr strobe = 3 30ns 21..20 Wr hold = 1 19..16 Rd setup =1 15..14 Ta = 2 13..8 Rd strobe = 3 30ns 7..4 MTYPE 0010 Async 32bits 3 Wr hold MSB =0 2..0 Rd hold = 1 */ { u32 cE1 = (1L << 28) | (3L << 22) | (1L << 20) | (1L << 16) | (2L << 14) | (3L << 8) | (2L << 4) | 1L; hpi_write_word(pdo, 0x01800004, cE1); } /* delay a little to allow SDRAM and DSP to "get going" */ hpios_delay_micro_seconds(1000); /* test access to SDRAM */ { test_addr = 0x80000000; test_data = 0x00000001; /* test each bit in the 32bit word */ for (j = 0; j < 32; j++) { hpi_write_word(pdo, test_addr, test_data); data = hpi_read_word(pdo, test_addr); if (data != test_data) { HPI_DEBUG_LOG(ERROR, "DSP dram %x %x %x %x\n", test_addr, test_data, data, dsp_index); return HPI6000_ERROR_INIT_SDRAM1; } test_data = test_data << 1; } /* test every Nth address in the DRAM */ #define DRAM_SIZE_WORDS 0x200000 /*2_mx32 */ #define DRAM_INC 1024 test_addr = 0x80000000; test_data = 0x0; for (i = 0; i < DRAM_SIZE_WORDS; i = i + DRAM_INC) { hpi_write_word(pdo, test_addr + i, test_data); test_data++; } test_addr = 0x80000000; test_data = 0x0; for (i = 0; i < DRAM_SIZE_WORDS; i = i + DRAM_INC) { data = hpi_read_word(pdo, test_addr + i); if (data != test_data) { HPI_DEBUG_LOG(ERROR, "DSP dram %x %x %x %x\n", test_addr + i, test_data, data, dsp_index); return HPI6000_ERROR_INIT_SDRAM2; } test_data++; } } /* write the DSP code down into the DSPs memory */ error = hpi_dsp_code_open(boot_load_family, pao->pci.pci_dev, &dsp_code, pos_error_code); if (error) return error; while (1) { u32 length; u32 address; u32 type; u32 *pcode; error = hpi_dsp_code_read_word(&dsp_code, &length); if (error) break; if (length == 0xFFFFFFFF) break; /* end of code */ error = hpi_dsp_code_read_word(&dsp_code, &address); if (error) break; error = hpi_dsp_code_read_word(&dsp_code, &type); if (error) break; error = hpi_dsp_code_read_block(length, &dsp_code, &pcode); if (error) break; error = hpi6000_dsp_block_write32(pao, (u16)dsp_index, address, pcode, length); if (error) break; } if (error) { hpi_dsp_code_close(&dsp_code); return error; } /* verify that code was written correctly */ /* this time through, assume no errors in DSP code file/array */ hpi_dsp_code_rewind(&dsp_code); while (1) { u32 length; u32 address; u32 type; u32 *pcode; hpi_dsp_code_read_word(&dsp_code, &length); if (length == 0xFFFFFFFF) break; /* end of code */ hpi_dsp_code_read_word(&dsp_code, &address); hpi_dsp_code_read_word(&dsp_code, &type); hpi_dsp_code_read_block(length, &dsp_code, &pcode); for (i = 0; i < length; i++) { data = hpi_read_word(pdo, address); if (data != *pcode) { error = HPI6000_ERROR_INIT_VERIFY; HPI_DEBUG_LOG(ERROR, "DSP verify %x %x %x %x\n", address, *pcode, data, dsp_index); break; } pcode++; address += 4; } if (error) break; } hpi_dsp_code_close(&dsp_code); if (error) return error; /* zero out the hostmailbox */ { u32 address = HPI_HIF_ADDR(host_cmd); for (i = 0; i < 4; i++) { hpi_write_word(pdo, address, 0); address += 4; } } /* write the DSP number into the hostmailbox */ /* structure before starting the DSP */ hpi_write_word(pdo, HPI_HIF_ADDR(dsp_number), dsp_index); /* write the DSP adapter Info into the */ /* hostmailbox before starting the DSP */ if (dsp_index > 0) hpi_write_word(pdo, HPI_HIF_ADDR(adapter_info), adapter_info); /* step 3. Start code by sending interrupt */ iowrite32(0x00030003, pdo->prHPI_control); hpios_delay_micro_seconds(10000); /* wait for a non-zero value in hostcmd - * indicating initialization is complete * * Init could take a while if DSP checks SDRAM memory * Was 200000. Increased to 2000000 for ASI8801 so we * don't get 938 errors. */ timeout = 2000000; while (timeout) { do { read = hpi_read_word(pdo, HPI_HIF_ADDR(host_cmd)); } while (--timeout && hpi6000_check_PCI2040_error_flag(pao, H6READ)); if (read) break; /* The following is a workaround for bug #94: * Bluescreen on install and subsequent boots on a * DELL PowerEdge 600SC PC with 1.8GHz P4 and * ServerWorks chipset. Without this delay the system * locks up with a bluescreen (NOT GPF or pagefault). */ else hpios_delay_micro_seconds(10000); } if (timeout == 0) return HPI6000_ERROR_INIT_NOACK; /* read the DSP adapter Info from the */ /* hostmailbox structure after starting the DSP */ if (dsp_index == 0) { /*u32 dwTestData=0; */ u32 mask = 0; adapter_info = hpi_read_word(pdo, HPI_HIF_ADDR(adapter_info)); if (HPI_ADAPTER_FAMILY_ASI (HPI_HIF_ADAPTER_INFO_EXTRACT_ADAPTER (adapter_info)) == HPI_ADAPTER_FAMILY_ASI(0x6200)) /* all 6200 cards have this many DSPs */ phw->num_dsp = 2; /* test that the PLD is programmed */ /* and we can read/write 24bits */ #define PLD_BASE_ADDRESS 0x90000000L /*for ASI6100/6200/8800 */ switch (boot_load_family) { case HPI_ADAPTER_FAMILY_ASI(0x6200): /* ASI6100/6200 has 24bit path to FPGA */ mask = 0xFFFFFF00L; /* ASI5100 uses AX6 code, */ /* but has no PLD r/w register to test */ if (HPI_ADAPTER_FAMILY_ASI(pao->pci.pci_dev-> subsystem_device) == HPI_ADAPTER_FAMILY_ASI(0x5100)) mask = 0x00000000L; /* ASI5200 uses AX6 code, */ /* but has no PLD r/w register to test */ if (HPI_ADAPTER_FAMILY_ASI(pao->pci.pci_dev-> subsystem_device) == HPI_ADAPTER_FAMILY_ASI(0x5200)) mask = 0x00000000L; break; case HPI_ADAPTER_FAMILY_ASI(0x8800): /* ASI8800 has 16bit path to FPGA */ mask = 0xFFFF0000L; break; } test_data = 0xAAAAAA00L & mask; /* write to 24 bit Debug register (D31-D8) */ hpi_write_word(pdo, PLD_BASE_ADDRESS + 4L, test_data); read = hpi_read_word(pdo, PLD_BASE_ADDRESS + 4L) & mask; if (read != test_data) { HPI_DEBUG_LOG(ERROR, "PLD %x %x\n", test_data, read); return HPI6000_ERROR_INIT_PLDTEST1; } test_data = 0x55555500L & mask; hpi_write_word(pdo, PLD_BASE_ADDRESS + 4L, test_data); read = hpi_read_word(pdo, PLD_BASE_ADDRESS + 4L) & mask; if (read != test_data) { HPI_DEBUG_LOG(ERROR, "PLD %x %x\n", test_data, read); return HPI6000_ERROR_INIT_PLDTEST2; } } } /* for numDSP */ return 0; }
/* this routine is called from SubSysFindAdapter and SubSysCreateAdapter */ static short create_adapter_obj(struct hpi_adapter_obj *pao, u32 *pos_error_code) { short boot_error = 0; u32 dsp_index = 0; u32 control_cache_size = 0; u32 control_cache_count = 0; struct hpi_hw_obj *phw = pao->priv; /* The PCI2040 has the following address map */ /* BAR0 - 4K = HPI control and status registers on PCI2040 (HPI CSR) */ /* BAR1 - 32K = HPI registers on DSP */ phw->dw2040_HPICSR = pao->pci.ap_mem_base[0]; phw->dw2040_HPIDSP = pao->pci.ap_mem_base[1]; HPI_DEBUG_LOG(VERBOSE, "csr %p, dsp %p\n", phw->dw2040_HPICSR, phw->dw2040_HPIDSP); /* set addresses for the possible DSP HPI interfaces */ for (dsp_index = 0; dsp_index < MAX_DSPS; dsp_index++) { phw->ado[dsp_index].prHPI_control = phw->dw2040_HPIDSP + (CONTROL + DSP_SPACING * dsp_index); phw->ado[dsp_index].prHPI_address = phw->dw2040_HPIDSP + (ADDRESS + DSP_SPACING * dsp_index); phw->ado[dsp_index].prHPI_data = phw->dw2040_HPIDSP + (DATA + DSP_SPACING * dsp_index); phw->ado[dsp_index].prHPI_data_auto_inc = phw->dw2040_HPIDSP + (DATA_AUTOINC + DSP_SPACING * dsp_index); HPI_DEBUG_LOG(VERBOSE, "ctl %p, adr %p, dat %p, dat++ %p\n", phw->ado[dsp_index].prHPI_control, phw->ado[dsp_index].prHPI_address, phw->ado[dsp_index].prHPI_data, phw->ado[dsp_index].prHPI_data_auto_inc); phw->ado[dsp_index].pa_parent_adapter = pao; } phw->pCI2040HPI_error_count = 0; pao->has_control_cache = 0; /* Set the default number of DSPs on this card */ /* This is (conditionally) adjusted after bootloading */ /* of the first DSP in the bootload section. */ phw->num_dsp = 1; boot_error = hpi6000_adapter_boot_load_dsp(pao, pos_error_code); if (boot_error) return boot_error; HPI_DEBUG_LOG(INFO, "bootload DSP OK\n"); phw->message_buffer_address_on_dsp = 0L; phw->response_buffer_address_on_dsp = 0L; /* get info about the adapter by asking the adapter */ /* send a HPI_ADAPTER_GET_INFO message */ { struct hpi_message hm; struct hpi_response hr0; /* response from DSP 0 */ struct hpi_response hr1; /* response from DSP 1 */ u16 error = 0; HPI_DEBUG_LOG(VERBOSE, "send ADAPTER_GET_INFO\n"); memset(&hm, 0, sizeof(hm)); hm.type = HPI_TYPE_REQUEST; hm.size = sizeof(struct hpi_message); hm.object = HPI_OBJ_ADAPTER; hm.function = HPI_ADAPTER_GET_INFO; hm.adapter_index = 0; memset(&hr0, 0, sizeof(hr0)); memset(&hr1, 0, sizeof(hr1)); hr0.size = sizeof(hr0); hr1.size = sizeof(hr1); error = hpi6000_message_response_sequence(pao, 0, &hm, &hr0); if (hr0.error) { HPI_DEBUG_LOG(DEBUG, "message error %d\n", hr0.error); return hr0.error; } if (phw->num_dsp == 2) { error = hpi6000_message_response_sequence(pao, 1, &hm, &hr1); if (error) return error; } pao->type = hr0.u.ax.info.adapter_type; pao->index = hr0.u.ax.info.adapter_index; } memset(&phw->control_cache[0], 0, sizeof(struct hpi_control_cache_single) * HPI_NMIXER_CONTROLS); /* Read the control cache length to figure out if it is turned on */ control_cache_size = hpi_read_word(&phw->ado[0], HPI_HIF_ADDR(control_cache_size_in_bytes)); if (control_cache_size) { control_cache_count = hpi_read_word(&phw->ado[0], HPI_HIF_ADDR(control_cache_count)); phw->p_cache = hpi_alloc_control_cache(control_cache_count, control_cache_size, (unsigned char *) &phw->control_cache[0] ); if (phw->p_cache) pao->has_control_cache = 1; } HPI_DEBUG_LOG(DEBUG, "get adapter info ASI%04X index %d\n", pao->type, pao->index); if (phw->p_cache) phw->p_cache->adap_idx = pao->index; return hpi_add_adapter(pao); }
static short hpi6000_update_control_cache(struct hpi_adapter_obj *pao, struct hpi_message *phm) { const u16 dsp_index = 0; struct hpi_hw_obj *phw = pao->priv; struct dsp_obj *pdo = &phw->ado[dsp_index]; u32 timeout; u32 cache_dirty_flag; u16 err; hpios_dsplock_lock(pao); timeout = TIMEOUT; do { cache_dirty_flag = hpi_read_word((struct dsp_obj *)pdo, HPI_HIF_ADDR(control_cache_is_dirty)); } while (hpi6000_check_PCI2040_error_flag(pao, H6READ) && --timeout); if (!timeout) { err = HPI6000_ERROR_CONTROL_CACHE_PARAMS; goto unlock; } if (cache_dirty_flag) { /* read the cached controls */ u32 address; u32 length; timeout = TIMEOUT; if (pdo->control_cache_address_on_dsp == 0) { do { address = hpi_read_word((struct dsp_obj *)pdo, HPI_HIF_ADDR(control_cache_address)); length = hpi_read_word((struct dsp_obj *)pdo, HPI_HIF_ADDR (control_cache_size_in_bytes)); } while (hpi6000_check_PCI2040_error_flag(pao, H6READ) && --timeout); if (!timeout) { err = HPI6000_ERROR_CONTROL_CACHE_ADDRLEN; goto unlock; } pdo->control_cache_address_on_dsp = address; pdo->control_cache_length_on_dsp = length; } else { address = pdo->control_cache_address_on_dsp; length = pdo->control_cache_length_on_dsp; } if (hpi6000_dsp_block_read32(pao, dsp_index, address, (u32 *)&phw->control_cache[0], length / sizeof(u32))) { err = HPI6000_ERROR_CONTROL_CACHE_READ; goto unlock; } do { hpi_write_word((struct dsp_obj *)pdo, HPI_HIF_ADDR(control_cache_is_dirty), 0); /* flush the FIFO */ hpi_set_address(pdo, HPI_HIF_ADDR(host_cmd)); } while (hpi6000_check_PCI2040_error_flag(pao, H6WRITE) && --timeout); if (!timeout) { err = HPI6000_ERROR_CONTROL_CACHE_FLUSH; goto unlock; } } err = 0; unlock: hpios_dsplock_unlock(pao); return err; }
static short hpi6000_send_data(struct hpi_adapter_obj *pao, u16 dsp_index, struct hpi_message *phm, struct hpi_response *phr) { struct hpi_hw_obj *phw = pao->priv; struct dsp_obj *pdo = &phw->ado[dsp_index]; u32 data_sent = 0; u16 ack; u32 length, address; u32 *p_data = (u32 *)phm->u.d.u.data.pb_data; u16 time_out = 8; (void)phr; /* round dwDataSize down to nearest 4 bytes */ while ((data_sent < (phm->u.d.u.data.data_size & ~3L)) && --time_out) { ack = hpi6000_wait_dsp_ack(pao, dsp_index, HPI_HIF_IDLE); if (ack & HPI_HIF_ERROR_MASK) return HPI6000_ERROR_SEND_DATA_IDLE_TIMEOUT; if (hpi6000_send_host_command(pao, dsp_index, HPI_HIF_SEND_DATA)) return HPI6000_ERROR_SEND_DATA_CMD; hpi6000_send_dsp_interrupt(pdo); ack = hpi6000_wait_dsp_ack(pao, dsp_index, HPI_HIF_SEND_DATA); if (ack & HPI_HIF_ERROR_MASK) return HPI6000_ERROR_SEND_DATA_ACK; do { /* get the address and size */ address = hpi_read_word(pdo, HPI_HIF_ADDR(address)); /* DSP returns number of DWORDS */ length = hpi_read_word(pdo, HPI_HIF_ADDR(length)); } while (hpi6000_check_PCI2040_error_flag(pao, H6READ)); if (!hpi6000_send_data_check_adr(address, length)) return HPI6000_ERROR_SEND_DATA_ADR; /* send the data. break data into 512 DWORD blocks (2K bytes) * and send using block write. 2Kbytes is the max as this is the * memory window given to the HPI data register by the PCI2040 */ { u32 len = length; u32 blk_len = 512; while (len) { if (len < blk_len) blk_len = len; if (hpi6000_dsp_block_write32(pao, dsp_index, address, p_data, blk_len)) return HPI6000_ERROR_SEND_DATA_WRITE; address += blk_len * 4; p_data += blk_len; len -= blk_len; } } if (hpi6000_send_host_command(pao, dsp_index, HPI_HIF_IDLE)) return HPI6000_ERROR_SEND_DATA_IDLECMD; hpi6000_send_dsp_interrupt(pdo); data_sent += length * 4; } if (!time_out) return HPI6000_ERROR_SEND_DATA_TIMEOUT; return 0; }
static short hpi6000_message_response_sequence(struct hpi_adapter_obj *pao, u16 dsp_index, struct hpi_message *phm, struct hpi_response *phr) { struct hpi_hw_obj *phw = pao->priv; struct dsp_obj *pdo = &phw->ado[dsp_index]; u32 timeout; u16 ack; u32 address; u32 length; u32 *p_data; u16 error = 0; ack = hpi6000_wait_dsp_ack(pao, dsp_index, HPI_HIF_IDLE); if (ack & HPI_HIF_ERROR_MASK) { pao->dsp_crashed++; return HPI6000_ERROR_MSG_RESP_IDLE_TIMEOUT; } pao->dsp_crashed = 0; /* get the message address and size */ if (phw->message_buffer_address_on_dsp == 0) { timeout = TIMEOUT; do { address = hpi_read_word(pdo, HPI_HIF_ADDR(message_buffer_address)); phw->message_buffer_address_on_dsp = address; } while (hpi6000_check_PCI2040_error_flag(pao, H6READ) && --timeout); if (!timeout) return HPI6000_ERROR_MSG_GET_ADR; } else address = phw->message_buffer_address_on_dsp; length = phm->size; /* send the message */ p_data = (u32 *)phm; if (hpi6000_dsp_block_write32(pao, dsp_index, address, p_data, (u16)length / 4)) return HPI6000_ERROR_MSG_RESP_BLOCKWRITE32; if (hpi6000_send_host_command(pao, dsp_index, HPI_HIF_GET_RESP)) return HPI6000_ERROR_MSG_RESP_GETRESPCMD; hpi6000_send_dsp_interrupt(pdo); ack = hpi6000_wait_dsp_ack(pao, dsp_index, HPI_HIF_GET_RESP); if (ack & HPI_HIF_ERROR_MASK) return HPI6000_ERROR_MSG_RESP_GET_RESP_ACK; /* get the response address */ if (phw->response_buffer_address_on_dsp == 0) { timeout = TIMEOUT; do { address = hpi_read_word(pdo, HPI_HIF_ADDR(response_buffer_address)); } while (hpi6000_check_PCI2040_error_flag(pao, H6READ) && --timeout); phw->response_buffer_address_on_dsp = address; if (!timeout) return HPI6000_ERROR_RESP_GET_ADR; } else address = phw->response_buffer_address_on_dsp; /* read the length of the response back from the DSP */ timeout = TIMEOUT; do { length = hpi_read_word(pdo, HPI_HIF_ADDR(length)); } while (hpi6000_check_PCI2040_error_flag(pao, H6READ) && --timeout); if (!timeout) return HPI6000_ERROR_RESP_GET_LEN; if (length > phr->size) return HPI_ERROR_RESPONSE_BUFFER_TOO_SMALL; /* get the response */ p_data = (u32 *)phr; if (hpi6000_dsp_block_read32(pao, dsp_index, address, p_data, (u16)length / 4)) return HPI6000_ERROR_MSG_RESP_BLOCKREAD32; /* set i/f back to idle */ if (hpi6000_send_host_command(pao, dsp_index, HPI_HIF_IDLE)) return HPI6000_ERROR_MSG_RESP_IDLECMD; hpi6000_send_dsp_interrupt(pdo); error = hpi_validate_response(phm, phr); return error; }
/* this routine is called from SubSysFindAdapter and SubSysCreateAdapter */ static short CreateAdapterObj( struct hpi_adapter_obj *pao, u32 *pdwOsErrorCode ) { short nBootError = 0; u32 dwDspIndex = 0; u32 dwControlCacheSize = 0; u32 dwControlCacheCount = 0; struct hpi_hw_obj *phw = (struct hpi_hw_obj *)pao->priv; /* init error reporting */ pao->wDspCrashed = 0; /* The PCI2040 has the following address map */ /* BAR0 - 4K = HPI control and status registers on PCI2040 (HPI CSR) */ /* BAR1 - 32K = HPI registers on DSP */ phw->dw2040_HPICSR = pao->Pci.apMemBase[0]; phw->dw2040_HPIDSP = pao->Pci.apMemBase[1]; HPI_DEBUG_LOG(VERBOSE, "csr %p, dsp %p\n", phw->dw2040_HPICSR, phw->dw2040_HPIDSP); /* set addresses for the possible DSP HPI interfaces */ for (dwDspIndex = 0; dwDspIndex < MAX_DSPS; dwDspIndex++) { phw->ado[dwDspIndex].prHPIControl = phw->dw2040_HPIDSP + (CONTROL + DSP_SPACING * dwDspIndex); phw->ado[dwDspIndex].prHPIAddress = phw->dw2040_HPIDSP + (ADDRESS + DSP_SPACING * dwDspIndex); phw->ado[dwDspIndex].prHPIData = phw->dw2040_HPIDSP + (DATA + DSP_SPACING * dwDspIndex); phw->ado[dwDspIndex].prHPIDataAutoInc = phw->dw2040_HPIDSP + (DATA_AUTOINC + DSP_SPACING * dwDspIndex); HPI_DEBUG_LOG(VERBOSE, "ctl %p, adr %p, dat %p, dat++ %p\n", phw->ado[dwDspIndex].prHPIControl, phw->ado[dwDspIndex].prHPIAddress, phw->ado[dwDspIndex].prHPIData, phw->ado[dwDspIndex].prHPIDataAutoInc); phw->ado[dwDspIndex].paParentAdapter = pao; } phw->dwPCI2040HPIErrorCount = 0; pao->wHasControlCache = 0; /* Set the default number of DSPs on this card */ /* This is (conditionally) adjusted after bootloading */ /* of the first DSP in the bootload section. */ phw->wNumDsp = 1; nBootError = Hpi6000_AdapterBootLoadDsp(pao, pdwOsErrorCode); if (nBootError) return (nBootError); HPI_DEBUG_LOG(INFO, "Bootload DSP OK\n"); phw->dwMessageBufferAddressOnDSP = 0L; phw->dwResponseBufferAddressOnDSP = 0L; /* get info about the adapter by asking the adapter */ /* send a HPI_ADAPTER_GET_INFO message */ { struct hpi_message hM; struct hpi_response hR0; /* response from DSP 0 */ struct hpi_response hR1; /* response from DSP 1 */ u16 wError = 0; HPI_DEBUG_LOG(VERBOSE, "send ADAPTER_GET_INFO\n"); memset(&hM, 0, sizeof(hM)); hM.wType = HPI_TYPE_MESSAGE; hM.wSize = sizeof(struct hpi_message); hM.wObject = HPI_OBJ_ADAPTER; hM.wFunction = HPI_ADAPTER_GET_INFO; hM.wAdapterIndex = 0; hM.wDspIndex = 0; memset(&hR0, 0, sizeof(hR0)); memset(&hR1, 0, sizeof(hR1)); hR0.wSize = sizeof(hR0); hR1.wSize = sizeof(hR1); wError = Hpi6000_MessageResponseSequence(pao, &hM, &hR0); if (hR0.wError) { HPI_DEBUG_LOG(DEBUG, "message error %d\n", hR0.wError); return (hR0.wError); /*error */ } if (phw->wNumDsp == 2) { hM.wDspIndex = 1; wError = Hpi6000_MessageResponseSequence(pao, &hM, &hR1); if (wError) return wError; } pao->wAdapterType = hR0.u.a.wAdapterType; pao->wIndex = hR0.u.a.wAdapterIndex; } memset(&phw->aControlCache[0], 0, sizeof(struct hpi_control_cache_single) * HPI_NMIXER_CONTROLS); /* Read the control cache length to figure out if it is turned on */ dwControlCacheSize = HpiReadWord(&phw->ado[0], HPI_HIF_ADDR(dwControlCacheSizeInBytes)); if (dwControlCacheSize) { dwControlCacheCount = HpiReadWord(&phw->ado[0], HPI_HIF_ADDR(dwControlCacheCount)); pao->wHasControlCache = 1; phw->pCache = HpiAllocControlCache(dwControlCacheCount, dwControlCacheSize, (struct hpi_control_cache_info *) &phw->aControlCache[0] ); } else pao->wHasControlCache = 0; HPI_DEBUG_LOG(DEBUG, "Get adapter info ASI%04X index %d\n", pao->wAdapterType, pao->wIndex); pao->wOpen = 0; /* upon creation the adapter is closed */ return 0; }
static short Hpi6000_UpdateControlCache( struct hpi_adapter_obj *pao, struct hpi_message *phm ) { const u16 wDspIndex = phm->wDspIndex; struct hpi_hw_obj *phw = (struct hpi_hw_obj *)pao->priv; struct dsp_obj *pdo = &phw->ado[wDspIndex]; u32 dwTimeout; u32 dwCacheDirtyFlag; u16 err; HpiOs_Dsplock_Lock(pao); dwTimeout = TIMEOUT; do { dwCacheDirtyFlag = HpiReadWord((struct dsp_obj *)pdo, HPI_HIF_ADDR(dwControlCacheIsDirty)); } while (Hpi6000_Check_PCI2040_ErrorFlag(pao, H6READ) && --dwTimeout); if (!dwTimeout) { err = HPI6000_ERROR_CONTROL_CACHE_PARAMS; goto unlock; } if (dwCacheDirtyFlag) { /* read the cached controls */ u32 dwAddress; u32 dwLength; dwTimeout = TIMEOUT; if (pdo->dwControlCacheAddressOnDSP == 0) { do { dwAddress = HpiReadWord((struct dsp_obj *)pdo, HPI_HIF_ADDR(dwControlCacheAddress)); dwLength = HpiReadWord((struct dsp_obj *)pdo, HPI_HIF_ADDR (dwControlCacheSizeInBytes)); } while (Hpi6000_Check_PCI2040_ErrorFlag(pao, H6READ) && --dwTimeout); if (!dwTimeout) { err = HPI6000_ERROR_CONTROL_CACHE_ADDRLEN; goto unlock; } pdo->dwControlCacheAddressOnDSP = dwAddress; pdo->dwControlCacheLengthOnDSP = dwLength; } else { dwAddress = pdo->dwControlCacheAddressOnDSP; dwLength = pdo->dwControlCacheLengthOnDSP; } if (Hpi6000_DspBlockRead32(pao, wDspIndex, dwAddress, (u32 *)&phw->aControlCache[0], dwLength / sizeof(u32))) { err = HPI6000_ERROR_CONTROL_CACHE_READ; goto unlock; } do { HpiWriteWord((struct dsp_obj *)pdo, HPI_HIF_ADDR(dwControlCacheIsDirty), 0); /* flush the FIFO */ HpiSetAddress(pdo, HPI_HIF_ADDR(dwHostCmd)); } while (Hpi6000_Check_PCI2040_ErrorFlag(pao, H6WRITE) && --dwTimeout); if (!dwTimeout) { err = HPI6000_ERROR_CONTROL_CACHE_FLUSH; goto unlock; } } err = 0; unlock: HpiOs_Dsplock_UnLock(pao); return err; }
static short Hpi6000_GetData( struct hpi_adapter_obj *pao, struct hpi_message *phm, struct hpi_response *phr ) { u16 wDspIndex = phm->wDspIndex; struct dsp_obj *pdo = &(*(struct hpi_hw_obj *)pao->priv).ado[wDspIndex]; u32 dwDataGot = 0; u16 wAck; u32 dwLength, dwAddress; u32 *pData = (u32 *)phm->u.d.u.Data.pbData; (void)phr; /* this parameter not used! */ /* round dwDataSize down to nearest 4 bytes */ while (dwDataGot < (phm->u.d.u.Data.dwDataSize & ~3L)) { wAck = Hpi6000_WaitDspAck(pao, wDspIndex, HPI_HIF_IDLE); if (wAck & HPI_HIF_ERROR_MASK) return HPI6000_ERROR_GET_DATA_IDLE_TIMEOUT; if (Hpi6000_SendHostCommand(pao, wDspIndex, HPI_HIF_GET_DATA)) return HPI6000_ERROR_GET_DATA_CMD; Hpi6000_SendDspInterrupt(pdo); wAck = Hpi6000_WaitDspAck(pao, wDspIndex, HPI_HIF_GET_DATA); if (wAck & HPI_HIF_ERROR_MASK) return HPI6000_ERROR_GET_DATA_ACK; /* get the address and size */ do { dwAddress = HpiReadWord(pdo, HPI_HIF_ADDR(dwAddress)); dwLength = HpiReadWord(pdo, HPI_HIF_ADDR(dwLength)); } while (Hpi6000_Check_PCI2040_ErrorFlag(pao, H6READ)); /* read the data */ { u32 dwLen = dwLength; u32 dwBlkLen = 512; while (dwLen) { if (dwLen < dwBlkLen) dwBlkLen = dwLen; if (Hpi6000_DspBlockRead32(pao, wDspIndex, dwAddress, pData, dwBlkLen)) return HPI6000_ERROR_GET_DATA_READ; dwAddress += dwBlkLen * 4; pData += dwBlkLen; dwLen -= dwBlkLen; } } if (Hpi6000_SendHostCommand(pao, wDspIndex, HPI_HIF_IDLE)) return HPI6000_ERROR_GET_DATA_IDLECMD; Hpi6000_SendDspInterrupt(pdo); dwDataGot += dwLength * 4; } return 0; }
static short Hpi6000_SendData( struct hpi_adapter_obj *pao, struct hpi_message *phm, struct hpi_response *phr ) { u16 wDspIndex = phm->wDspIndex; struct dsp_obj *pdo = &(*(struct hpi_hw_obj *)pao->priv).ado[wDspIndex]; u32 dwDataSent = 0; u16 wAck; u32 dwLength, dwAddress; u32 *pData = (u32 *)phm->u.d.u.Data.pbData; u16 wTimeOut = 8; (void)phr; /* round dwDataSize down to nearest 4 bytes */ while ((dwDataSent < (phm->u.d.u.Data.dwDataSize & ~3L)) && --wTimeOut) { wAck = Hpi6000_WaitDspAck(pao, wDspIndex, HPI_HIF_IDLE); if (wAck & HPI_HIF_ERROR_MASK) return HPI6000_ERROR_SEND_DATA_IDLE_TIMEOUT; if (Hpi6000_SendHostCommand (pao, wDspIndex, HPI_HIF_SEND_DATA)) return HPI6000_ERROR_SEND_DATA_CMD; Hpi6000_SendDspInterrupt(pdo); wAck = Hpi6000_WaitDspAck(pao, wDspIndex, HPI_HIF_SEND_DATA); if (wAck & HPI_HIF_ERROR_MASK) return HPI6000_ERROR_SEND_DATA_ACK; do { /* get the address and size */ dwAddress = HpiReadWord(pdo, HPI_HIF_ADDR(dwAddress)); /* DSP returns number of DWORDS */ dwLength = HpiReadWord(pdo, HPI_HIF_ADDR(dwLength)); } while (Hpi6000_Check_PCI2040_ErrorFlag(pao, H6READ)); if (!Hpi6000_SendData_CheckAdr(dwAddress, dwLength)) return HPI6000_ERROR_SEND_DATA_ADR; /* send the data. break data into 512 DWORD blocks (2K bytes) * and send using block write. 2Kbytes is the max as this is the * memory window given to the HPI data register by the PCI2040 */ { u32 dwLen = dwLength; u32 dwBlkLen = 512; while (dwLen) { if (dwLen < dwBlkLen) dwBlkLen = dwLen; if (Hpi6000_DspBlockWrite32(pao, wDspIndex, dwAddress, pData, dwBlkLen)) return HPI6000_ERROR_SEND_DATA_WRITE; dwAddress += dwBlkLen * 4; pData += dwBlkLen; dwLen -= dwBlkLen; } } if (Hpi6000_SendHostCommand(pao, wDspIndex, HPI_HIF_IDLE)) return HPI6000_ERROR_SEND_DATA_IDLECMD; Hpi6000_SendDspInterrupt(pdo); dwDataSent += dwLength * 4; } if (!wTimeOut) return HPI6000_ERROR_SEND_DATA_TIMEOUT; return 0; }
static short Hpi6000_MessageResponseSequence( struct hpi_adapter_obj *pao, struct hpi_message *phm, struct hpi_response *phr ) { u16 wDspIndex = phm->wDspIndex; struct hpi_hw_obj *phw = (struct hpi_hw_obj *)pao->priv; struct dsp_obj *pdo = &phw->ado[wDspIndex]; u32 dwTimeout; u16 wAck; u32 dwAddress; u32 dwLength; u32 *pData; u16 wError = 0; /* does the DSP we are referencing exist? */ if (wDspIndex >= phw->wNumDsp) return HPI6000_ERROR_MSG_INVALID_DSP_INDEX; wAck = Hpi6000_WaitDspAck(pao, wDspIndex, HPI_HIF_IDLE); if (wAck & HPI_HIF_ERROR_MASK) { pao->wDspCrashed++; return HPI6000_ERROR_MSG_RESP_IDLE_TIMEOUT; } pao->wDspCrashed = 0; /* send the message */ /* get the address and size */ if (phw->dwMessageBufferAddressOnDSP == 0) { dwTimeout = TIMEOUT; do { dwAddress = HpiReadWord(pdo, HPI_HIF_ADDR(dwMessageBufferAddress)); phw->dwMessageBufferAddressOnDSP = dwAddress; } while (Hpi6000_Check_PCI2040_ErrorFlag(pao, H6READ) && --dwTimeout); if (!dwTimeout) return HPI6000_ERROR_MSG_GET_ADR; } else dwAddress = phw->dwMessageBufferAddressOnDSP; /* dwLength = sizeof(struct hpi_message); */ dwLength = phm->wSize; /* send it */ pData = (u32 *)phm; if (Hpi6000_DspBlockWrite32(pao, wDspIndex, dwAddress, pData, (u16)dwLength / 4)) return HPI6000_ERROR_MSG_RESP_BLOCKWRITE32; if (Hpi6000_SendHostCommand(pao, wDspIndex, HPI_HIF_GET_RESP)) return HPI6000_ERROR_MSG_RESP_GETRESPCMD; Hpi6000_SendDspInterrupt(pdo); wAck = Hpi6000_WaitDspAck(pao, wDspIndex, HPI_HIF_GET_RESP); if (wAck & HPI_HIF_ERROR_MASK) return HPI6000_ERROR_MSG_RESP_GET_RESP_ACK; /* get the address and size */ if (phw->dwResponseBufferAddressOnDSP == 0) { dwTimeout = TIMEOUT; do { dwAddress = HpiReadWord(pdo, HPI_HIF_ADDR(dwResponseBufferAddress)); } while (Hpi6000_Check_PCI2040_ErrorFlag(pao, H6READ) && --dwTimeout); phw->dwResponseBufferAddressOnDSP = dwAddress; if (!dwTimeout) return HPI6000_ERROR_RESP_GET_ADR; } else dwAddress = phw->dwResponseBufferAddressOnDSP; /* read the length of the response back from the DSP */ dwTimeout = TIMEOUT; do { dwLength = HpiReadWord(pdo, HPI_HIF_ADDR(dwLength)); } while (Hpi6000_Check_PCI2040_ErrorFlag(pao, H6READ) && --dwTimeout); if (!dwTimeout) dwLength = sizeof(struct hpi_response); /* get it */ pData = (u32 *)phr; if (Hpi6000_DspBlockRead32 (pao, wDspIndex, dwAddress, pData, (u16)dwLength / 4)) return HPI6000_ERROR_MSG_RESP_BLOCKREAD32; /* set i/f back to idle */ if (Hpi6000_SendHostCommand(pao, wDspIndex, HPI_HIF_IDLE)) return HPI6000_ERROR_MSG_RESP_IDLECMD; Hpi6000_SendDspInterrupt(pdo); wError = HpiValidateResponse(phm, phr); return wError; }