{ UDATA (NULL, UNIT_FIX + UNIT_ATTABLE + UNIT_DISABLE + UNIT_ROABLE, DISK3_CAPACITY) },
{ UDATA (NULL, UNIT_FIX + UNIT_ATTABLE + UNIT_DISABLE + UNIT_ROABLE, DISK3_CAPACITY) },
{ UDATA (NULL, UNIT_FIX + UNIT_ATTABLE + UNIT_DISABLE + UNIT_ROABLE, DISK3_CAPACITY) },
{ UDATA (NULL, UNIT_FIX + UNIT_ATTABLE + UNIT_DISABLE + UNIT_ROABLE, DISK3_CAPACITY) }
};
static REG disk3_reg[] = {
{ DRDATAD (NTRACKS, ntracks, 10,
"Number of tracks"), },
{ DRDATAD (NHEADS, nheads, 8,
"Number of heads"), },
{ DRDATAD (NSECTORS, nsectors, 8,
"Number of sectors per track"), },
{ DRDATAD (SECTSIZE, sectsize, 11,
"Sector size not including pre/postamble"), },
{ HRDATAD (SEL_DRIVE, disk3_info_data.sel_drive, 3,
"Currently selected drive"), },
{ HRDATAD (MODE, disk3_info_data.mode, 8,
"Mode (0xFF=absolute, 0x00=logical)"), },
{ HRDATAD (RETRIES, disk3_info_data.retries, 8,
"Number of retries to attempt"), },
{ HRDATAD (NDRIVES, disk3_info_data.ndrives, 8,
"Number of drives attached to the controller"), },
{ HRDATAD (LINK_ADDR, disk3_info_data.link_addr, 32,
"Link address for next IOPB"), },
{ HRDATAD (DMA_ADDR, disk3_info_data.dma_addr, 32,
"DMA address for the current IOPB"), },
{ BRDATAD (IOPB, &disk3_info_data.iopb[DISK3_IOPB_CMD], 16, 8, 16,
"IOPB command register"), } ,
{ NULL }
};
/* The ADCS6 does not really have RAM associated with it, but for ease of integration with the
* SIMH/AltairZ80 Resource Mapping Scheme, rather than Map and Unmap the ROM, simply implement our
* own RAM that can be swapped in when the ADCS6 Boot ROM is disabled.
*/
static uint8 adcs6ram[ADCS6_ROM_SIZE];
static UNIT adcs6_unit[] = {
{ UDATA (&adcs6_svc, UNIT_FIX + UNIT_ATTABLE + UNIT_DISABLE + UNIT_ROABLE + UNIT_ADCS6_ROM, ADCS6_CAPACITY), 1024 },
{ UDATA (&adcs6_svc, UNIT_FIX + UNIT_ATTABLE + UNIT_DISABLE + UNIT_ROABLE, ADCS6_CAPACITY) },
{ UDATA (&adcs6_svc, UNIT_FIX + UNIT_ATTABLE + UNIT_DISABLE + UNIT_ROABLE, ADCS6_CAPACITY) },
{ UDATA (&adcs6_svc, UNIT_FIX + UNIT_ATTABLE + UNIT_DISABLE + UNIT_ROABLE, ADCS6_CAPACITY) }
};
static REG adcs6_reg[] = {
{ HRDATAD (J7, dipswitch, 8, "5-position DIP switch on 64FDC card"), },
{ NULL }
};
#define ADCS6_NAME "ADC Super-Six ADCS6"
static MTAB adcs6_mod[] = {
{ MTAB_XTD|MTAB_VDV, 0, "MEMBASE", "MEMBASE",
&set_membase, &show_membase, NULL, "Sets disk controller memory base address" },
{ MTAB_XTD|MTAB_VDV, 0, "IOBASE", "IOBASE",
&set_iobase, &show_iobase, NULL, "Sets disk controller I/O base address" },
/* quiet, no warning messages */
{ UNIT_ADCS6_ROM, 0, "NOROM", "NOROM",
NULL, NULL, NULL, "Disables boot ROM for unit " ADCS6_NAME "n" },
{ UNIT_ADCS6_ROM, UNIT_ADCS6_ROM, "ROM", "ROM",
NULL, NULL, NULL, "Enables boot ROM for unit " ADCS6_NAME "n" },
extern void txcs_wr (int32 dat);
extern void txdb_wr (int32 dat);
extern void ioreset_wr (int32 dat);
extern int32 eval_int (void);
/* SYSD data structures
sysd_dev SYSD device descriptor
sysd_unit SYSD units
sysd_reg SYSD register list
*/
UNIT sysd_unit = { UDATA (NULL, 0, 0) };
REG sysd_reg[] = {
{ HRDATAD (CONISP, conisp, 32, "console ISP") },
{ HRDATAD (CONPC, conpc, 32, "console PD") },
{ HRDATAD (CONPSL, conpsl, 32, "console PSL") },
{ BRDATA (BOOTCMD, cpu_boot_cmd, 16, 8, CBUFSIZE), REG_HRO },
{ NULL }
};
DEVICE sysd_dev = {
"SYSD", &sysd_unit, sysd_reg, NULL,
1, 16, 16, 1, 16, 8,
NULL, NULL, &sysd_reset,
NULL, NULL, NULL,
NULL, 0, 0, NULL, NULL, NULL, NULL, NULL, NULL,
&sysd_description
};
extern int32 sysd_hlt_enb (void);
extern int32 fault_PC;
/* TTI data structures
tti_dev TTI device descriptor
tti_unit TTI unit descriptor
tti_reg TTI register list
*/
DIB tti_dib = { 0, 0, NULL, NULL, 1, IVCL (TTI), SCB_TTI, { NULL } };
UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE|TT_MODE_8B, 0), TMLN_SPD_9600_BPS };
REG tti_reg[] = {
{ HRDATAD (BUF, tti_unit.buf, 16, "last data item processed") },
{ HRDATAD (CSR, tti_csr, 16, "control/status register") },
{ FLDATAD (INT, int_req[IPL_TTI], INT_V_TTI, "interrupt pending flag") },
{ FLDATAD (ERR, tti_csr, CSR_V_ERR, "error flag (CSR<15>)") },
{ FLDATAD (DONE, tti_csr, CSR_V_DONE, "device done flag (CSR<7>)") },
{ FLDATAD (IE, tti_csr, CSR_V_IE, "interrupt enable flag (CSR<6>)") },
{ DRDATAD (POS, tti_unit.pos, T_ADDR_W, "number of characters input"), PV_LEFT },
{ DRDATAD (TIME, tti_unit.wait, 24, "input polling interval"), PV_LEFT },
{ NULL }
};
MTAB tti_mod[] = {
{ TT_MODE, TT_MODE_7B, "7b", "7B", NULL, NULL, NULL, "Set 7 bit mode" },
{ TT_MODE, TT_MODE_8B, "8b", "8B", NULL, NULL, NULL, "Set 8 bit mode" },
{ MTAB_XTD|MTAB_VDV, 0, "VECTOR", NULL, NULL, &show_vec, NULL, "Display interrupt vector" },
{ 0 }
t_bool fl_test_xfr (UNIT *uptr, t_bool wr);
void fl_protocol_error (void);
extern int32 con_halt (int32 code, int32 cc);
/* TTI data structures
tti_dev TTI device descriptor
tti_unit TTI unit descriptor
tti_reg TTI register list
*/
UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE|TT_MODE_8B, 0), TMLN_SPD_9600_BPS };
REG tti_reg[] = {
{ HRDATAD (RXDB, tti_buf, 16, "last data item processed") },
{ HRDATAD (RXCS, tti_csr, 16, "control/status register") },
{ FLDATAD (INT, tti_int, 0, "interrupt pending flag") },
{ FLDATAD (DONE, tti_csr, CSR_V_DONE, "device done flag (CSR<7>)") },
{ FLDATAD (IE, tti_csr, CSR_V_IE, "interrupt enable flag (CSR<6>)") },
{ DRDATAD (POS, tti_unit.pos, T_ADDR_W, "number of characters input"), PV_LEFT },
{ DRDATAD (TIME, tti_unit.wait, 24, "input polling interval"), PV_LEFT },
{ NULL }
};
MTAB tti_mod[] = {
{ TT_MODE, TT_MODE_7B, "7b", "7B", NULL, NULL, NULL, "Set 7 bit mode" },
{ TT_MODE, TT_MODE_8B, "8b", "8B", NULL, NULL, NULL, "Set 8 bit mode" },
{ 0 }
};
/* These are needed for DMA. */
extern void PutByteDMA(const uint32 Addr, const uint32 Value);
extern uint8 GetByteDMA(const uint32 Addr);
static t_stat selchan_reset(DEVICE *selchan_dev);
static int32 selchandev(const int32 port, const int32 io, const int32 data);
static UNIT selchan_unit[] = {
{ UDATA (NULL, UNIT_FIX + UNIT_DISABLE + UNIT_ROABLE, 0) }
};
static REG selchan_reg[] = {
{ HRDATAD (DMA_MODE, selchan_info_data.dma_mode, 8, "DMA mode register"), },
{ HRDATAD (DMA_ADDR, selchan_info_data.dma_addr, 24, "DMA transfer address register"), },
{ NULL }
};
static MTAB selchan_mod[] = {
{ MTAB_XTD|MTAB_VDV, 0, "IOBASE", "IOBASE", &set_iobase, &show_iobase, NULL,
"Sets disk controller I/O base address" },
{ 0 }
};
/* Debug Flags */
static DEBTAB selchan_dt[] = {
{ "VERBOSE", VERBOSE_MSG, "Verbose messages" },
{ "DMA", DMA_MSG, "DMA messages" },
{ NULL, 0 }
t_stat todr_resync (void);
t_stat txdb_misc_wr (int32 data);
extern int32 con_halt (int32 code, int32 cc);
/* TTI data structures
tti_dev TTI device descriptor
tti_unit TTI unit descriptor
tti_reg TTI register list
*/
UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE|TT_MODE_8B, 0), TMLN_SPD_9600_BPS };
REG tti_reg[] = {
{ HRDATAD (RXDB, tti_buf, 16, "last data item processed") },
{ HRDATAD (RXCS, tti_csr, 16, "control/status register") },
{ FLDATAD (INT, tti_int, 0, "interrupt pending flag") },
{ FLDATAD (DONE, tti_csr, CSR_V_DONE, "device done flag (CSR<7>)") },
{ FLDATAD (IE, tti_csr, CSR_V_IE, "interrupt enable flag (CSR<6>)") },
{ DRDATAD (POS, tti_unit.pos, T_ADDR_W, "number of characters input"), PV_LEFT },
{ DRDATAD (TIME, tti_unit.wait, 24, "input polling interval"), PV_LEFT },
{ NULL }
};
MTAB tti_mod[] = {
{ TT_MODE, TT_MODE_7B, "7b", "7B", NULL, NULL, NULL, "Set 7 bit mode" },
{ TT_MODE, TT_MODE_8B, "8b", "8B", NULL, NULL, NULL, "Set 8 bit mode" },
{ 0 }
};
int32 int_vec[IPL_HLVL][32]; /* int req to vector */
/* Unibus adapter data structures
uba_dev UBA device descriptor
uba_unit UBA units
uba_reg UBA register list
*/
DIB uba_dib = { TR_UBA, 0, &uba_rdreg, &uba_wrreg, 0, 0 };
UNIT uba_unit = { UDATA (&uba_svc, 0, 0) };
REG uba_reg[] = {
{ HRDATAD (IPL14, int_req[0], 32, "IPL 14 Interrupt Request"), REG_RO },
{ HRDATAD (IPL15, int_req[1], 32, "IPL 15 Interrupt Request"), REG_RO },
{ HRDATAD (IPL16, int_req[2], 32, "IPL 16 Interrupt Request"), REG_RO },
{ HRDATAD (IPL17, int_req[3], 32, "IPL 17 Interrupt Request"), REG_RO },
{ HRDATAD (CNFR, uba_cnf, 32, "config register") },
{ HRDATAD (CR, uba_cr, 32, "control register") },
{ HRDATAD (SR, uba_sr, 32, "status register") },
{ HRDATAD (DR, uba_dr, 32, "diagnostic control register") },
{ FLDATAD (INT, uba_int, 0, "UBA interrupt") },
{ FLDATAD (NEXINT, nexus_req[IPL_UBA], TR_UBA, "") },
{ FLDATAD (AIIP, uba_aiip, 0, "adapter interrupt in progress") },
{ FLDATAD (UIIP, uba_uiip, 0, "Unibus interrupt in progress") },
{ HRDATAD (FMER, uba_fmer, 32, "failing map register") },
{ HRDATAD (FUBAR, uba_fubar, 32, "failing Unibus address") },
{ HRDATAD (BRSVR0, uba_svr[0], 32, "diagnostic register 0") },
{ HRDATAD (BRSVR1, uba_svr[1], 32, "diagnostic register 1") },
dp_unit DP units
dp_reg DP register list
dp_mod DP modifier list
*/
UNIT dp_unit[] = {
{ UDATA(&dp_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+UNIT_854, DP854_SIZE),
0, 0, 0, 0, 0, &DPunits[0]
},
{ UDATA(&dp_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+UNIT_854, DP854_SIZE),
0, 0, 0, 0, 0, &DPunits[1]
},
};
REG dp_reg[] = {
{ HRDATAD(FUNCTION, DPdev.FUNCTION, 16, "Last director function issued") },
{ HRDATAD(STATUS, DPdev.STATUS, 16, "Director status register") },
{ HRDATAD(IENABLE, DPdev.IENABLE, 16, "Interrupts enabled") },
{ HRDATAD(ADDRSTATUS, DPdev.ADDRSTATUS, 16, "Address register status") },
{ NULL }
};
MTAB dp_mod[] = {
{ MTAB_XTD|MTAB_VDV, 0, "1738-B Disk Pack Controller" },
{ MTAB_XTD|MTAB_VDV, 0, "EQUIPMENT", "EQUIPMENT=hexAddress",
&set_equipment, &show_addr, NULL, "Display equipment address" },
{ MTAB_XTD|MTAB_VUN, 0, "DRIVE", NULL,
NULL, &show_drive, NULL, "Display type of drive (853 or 854" },
{ MTAB_XTD|MTAB_VUN, 0, NULL, "853",
&set_dp853, NULL, NULL, "Set drive type to 853" },
{ MTAB_XTD|MTAB_VUN, 0, NULL, "854",
static t_stat (*mbregW[MBA_NUM])(int32 dat, int32 ad, int32 md);
static int32 (*mbabort[MBA_NUM])(void);
/* Massbus adapter data structures
mba_dev MBA device descriptors
mbax_unit MBA unit
mbax_reg MBA register list
*/
DIB mba0_dib = { TR_MBA0, 0, &mba_rdreg, &mba_wrreg, 0, NVCL (MBA0) };
UNIT mba0_unit = { UDATA (NULL, 0, 0) };
REG mba0_reg[] = {
{ HRDATAD (CNFR, mba_cnf[0], 32, "config register") },
{ HRDATAD (CR, mba_cr[0], 4, "control register") },
{ HRDATAD (SR, mba_sr[0], 32, "status register") },
{ HRDATAD (VA, mba_va[0], 17, "virtual address register") },
{ HRDATAD (BC, mba_bc[0], 16, "byte count register") },
{ HRDATAD (DR, mba_dr[0], 32, "diag register") },
{ HRDATAD (SMR, mba_dr[0], 32, "sel map register") },
{ BRDATAD (MAP, mba_map[0], 16, 32, MBA_NMAPR, "map registers") },
{ FLDATAD (NEXINT, nexus_req[IPL_MBA0], TR_MBA0, "nexus interrupt request") },
{ NULL }
};
MTAB mba0_mod[] = {
{ MTAB_XTD|MTAB_VDV, TR_MBA0, "NEXUS", NULL,
NULL, &show_nexus, NULL, "Display nexus" },
{ 0 }
/* TTI data structures
tti_dev TTI device descriptor
tti_unit TTI unit descriptor
tti_reg TTI register list
*/
UNIT tti_unit[] = {
{ UDATA (&tti_svc, UNIT_IDLE|TT_MODE_8B, 0), 0 },
{ UDATA (&tti_svc, UNIT_IDLE|TT_MODE_8B, 0), 0 },
{ UDATA (&tti_svc, UNIT_IDLE|TT_MODE_8B, 0), 0 },
{ UDATA (&tti_svc, UNIT_IDLE|TT_MODE_8B, 0), 0 },
};
REG tti_reg[] = {
{ HRDATAD (RXDB, tti_buf, 16, "last data item processed") },
{ HRDATAD (RXCS, tti_csr, 16, "control/status register") },
{ FLDATAD (INT, tti_int, 0, "interrupt pending flag") },
{ FLDATAD (DONE, tti_csr, CSR_V_DONE, "device done flag (CSR<7>)") },
{ FLDATAD (IE, tti_csr, CSR_V_IE, "interrupt enable flag (CSR<6>)") },
{ URDATAD (POS, tti_unit[0].pos, 10, T_ADDR_W, 0, 4, PV_LEFT, "number of characters input") },
{ URDATAD (TIME, tti_unit[0].wait, 10, 24, 0, 4, PV_LEFT, "input polling interval") },
{ NULL }
};
MTAB tti_mod[] = {
{ TT_MODE, TT_MODE_7B, "7b", "7B", NULL, NULL, NULL, "Set 7 bit mode" },
{ TT_MODE, TT_MODE_8B, "8b", "8B", NULL, NULL, NULL, "Set 8 bit mode" },
{ 0 }
};
