VOID
HalpInitializeCoreIntrs(VOID
)
{
//
// Here we initialize all the core interrupts that need to
// work EARLY on in kernel startup. Device interrupts are
// not enabled until later (in HalInitSystem).
//
// Each processor needs to call KiSetHandlerAddressToIDT()
// and HalEnableSystemInterrupt() for himself. This is done
// as a by-product of the HAL IDT registration scheme.
//
// Even though race conditions can exist between processors as
// there is no interlocking when calling HalpRegisterVector()
// from HalpEnabledInterruptHandler(), this is not harmful in
// this particular case, as all processors will be writing the
// exact same values.
//
HalpEnableInterruptHandler (
DeviceUsage, // Mark as device vector
DPC_TASKPRI, // No real IRQ, so use this
DPC_TASKPRI, // System IDT
DISPATCH_LEVEL, // System Irql
HalpDispatchInterrupt, // ISR
Latched );
HalpEnableInterruptHandler (
DeviceUsage, // Mark as device vector
APC_TASKPRI, // No real IRQ, so use this
APC_TASKPRI, // System IDT
APC_LEVEL, // System Irql
HalpApcInterrupt, // ISR
Latched );
HalpEnableInterruptHandler (
DeviceUsage, // Mark as device vector
CbusIpiVector, // No real IRQ, so use this
CbusIpiVector, // System IDT
IPI_LEVEL, // System Irql
HalpIpiHandler, // ISR
Latched );
}
VOID
HalpInitPhase0(IN PLOADER_PARAMETER_BLOCK LoaderBlock)
{
/* Enable clock interrupt handler */
HalpEnableInterruptHandler(IDT_INTERNAL,
0,
APIC_CLOCK_VECTOR,
CLOCK2_LEVEL,
HalpClockInterrupt,
Latched);
}
VOID
HalpInitPhase1(VOID)
{
/* Enable IRQ 0 */
HalpEnableInterruptHandler(IDT_DEVICE,
0,
PRIMARY_VECTOR_BASE,
CLOCK2_LEVEL,
HalpClockInterrupt,
Latched);
/* Enable IRQ 8 */
HalpEnableInterruptHandler(IDT_DEVICE,
0,
PRIMARY_VECTOR_BASE + 8,
PROFILE_LEVEL,
HalpProfileInterrupt,
Latched);
/* Initialize DMA. NT does this in Phase 0 */
HalpInitDma();
}
BOOLEAN
HalpCreateSioStructures (
VOID
)
/*++
Routine Description:
This routine initializes the structures necessary for SIO operations
and connects the intermediate interrupt dispatcher.
Arguments:
None.
Return Value:
If the second level interrupt dispatcher is connected, then a value of
TRUE is returned. Otherwise, a value of FALSE is returned.
--*/
{
UCHAR DataByte;
KIRQL oldIrql;
//
// Initialize the Machine Check interrupt handler
//
if (HalpEnableInterruptHandler(&HalpMachineCheckInterrupt,
HalpHandleMachineCheck,
NULL,
NULL,
MACHINE_CHECK_VECTOR,
MACHINE_CHECK_LEVEL,
MACHINE_CHECK_LEVEL,
Latched,
FALSE,
0,
FALSE,
InternalUsage,
MACHINE_CHECK_VECTOR
) == FALSE) {
KeBugCheck(HAL_INITIALIZATION_FAILED);
}
//
// Enable NMI IOCHK# and PCI SERR#
//
DataByte = READ_REGISTER_UCHAR(&((PEISA_CONTROL)HalpIoControlBase)->NmiStatus);
WRITE_REGISTER_UCHAR(&((PEISA_CONTROL)HalpIoControlBase)->NmiStatus,
DataByte & ~DISABLE_IOCHK_NMI & ~DISABLE_PCI_SERR_NMI);
//
// Clear the SIO NMI disable bit. This bit is the high order of the
// NMI enable register.
//
DataByte = 0;
WRITE_REGISTER_UCHAR(
&((PEISA_CONTROL) HalpIoControlBase)->NmiEnable,
DataByte
);
//
// Connect the external interrupt handler
//
PCR->InterruptRoutine[EXTERNAL_INTERRUPT_VECTOR] = (PKINTERRUPT_ROUTINE) HalpHandleExternalInterrupt;
//
// register the interrupt vector
//
HalpRegisterVector(InternalUsage,
EXTERNAL_INTERRUPT_VECTOR,
EXTERNAL_INTERRUPT_VECTOR,
HIGH_LEVEL);
// Connect directly to the decrementer handler. This is done
// directly rather than thru HalpEnableInterruptHandler due to
// special handling required because the handler calls KdPollBreakIn().
//
PCR->InterruptRoutine[DECREMENT_VECTOR] = (PKINTERRUPT_ROUTINE) HalpHandleDecrementerInterrupt;
//
// Initialize and connect the Timer 1 interrupt (IRQ0)
//
if (HalpEnableInterruptHandler( &HalpProfileInterrupt,
(PKSERVICE_ROUTINE) HalpHandleProfileInterrupt,
(PVOID) NULL,
(PKSPIN_LOCK)NULL,
PROFILE_VECTOR,
PROFILE_LEVEL,
PROFILE_LEVEL,
Latched,
TRUE,
0,
FALSE,
DeviceUsage,
PROFILE_VECTOR
) == FALSE) {
KeBugCheck(HAL_INITIALIZATION_FAILED);
}
//
// Disable Timer 1; only used by profiling
//
HalDisableSystemInterrupt(PROFILE_VECTOR, PROFILE_LEVEL);
//
// Set default profile rate
//
HalSetProfileInterval(5000);
//
// Raise the IRQL while the SIO interrupt controller is initialized.
//
KeRaiseIrql(CLOCK2_LEVEL, &oldIrql);
//
// Initialize any planar registers
//
HalpInitPlanar();
//
// Enable the clock interrupt
//
HalpUpdateDecrementer(1000); // Get those decrementer ticks going
//
// Set ISA bus interrupt affinity.
//
HalpIsaBusAffinity = PCR->SetMember;
//
// Restore IRQL level.
//
KeLowerIrql(oldIrql);
//
// DMA command - set assert level
//
DataByte = READ_REGISTER_UCHAR(&((PEISA_CONTROL)HalpIoControlBase)->Dma1BasePort.DmaStatus);
WRITE_REGISTER_UCHAR(&((PEISA_CONTROL)HalpIoControlBase)->Dma1BasePort.DmaStatus,
DataByte & ~DACK_ASSERT_HIGH & ~DREQ_ASSERT_LOW);
//
// Initialize the DMA mode registers to a default value.
// Disable all of the DMA channels except channel 4 which is that
// cascade of channels 0-3.
//
WRITE_REGISTER_UCHAR(
&((PEISA_CONTROL) HalpIoControlBase)->Dma1BasePort.AllMask,
0x0F
);
WRITE_REGISTER_UCHAR(
&((PEISA_CONTROL) HalpIoControlBase)->Dma2BasePort.AllMask,
0x0E
);
return(TRUE);
}
/*
* @implemented
*/
BOOLEAN
NTAPI
HalInitSystem(IN ULONG BootPhase,
IN PLOADER_PARAMETER_BLOCK LoaderBlock)
{
PKPRCB Prcb = KeGetCurrentPrcb();
/* Check the boot phase */
if (!BootPhase)
{
/* Get command-line parameters */
HalpGetParameters(LoaderBlock);
/* Checked HAL requires checked kernel */
#if DBG
if (!(Prcb->BuildType & PRCB_BUILD_DEBUG))
{
/* No match, bugcheck */
KeBugCheckEx(MISMATCHED_HAL, 2, Prcb->BuildType, 1, 0);
}
#else
/* Release build requires release HAL */
if (Prcb->BuildType & PRCB_BUILD_DEBUG)
{
/* No match, bugcheck */
KeBugCheckEx(MISMATCHED_HAL, 2, Prcb->BuildType, 0, 0);
}
#endif
#ifdef CONFIG_SMP
/* SMP HAL requires SMP kernel */
if (Prcb->BuildType & PRCB_BUILD_UNIPROCESSOR)
{
/* No match, bugcheck */
KeBugCheckEx(MISMATCHED_HAL, 2, Prcb->BuildType, 0, 0);
}
#endif
/* Validate the PRCB */
if (Prcb->MajorVersion != PRCB_MAJOR_VERSION)
{
/* Validation failed, bugcheck */
KeBugCheckEx(MISMATCHED_HAL, 1, Prcb->MajorVersion, 1, 0);
}
/* Initialize interrupts */
HalpInitializeInterrupts();
/* Force initial PIC state */
KfRaiseIrql(KeGetCurrentIrql());
/* Fill out the dispatch tables */
//HalQuerySystemInformation = NULL; // FIXME: TODO;
//HalSetSystemInformation = NULL; // FIXME: TODO;
//HalInitPnpDriver = NULL; // FIXME: TODO
//HalGetDmaAdapter = NULL; // FIXME: TODO;
//HalGetInterruptTranslator = NULL; // FIXME: TODO
//HalResetDisplay = NULL; // FIXME: TODO;
//HalHaltSystem = NULL; // FIXME: TODO;
/* Setup I/O space */
//HalpDefaultIoSpace.Next = HalpAddressUsageList;
//HalpAddressUsageList = &HalpDefaultIoSpace;
/* Setup busy waiting */
//HalpCalibrateStallExecution();
/* Initialize the clock */
HalpInitializeClock();
/* Setup time increments to 10ms and 1ms */
HalpCurrentTimeIncrement = 100000;
HalpNextTimeIncrement = 100000;
HalpNextIntervalCount = 0;
KeSetTimeIncrement(100000, 10000);
/*
* We could be rebooting with a pending profile interrupt,
* so clear it here before interrupts are enabled
*/
HalStopProfileInterrupt(ProfileTime);
/* Do some HAL-specific initialization */
HalpInitPhase0(LoaderBlock);
}
else if (BootPhase == 1)
{
/* Enable timer interrupt */
HalpEnableInterruptHandler(IDT_DEVICE,
0,
PRIMARY_VECTOR_BASE,
CLOCK2_LEVEL,
HalpClockInterrupt,
Latched);
#if 0
/* Enable IRQ 8 */
HalpEnableInterruptHandler(IDT_DEVICE,
0,
PRIMARY_VECTOR_BASE + 8,
PROFILE_LEVEL,
HalpProfileInterrupt,
Latched);
#endif
/* Initialize DMA. NT does this in Phase 0 */
//HalpInitDma();
/* Do some HAL-specific initialization */
HalpInitPhase1();
}
/* All done, return */
return TRUE;
}