void internal_tve_set_config(unsigned int type) { volatile PNTSCPAL pHwTVE = (volatile PNTSCPAL)tcc_p2v(HwTVE_BASE); volatile PNTSCPAL_ENCODER_CTRL pHwTVE_VEN = (volatile PNTSCPAL_ENCODER_CTRL)tcc_p2v(HwNTSCPAL_ENC_CTRL_BASE); //Disconnect LCDC with NTSC/PAL encoder BITCLR(pHwTVE_VEN->VENCON.nREG, HwTVEVENCON_EN_EN); //Set ECMDA Register internal_tve_set_mode(type); //Set ECMDB Register BITSET(pHwTVE->ECMDB.nREG, HwTVECMDB_CBW(2)|HwTVECMDB_YBW(2)); //Set SAT Register BITSET(pHwTVE->SAT.nREG, 0x44); //Set DACSEL Register BITSET(pHwTVE->DACSEL.nREG, HwTVEDACSEL_DACSEL_CVBS); //Set DACPD Register BITCLR(pHwTVE->DACPD.nREG, HwTVEDACPD_PD_EN); BITSET(pHwTVE->ICNTL.nREG, HwTVEICNTL_VSIP_HIGH); BITSET(pHwTVE->ICNTL.nREG, HwTVEICNTL_HSVSP_RISING); #ifdef TCC_COMPOSITE_CCIR656 BITCSET(pHwTVE->ICNTL.nREG, HwTVEICNTL_ISYNC_MASK, HwTVEICNTL_ISYNC_ESAV_F); #else BITCSET(pHwTVE->ICNTL.nREG, HwTVEICNTL_ISYNC_MASK, HwTVEICNTL_ISYNC_HVSI); #endif //Set the Vertical Offset BITCSET(pHwTVE->HVOFFST.nREG, 0x07, ((0 & 0x700)>>8)); pHwTVE->HOFFST.nREG = (0 & 0xFF); //Set the Horizontal Offset BITCSET(pHwTVE->HVOFFST.nREG, 0x08, ((1 & 0x100)>>5)); pHwTVE->VOFFST.nREG = (1 & 0xFF); //Set the Digital Output Format BITCSET(pHwTVE->HVOFFST.nREG, HwTVEHVOFFST_INSEL_MASK, HwTVEHVOFFST_INSEL(2)); //Set HSVSO Register BITCSET(pHwTVE->HSVSO.nREG, 0x07, ((0 & 0x700)>>8)); pHwTVE->HSOE.nREG = (0 & 0xFF); BITCSET(pHwTVE->HSVSO.nREG, 0x38, ((0 & 0x700)>>5)); pHwTVE->HSOB.nREG = (0 & 0xFF); BITCSET(pHwTVE->HSVSO.nREG, 0x40, ((0 & 0x100)>>2)); pHwTVE->VSOB.nREG = (0 & 0xFF); //Set VSOE Register BITCSET(pHwTVE->VSOE.nREG, 0x1F, (0 & 0x1F)); BITCSET(pHwTVE->VSOE.nREG, 0xC0, (0 & 0x03)<<6); BITCSET(pHwTVE->VSOE.nREG, 0x20, (0 & 0x01)<<5); //Set the Connection Type BITSET(pHwTVE_VEN->VENCIF.nREG, HwTVEVENCIF_FMT_1); BITSET(pHwTVE_VEN->VENCON.nREG, HwTVEVENCON_EN_EN); BITSET(pHwTVE->DACPD.nREG, HwTVEDACPD_PD_EN); BITCLR(pHwTVE->ECMDA.nREG, HwTVECMDA_PWDENC_PD); }
static void lcdc_io_init_composite(unsigned char lcdc_num, unsigned char type) { unsigned int lcd_reg = 0; unsigned int width, height; stCOMPOSITE_SPEC spec; stLTIMING CompositeTiming; stLCDCTR LcdCtrlParam; PVIOC_DISP pDISPBase; PVIOC_WMIX pWIXBase; PVIOC_RDMA pRDMA; PDDICONFIG pDDICfg = (PDDICONFIG)HwDDI_CONFIG_BASE; PNTSCPAL pTVE = (PNTSCPAL)HwNTSCPAL_BASE; PNTSCPAL_ENCODER_CTRL pTVE_VEN = (PNTSCPAL_ENCODER_CTRL)HwNTSCPAL_ENC_CTRL_BASE; struct fbcon_config *fb_con; printf("%s, lcdc_num=%d, type=%d\n", __func__, lcdc_num, type); if(type >= LCDC_COMPOSITE_MAX) type = defalut_composite_resolution; composite_get_spec(type, &spec); fb_con = &fb_cfg; BITSET(pDDICfg->PWDN.nREG, Hw1); // PWDN - TVE BITCLR(pDDICfg->SWRESET.nREG, Hw1); // SWRESET - TVE BITSET(pDDICfg->SWRESET.nREG, Hw1); // SWRESET - TVE BITSET(pDDICfg->NTSCPAL_EN.nREG, Hw0); // NTSCPAL_EN if(lcdc_num) { pDISPBase = (VIOC_DISP *)HwVIOC_DISP1; pWIXBase =(VIOC_WMIX *)HwVIOC_WMIX1; tca_ckc_setperi(PERI_LCD1, ENABLE, spec.composite_clock*spec.composite_divider); VIOC_OUTCFG_SetOutConfig(VIOC_OUTCFG_SDVENC, VIOC_OUTCFG_DISP1); } else { pDISPBase = (VIOC_DISP *)HwVIOC_DISP0; pWIXBase =(VIOC_WMIX *)HwVIOC_WMIX0; tca_ckc_setperi(PERI_LCD0, ENABLE, spec.composite_clock*spec.composite_divider); VIOC_OUTCFG_SetOutConfig(VIOC_OUTCFG_SDVENC, VIOC_OUTCFG_DISP0); } printf("lcdc_num = %d, LCDC0 clk:%d, LCDC1 clk:%d, divide:%d\n", lcdc_num, tca_ckc_getperi(PERI_LCD0), tca_ckc_getperi(PERI_LCD1), spec.composite_divider); //LCDC_IO_Set(lcdc_num, spec.composite_bus_width); // hdmi power wake up tca_ckc_setippwdn(PMU_ISOL_VDAC, 0); //tca_ckc_setperi(PERI_HDMI, ENABLE, 10000); width = spec.composite_width; height = spec.composite_height; lcdc_set_logo(lcdc_num, width, height, fb_con); CompositeTiming.lpw = spec.composite_LPW; CompositeTiming.lpc = spec.composite_LPC + 1; CompositeTiming.lswc = spec.composite_LSWC + 1; CompositeTiming.lewc = spec.composite_LEWC + 1; CompositeTiming.vdb = spec.composite_VDB; CompositeTiming.vdf = spec.composite_VDF; CompositeTiming.fpw = spec.composite_FPW1; CompositeTiming.flc = spec.composite_FLC1; CompositeTiming.fswc = spec.composite_FSWC1; CompositeTiming.fewc = spec.composite_FEWC1; CompositeTiming.fpw2 = spec.composite_FPW2; CompositeTiming.flc2 = spec.composite_FLC2; CompositeTiming.fswc2 = spec.composite_FSWC2; CompositeTiming.fewc2 = spec.composite_FEWC2; VIOC_DISP_SetTimingParam(pDISPBase, &CompositeTiming); memset(&LcdCtrlParam, NULL, sizeof(LcdCtrlParam)); LcdCtrlParam.r2ymd = 3; LcdCtrlParam.ckg = 1; //LcdCtrlParam.id= 0; LcdCtrlParam.iv = 1; LcdCtrlParam.ih = 1; LcdCtrlParam.ip = 1; LcdCtrlParam.clen = 1; LcdCtrlParam.r2y = 1; LcdCtrlParam.pxdw = 6; //LcdCtrlParam.dp = 0; //LcdCtrlParam.ni = 0; LcdCtrlParam.tv = 1; //LcdCtrlParam.opt = 0; //LcdCtrlParam.stn = 0; //LcdCtrlParam.evsel = 0; //LcdCtrlParam.ovp = 0; VIOC_DISP_SetControlConfigure(pDISPBase, &LcdCtrlParam); VIOC_DISP_SetSize(pDISPBase, width, height); VIOC_DISP_SetBGColor(pDISPBase, 0, 0 , 0); //VIOC_DISP_TurnOn(pDISPBase); VIOC_WMIX_SetOverlayPriority(pWIXBase, 24); VIOC_WMIX_SetBGColor(pWIXBase, 0x00, 0x00, 0x00, 0xff); VIOC_WMIX_SetSize(pWIXBase, width, height); VIOC_WMIX_SetUpdate(pWIXBase); //Disconnect LCDC with NTSC/PAL encoder BITCLR(pTVE_VEN->VENCON.nREG, HwTVEVENCON_EN_EN); //Set ECMDA Register if(type == LCDC_COMPOSITE_NTSC) { pTVE->ECMDA.nREG = HwTVECMDA_PWDENC_PD | // [7] Power down mode for entire digital logic of TV encoder HwTVECMDA_FDRST_1 | // [6] Chroma is free running as compared to H-sync HwTVECMDA_FSCSEL_NTSC | // [5:4] Color subcarrier frequency is 3.57954545 MHz for NTSC HwTVECMDA_PEDESTAL | // [3] Video Output has a pedestal (0 is NTSC-J) HwTVECMDA_PIXEL_601 | // [2] Input data is at 601 rates. HwTVECMDA_IFMT_525 | // [1] Output data has 525 lines HwTVECMDA_PHALT_NTSC | // [0] NTSC encoded chroma signal output 0; } else { pTVE->ECMDA.nREG = HwTVECMDA_FDRST_1 | // [6] Chroma is free running as compared to H-sync HwTVECMDA_FSCSEL_PALX | // [5:4] Color subcarrier frequency is 4.43361875 MHz for PAL-B,D,G,H,I,N HwTVECMDA_PIXEL_601 | // [2] Input data is at 601 rates. HwTVECMDA_IFMT_625 | // [1] Output data has 625 lines HwTVECMDA_PHALT_PAL | // [0] PAL encoded chroma signal output 0; } //Set DACSEL Register BITSET(pTVE->DACSEL.nREG, HwTVEDACSEL_DACSEL_CVBS); //Set DACPD Register #if defined(TCC892X) BITCLR(pTVE->DACPD.nREG, HwTVEDACPD_PD_EN); #else BITSET(pTVE->DACPD.nREG, HwTVEDACPD_PD_EN); #endif BITSET(pTVE->ICNTL.nREG, HwTVEICNTL_VSIP_HIGH); BITSET(pTVE->ICNTL.nREG, HwTVEICNTL_HSVSP_RISING); #if 0 // COMPOSITE_CCIR656 BITCSET(pTVE->ICNTL.nREG, HwTVEICNTL_ISYNC_MASK, HwTVEICNTL_ISYNC_ESAV_F); #else BITCSET(pTVE->ICNTL.nREG, HwTVEICNTL_ISYNC_MASK, HwTVEICNTL_ISYNC_HVSI); #endif //Set the Vertical Offset BITCSET(pTVE->HVOFFST.nREG, 0x07, ((0 & 0x700)>>8)); pTVE->HOFFST.nREG = (0 & 0xFF); //Set the Horizontal Offset BITCSET(pTVE->HVOFFST.nREG, 0x08, ((1 & 0x100)>>5)); pTVE->VOFFST.nREG = (1 & 0xFF); //Set the Digital Output Format BITCSET(pTVE->HVOFFST.nREG, HwTVEHVOFFST_INSEL_MASK, HwTVEHVOFFST_INSEL(2)); //Set HSVSO Register BITCSET(pTVE->HSVSO.nREG, 0x07, ((0 & 0x700)>>8)); pTVE->HSOE.nREG = (0 & 0xFF); BITCSET(pTVE->HSVSO.nREG, 0x38, ((0 & 0x700)>>5)); pTVE->HSOB.nREG = (0 & 0xFF); BITCSET(pTVE->HSVSO.nREG, 0x40, ((0 & 0x100)>>2)); pTVE->VSOB.nREG = (0 & 0xFF); //Set VSOE Register BITCSET(pTVE->VSOE.nREG, 0x1F, (0 & 0x1F)); BITCSET(pTVE->VSOE.nREG, 0xC0, (0 & 0x03)<<6); BITCSET(pTVE->VSOE.nREG, 0x20, (0 & 0x01)<<5); //Set the Connection Type BITSET(pTVE_VEN->VENCIF.nREG, HwTVEVENCIF_FMT_1); BITSET(pTVE_VEN->VENCON.nREG, HwTVEVENCON_EN_EN); #if defined(TCC892X) BITSET(pTVE->DACPD.nREG, HwTVEDACPD_PD_EN); #else BITCLR(pTVE->DACPD.nREG, HwTVEDACPD_PD_EN); #endif BITCLR(pTVE->ECMDA.nREG, HwTVECMDA_PWDENC_PD); VIOC_DISP_TurnOn(pDISPBase); }