/*
 * --------------------- OP LS DERIVED FUNCTION
 */
void CaPerfTranslator::trans_ibs_op_ls(struct ibs_op_sample* trans_op,
                                       gtUInt32 selected_flag,
                                       CpuProfileProcess* pProc,
                                       gtUInt64 ldAddr, gtUInt32 funcSize, CpuProfileModule* pMod,
                                       gtUInt64 ip, gtUInt32 pid, gtUInt32 tid, gtUInt32 cpu,
                                       gtUInt32 os, gtUInt32 usr, gtUInt32 count, const FunctionSymbolInfo* pFuncInfo)
{
    // In per-process mode, ignore this sample if it does not belong to the target pid
    if (! _isTargetPid(pid))
    {
        return;
    }

    /* Preliminary check */
    if (!IBS_OP_IBS_LD_OP(trans_op) && !IBS_OP_IBS_ST_OP(trans_op))
    {
        return;
    }

    if ((selected_flag) == 0)
    {
        return;
    }

    CHECK_OP_LS_SELECTED_FLAG(DE_IBS_LS_ALL_OP)
    {
        /* Count the number of LS op samples */
        AGG_IBS_COUNT(DE_IBS_LS_ALL_OP, count) ;
    }

    CHECK_OP_LS_SELECTED_FLAG(DE_IBS_LS_LOAD_OP)
    {
        if (IBS_OP_IBS_LD_OP(trans_op))
            /* TALLy an IBS load derived event */
        {
            AGG_IBS_COUNT(DE_IBS_LS_LOAD_OP, count) ;
        }
    }

    CHECK_OP_LS_SELECTED_FLAG(DE_IBS_LS_STORE_OP)
    {
        if (IBS_OP_IBS_ST_OP(trans_op))
            /* Count and handle store operations */
        {
            AGG_IBS_COUNT(DE_IBS_LS_STORE_OP, count);
        }
    }

    CHECK_OP_LS_SELECTED_FLAG(DE_IBS_LS_DTLB_L1H)
    {
        if (IBS_OP_IBS_DC_LIN_ADDR_VALID(trans_op)
            && !IBS_OP_IBS_DC_L1_TLB_MISS(trans_op))
            /* L1 DTLB hit -- This is the most frequent case */
        {
            AGG_IBS_COUNT(DE_IBS_LS_DTLB_L1H, count);
        }
    }

    CHECK_OP_LS_SELECTED_FLAG(DE_IBS_LS_DTLB_L1M_L2H)
    {
        /* l2_translation_size = 1 */
        if (IBS_OP_IBS_DC_LIN_ADDR_VALID(trans_op)
            && IBS_OP_IBS_DC_L1_TLB_MISS(trans_op)
            && !IBS_OP_IBS_DC_L2_TLB_MISS(trans_op))
            /* L1 DTLB miss, L2 DTLB hit */
        {
            AGG_IBS_COUNT(DE_IBS_LS_DTLB_L1M_L2H, count);
        }
    }

    CHECK_OP_LS_SELECTED_FLAG(DE_IBS_LS_DTLB_L1M_L2M)
    {
        if (IBS_OP_IBS_DC_LIN_ADDR_VALID(trans_op)
            && IBS_OP_IBS_DC_L1_TLB_MISS(trans_op)
            && IBS_OP_IBS_DC_L2_TLB_MISS(trans_op))
            /* L1 DTLB miss, L2 DTLB miss */
        {
            AGG_IBS_COUNT(DE_IBS_LS_DTLB_L1M_L2M, count);
        }
    }

    CHECK_OP_LS_SELECTED_FLAG(DE_IBS_LS_DC_MISS)
    {
        if (IBS_OP_IBS_DC_MISS(trans_op))
        {
            AGG_IBS_COUNT(DE_IBS_LS_DC_MISS, count);
        }
    }

    CHECK_OP_LS_SELECTED_FLAG(DE_IBS_LS_DC_HIT)
    {
        if (!IBS_OP_IBS_DC_MISS(trans_op))
        {
            AGG_IBS_COUNT(DE_IBS_LS_DC_HIT, count);
        }
    }

    CHECK_OP_LS_SELECTED_FLAG(DE_IBS_LS_MISALIGNED)
    {
        if (IBS_OP_IBS_DC_MISS_ACC(trans_op))
        {
            AGG_IBS_COUNT(DE_IBS_LS_MISALIGNED, count);
        }
    }

    CHECK_OP_LS_SELECTED_FLAG(DE_IBS_LS_BNK_CONF_LOAD)
    {
        if (IBS_OP_IBS_DC_LD_BNK_CON(trans_op))
        {
            AGG_IBS_COUNT(DE_IBS_LS_BNK_CONF_LOAD, count);
        }
    }

    CHECK_OP_LS_SELECTED_FLAG(DE_IBS_LS_BNK_CONF_STORE)
    {
        if (IBS_OP_IBS_DC_ST_BNK_CON(trans_op))
        {
            AGG_IBS_COUNT(DE_IBS_LS_BNK_CONF_STORE, count);
        }
    }

    CHECK_OP_LS_SELECTED_FLAG(DE_IBS_LS_STL_FORWARDED)
    {
        if (IBS_OP_IBS_LD_OP(trans_op)
            /* Data forwarding info are valid only for load ops */
            && IBS_OP_IBS_DC_ST_TO_LD_FWD(trans_op))
        {
            AGG_IBS_COUNT(DE_IBS_LS_STL_FORWARDED, count) ;
        }
    }

    CHECK_OP_LS_SELECTED_FLAG(DE_IBS_LS_STL_CANCELLED)
    {
        if (IBS_OP_IBS_LD_OP(trans_op))
            if (IBS_OP_IBS_DC_ST_TO_LD_CAN(trans_op))
            {
                AGG_IBS_COUNT(DE_IBS_LS_STL_CANCELLED, count) ;
            }
    }

    CHECK_OP_LS_SELECTED_FLAG(DE_IBS_LS_UC_MEM_ACCESS)
    {
        if (IBS_OP_IBS_DC_UC_MEM_ACC(trans_op))
        {
            AGG_IBS_COUNT(DE_IBS_LS_UC_MEM_ACCESS, count);
        }
    }

    CHECK_OP_LS_SELECTED_FLAG(DE_IBS_LS_WC_MEM_ACCESS)
    {
        if (IBS_OP_IBS_DC_WC_MEM_ACC(trans_op))
        {
            AGG_IBS_COUNT(DE_IBS_LS_WC_MEM_ACCESS, count);
        }
    }

    CHECK_OP_LS_SELECTED_FLAG(DE_IBS_LS_LOCKED_OP)
    {
        if (IBS_OP_IBS_LOCKED_OP(trans_op))
        {
            AGG_IBS_COUNT(DE_IBS_LS_LOCKED_OP, count);
        }
    }

    CHECK_OP_LS_SELECTED_FLAG(DE_IBS_LS_MAB_HIT)
    {
        if (IBS_OP_IBS_DC_MAB_HIT(trans_op))
        {
            AGG_IBS_COUNT(DE_IBS_LS_MAB_HIT, count);
        }
    }

    CHECK_OP_LS_SELECTED_FLAG(DE_IBS_LS_L1_DTLB_4K)
    {
        /* l1_translation */
        if (IBS_OP_IBS_DC_LIN_ADDR_VALID(trans_op)
            && !IBS_OP_IBS_DC_L1_TLB_MISS(trans_op)

            && !IBS_OP_IBS_DC_L1_TLB_HIT_2MB(trans_op)
            && !IBS_OP_IBS_DC_L1_TLB_HIT_1GB(trans_op))
            /* This is the most common case, unfortunately */
        {
            AGG_IBS_COUNT(DE_IBS_LS_L1_DTLB_4K, count) ;
        }
    }

    CHECK_OP_LS_SELECTED_FLAG(DE_IBS_LS_L1_DTLB_2M)
    {
        /* l1_translation */
        if (IBS_OP_IBS_DC_LIN_ADDR_VALID(trans_op)
            && !IBS_OP_IBS_DC_L1_TLB_MISS(trans_op)

            && IBS_OP_IBS_DC_L1_TLB_HIT_2MB(trans_op))
            /* 2M L1 DTLB page translation */
        {
            AGG_IBS_COUNT(DE_IBS_LS_L1_DTLB_2M, count);
        }
    }

    CHECK_OP_LS_SELECTED_FLAG(DE_IBS_LS_L1_DTLB_1G)
    {
        /* l1_translation */
        if (IBS_OP_IBS_DC_LIN_ADDR_VALID(trans_op)
            && !IBS_OP_IBS_DC_L1_TLB_MISS(trans_op)

            && !IBS_OP_IBS_DC_L1_TLB_HIT_2MB(trans_op)
            && IBS_OP_IBS_DC_L1_TLB_HIT_1GB(trans_op))
            /* 1G L1 DTLB page translation */
        {
            AGG_IBS_COUNT(DE_IBS_LS_L1_DTLB_1G, count);
        }
    }

    CHECK_OP_LS_SELECTED_FLAG(DE_IBS_LS_L1_DTLB_RES)
    {
    }

    CHECK_OP_LS_SELECTED_FLAG(DE_IBS_LS_L2_DTLB_4K)
    {
        /* l2_translation_size = 1 */
        if (IBS_OP_IBS_DC_LIN_ADDR_VALID(trans_op)
            && IBS_OP_IBS_DC_L1_TLB_MISS(trans_op)
            && !IBS_OP_IBS_DC_L2_TLB_MISS(trans_op)

            /* L2 DTLB page translation */
            && !IBS_OP_IBS_DC_L2_TLB_HIT_2MB(trans_op)
            && !IBS_OP_IBS_DC_L2_TLB_HIT_1GB(trans_op))
            /* 4K L2 DTLB page translation */
        {
            AGG_IBS_COUNT(DE_IBS_LS_L2_DTLB_4K, count);
        }
    }

    CHECK_OP_LS_SELECTED_FLAG(DE_IBS_LS_L2_DTLB_2M)
    {
        /* l2_translation_size = 1 */
        if (IBS_OP_IBS_DC_LIN_ADDR_VALID(trans_op)
            && IBS_OP_IBS_DC_L1_TLB_MISS(trans_op)
            && !IBS_OP_IBS_DC_L2_TLB_MISS(trans_op)

            /* L2 DTLB page translation */
            && IBS_OP_IBS_DC_L2_TLB_HIT_2MB(trans_op)
            && !IBS_OP_IBS_DC_L2_TLB_HIT_1GB(trans_op))
            /* 2M L2 DTLB page translation */
        {
            AGG_IBS_COUNT(DE_IBS_LS_L2_DTLB_2M, count);
        }
    }

    CHECK_OP_LS_SELECTED_FLAG(DE_IBS_LS_L2_DTLB_1G)
    {
        /* l2_translation_size = 1 */
        if (IBS_OP_IBS_DC_LIN_ADDR_VALID(trans_op)
            && IBS_OP_IBS_DC_L1_TLB_MISS(trans_op)
            && !IBS_OP_IBS_DC_L2_TLB_MISS(trans_op)

            /* L2 DTLB page translation */
            && !IBS_OP_IBS_DC_L2_TLB_HIT_2MB(trans_op)
            && IBS_OP_IBS_DC_L2_TLB_HIT_1GB(trans_op))
            /* 2M L2 DTLB page translation */
        {
            AGG_IBS_COUNT(DE_IBS_LS_L2_DTLB_1G, count);
        }
    }

    CHECK_OP_LS_SELECTED_FLAG(DE_IBS_LS_L2_DTLB_RES2)
    {
    }

    CHECK_OP_LS_SELECTED_FLAG(DE_IBS_LS_DC_LOAD_LAT)
    {
        if (IBS_OP_IBS_LD_OP(trans_op)
            /* If the load missed in DC, tally the DC load miss latency */
            && IBS_OP_IBS_DC_MISS(trans_op))
            /* DC load miss latency is only reliable for load ops */
            AGG_IBS_COUNT(DE_IBS_LS_DC_LOAD_LAT,
                          IBS_OP_DC_MISS_LATENCY(trans_op)) ;
    }
}
/*
 * --------------------- OP LS DERIVED FUNCTION
 */
void trans_ibs_op_ls (struct transient * trans, unsigned int selected_flag, unsigned int size)
{
    struct ibs_op_sample * trans_op = ((struct ibs_sample*)(trans->ext))->op;
    unsigned int i, j, mask = 1;

    /* Preliminary check */
    if (!IBS_OP_IBS_LD_OP(trans_op) && !IBS_OP_IBS_ST_OP(trans_op))
        return;


    for (i = IBS_OP_LS_BASE, j =0 ; i <= IBS_OP_LS_END && j < size ; i++, mask = mask << 1) {

        if ((selected_flag & mask) == 0)
            continue;

        j++;

        switch (i) {

        case DE_IBS_LS_ALL_OP:
            /* Count the number of LS op samples */
            AGG_IBS_EVENT(DE_IBS_LS_ALL_OP) ;
            break;

        case DE_IBS_LS_LOAD_OP:
            if (IBS_OP_IBS_LD_OP(trans_op))
                /* TALLy an IBS load derived event */
                AGG_IBS_EVENT(DE_IBS_LS_LOAD_OP) ;
            break;

        case DE_IBS_LS_STORE_OP:
            if (IBS_OP_IBS_ST_OP(trans_op))
                /* Count and handle store operations */
                AGG_IBS_EVENT(DE_IBS_LS_STORE_OP);
            break;

        case DE_IBS_LS_DTLB_L1H:
            if (IBS_OP_IBS_DC_LIN_ADDR_VALID(trans_op)
                    && !IBS_OP_IBS_DC_L1_TLB_MISS(trans_op))
                /* L1 DTLB hit -- This is the most frequent case */
                AGG_IBS_EVENT(DE_IBS_LS_DTLB_L1H);
            break;

        case DE_IBS_LS_DTLB_L1M_L2H:
            /* l2_translation_size = 1 */
            if (IBS_OP_IBS_DC_LIN_ADDR_VALID(trans_op)
                    && IBS_OP_IBS_DC_L1_TLB_MISS(trans_op)
                    && !IBS_OP_IBS_DC_L2_TLB_MISS(trans_op))
                /* L1 DTLB miss, L2 DTLB hit */
                AGG_IBS_EVENT(DE_IBS_LS_DTLB_L1M_L2H);
            break;

        case DE_IBS_LS_DTLB_L1M_L2M:
            if (IBS_OP_IBS_DC_LIN_ADDR_VALID(trans_op)
                    && IBS_OP_IBS_DC_L1_TLB_MISS(trans_op)
                    && IBS_OP_IBS_DC_L2_TLB_MISS(trans_op))
                /* L1 DTLB miss, L2 DTLB miss */
                AGG_IBS_EVENT(DE_IBS_LS_DTLB_L1M_L2M);
            break;

        case DE_IBS_LS_DC_MISS:
            if (IBS_OP_IBS_DC_MISS(trans_op))
                AGG_IBS_EVENT(DE_IBS_LS_DC_MISS);
            break;

        case DE_IBS_LS_DC_HIT:
            if (!IBS_OP_IBS_DC_MISS(trans_op))
                AGG_IBS_EVENT(DE_IBS_LS_DC_HIT);
            break;

        case DE_IBS_LS_MISALIGNED:
            if (IBS_OP_IBS_DC_MISS_ACC(trans_op))
                AGG_IBS_EVENT(DE_IBS_LS_MISALIGNED);
            break;

        case DE_IBS_LS_BNK_CONF_LOAD:
            if (IBS_OP_IBS_DC_LD_BNK_CON(trans_op))
                AGG_IBS_EVENT(DE_IBS_LS_BNK_CONF_LOAD);
            break;

        case DE_IBS_LS_BNK_CONF_STORE:
            if (IBS_OP_IBS_DC_ST_BNK_CON(trans_op))
                AGG_IBS_EVENT(DE_IBS_LS_BNK_CONF_STORE);
            break;

        case DE_IBS_LS_STL_FORWARDED:
            if (IBS_OP_IBS_LD_OP(trans_op)
                    /* Data forwarding info are valid only for load ops */
                    && IBS_OP_IBS_DC_ST_TO_LD_FWD(trans_op))
                AGG_IBS_EVENT(DE_IBS_LS_STL_FORWARDED) ;
            break;

        case DE_IBS_LS_STL_CANCELLED:
            if (IBS_OP_IBS_LD_OP(trans_op))
                if (IBS_OP_IBS_DC_ST_TO_LD_CAN(trans_op))
                    AGG_IBS_EVENT(DE_IBS_LS_STL_CANCELLED) ;
            break;

        case DE_IBS_LS_UC_MEM_ACCESS:
            if (IBS_OP_IBS_DC_UC_MEM_ACC(trans_op))
                AGG_IBS_EVENT(DE_IBS_LS_UC_MEM_ACCESS);
            break;

        case DE_IBS_LS_WC_MEM_ACCESS:
            if (IBS_OP_IBS_DC_WC_MEM_ACC(trans_op))
                AGG_IBS_EVENT(DE_IBS_LS_WC_MEM_ACCESS);
            break;

        case DE_IBS_LS_LOCKED_OP:
            if (IBS_OP_IBS_LOCKED_OP(trans_op))
                AGG_IBS_EVENT(DE_IBS_LS_LOCKED_OP);
            break;

        case DE_IBS_LS_MAB_HIT:
            if (IBS_OP_IBS_DC_MAB_HIT(trans_op))
                AGG_IBS_EVENT(DE_IBS_LS_MAB_HIT);
            break;

        case DE_IBS_LS_L1_DTLB_4K:
            /* l1_translation */
            if (IBS_OP_IBS_DC_LIN_ADDR_VALID(trans_op)
                    && !IBS_OP_IBS_DC_L1_TLB_MISS(trans_op)

                    && !IBS_OP_IBS_DC_L1_TLB_HIT_2MB(trans_op)
                    && !IBS_OP_IBS_DC_L1_TLB_HIT_1GB(trans_op))
                /* This is the most common case, unfortunately */
                AGG_IBS_EVENT(DE_IBS_LS_L1_DTLB_4K) ;
            break;

        case DE_IBS_LS_L1_DTLB_2M:
            /* l1_translation */
            if (IBS_OP_IBS_DC_LIN_ADDR_VALID(trans_op)
                    && !IBS_OP_IBS_DC_L1_TLB_MISS(trans_op)

                    && IBS_OP_IBS_DC_L1_TLB_HIT_2MB(trans_op))
                /* 2M L1 DTLB page translation */
                AGG_IBS_EVENT(DE_IBS_LS_L1_DTLB_2M);
            break;

        case DE_IBS_LS_L1_DTLB_1G:
            /* l1_translation */
            if (IBS_OP_IBS_DC_LIN_ADDR_VALID(trans_op)
                    && !IBS_OP_IBS_DC_L1_TLB_MISS(trans_op)

                    && !IBS_OP_IBS_DC_L1_TLB_HIT_2MB(trans_op)
                    && IBS_OP_IBS_DC_L1_TLB_HIT_1GB(trans_op))
                /* 1G L1 DTLB page translation */
                AGG_IBS_EVENT(DE_IBS_LS_L1_DTLB_1G);
            break;

        case DE_IBS_LS_L1_DTLB_RES:
            break;

        case DE_IBS_LS_L2_DTLB_4K:
            /* l2_translation_size = 1 */
            if (IBS_OP_IBS_DC_LIN_ADDR_VALID(trans_op)
                    && IBS_OP_IBS_DC_L1_TLB_MISS(trans_op)
                    && !IBS_OP_IBS_DC_L2_TLB_MISS(trans_op)

                    /* L2 DTLB page translation */
                    && !IBS_OP_IBS_DC_L2_TLB_HIT_2MB(trans_op)
                    && !IBS_OP_IBS_DC_L2_TLB_HIT_1GB(trans_op))
                /* 4K L2 DTLB page translation */
                AGG_IBS_EVENT(DE_IBS_LS_L2_DTLB_4K);
            break;

        case DE_IBS_LS_L2_DTLB_2M:
            /* l2_translation_size = 1 */
            if (IBS_OP_IBS_DC_LIN_ADDR_VALID(trans_op)
                    && IBS_OP_IBS_DC_L1_TLB_MISS(trans_op)
                    && !IBS_OP_IBS_DC_L2_TLB_MISS(trans_op)

                    /* L2 DTLB page translation */
                    && IBS_OP_IBS_DC_L2_TLB_HIT_2MB(trans_op)
                    && !IBS_OP_IBS_DC_L2_TLB_HIT_1GB(trans_op))
                /* 2M L2 DTLB page translation */
                AGG_IBS_EVENT(DE_IBS_LS_L2_DTLB_2M);
            break;

        case DE_IBS_LS_L2_DTLB_1G:
            /* l2_translation_size = 1 */
            if (IBS_OP_IBS_DC_LIN_ADDR_VALID(trans_op)
                    && IBS_OP_IBS_DC_L1_TLB_MISS(trans_op)
                    && !IBS_OP_IBS_DC_L2_TLB_MISS(trans_op)

                    /* L2 DTLB page translation */
                    && !IBS_OP_IBS_DC_L2_TLB_HIT_2MB(trans_op)
                    && IBS_OP_IBS_DC_L2_TLB_HIT_1GB(trans_op))
                /* 2M L2 DTLB page translation */
                AGG_IBS_EVENT(DE_IBS_LS_L2_DTLB_1G);
            break;

        case DE_IBS_LS_L2_DTLB_RES2:
            break;

        case DE_IBS_LS_DC_LOAD_LAT:
            if (IBS_OP_IBS_LD_OP(trans_op)
                    /* If the load missed in DC, tally the DC load miss latency */
                    && IBS_OP_IBS_DC_MISS(trans_op))
                /* DC load miss latency is only reliable for load ops */
                AGG_IBS_COUNT(DE_IBS_LS_DC_LOAD_LAT,
                              IBS_OP_DC_MISS_LATENCY(trans_op)) ;
            break;

        default:
            break;
        }
    }
}