void ipu_dump_registers(void) { debug("IPU_CONF = \t0x%08X\n", __raw_readl(IPU_CONF)); debug("IDMAC_CONF = \t0x%08X\n", __raw_readl(IDMAC_CONF)); debug("IDMAC_CHA_EN1 = \t0x%08X\n", __raw_readl(IDMAC_CHA_EN(0))); debug("IDMAC_CHA_EN2 = \t0x%08X\n", __raw_readl(IDMAC_CHA_EN(32))); debug("IDMAC_CHA_PRI1 = \t0x%08X\n", __raw_readl(IDMAC_CHA_PRI(0))); debug("IDMAC_CHA_PRI2 = \t0x%08X\n", __raw_readl(IDMAC_CHA_PRI(32))); debug("IPU_CHA_DB_MODE_SEL0 = \t0x%08X\n", __raw_readl(IPU_CHA_DB_MODE_SEL(0))); debug("IPU_CHA_DB_MODE_SEL1 = \t0x%08X\n", __raw_readl(IPU_CHA_DB_MODE_SEL(32))); debug("DMFC_WR_CHAN = \t0x%08X\n", __raw_readl(DMFC_WR_CHAN)); debug("DMFC_WR_CHAN_DEF = \t0x%08X\n", __raw_readl(DMFC_WR_CHAN_DEF)); debug("DMFC_DP_CHAN = \t0x%08X\n", __raw_readl(DMFC_DP_CHAN)); debug("DMFC_DP_CHAN_DEF = \t0x%08X\n", __raw_readl(DMFC_DP_CHAN_DEF)); debug("DMFC_IC_CTRL = \t0x%08X\n", __raw_readl(DMFC_IC_CTRL)); debug("IPU_FS_PROC_FLOW1 = \t0x%08X\n", __raw_readl(IPU_FS_PROC_FLOW1)); debug("IPU_FS_PROC_FLOW2 = \t0x%08X\n", __raw_readl(IPU_FS_PROC_FLOW2)); debug("IPU_FS_PROC_FLOW3 = \t0x%08X\n", __raw_readl(IPU_FS_PROC_FLOW3)); debug("IPU_FS_DISP_FLOW1 = \t0x%08X\n", __raw_readl(IPU_FS_DISP_FLOW1)); }
void ipu_cpmem_set_high_priority(struct ipuv3_channel *channel) { struct ipu_soc *ipu = channel->ipu; struct ipu_ch_param __iomem *p = ipu_get_cpmem(channel); u32 val; if (ipu->ipu_type == IPUV3EX) ipu_ch_param_write_field(p, IPU_FIELD_ID, 1); val = ipu_idmac_read(ipu, IDMAC_CHA_PRI(channel->num)); val |= 1 << (channel->num % 32); ipu_idmac_write(ipu, val, IDMAC_CHA_PRI(channel->num)); };
/* * This function is called by the driver framework to initialize the IPU * hardware. * * @param dev The device structure for the IPU passed in by the * driver framework. * * @return Returns 0 on success or negative error code on error */ int ipu_probe(void) { unsigned long ipu_base; #if defined CONFIG_MX51 u32 temp; u32 *reg_hsc_mcd = (u32 *)MIPI_HSC_BASE_ADDR; u32 *reg_hsc_mxt_conf = (u32 *)(MIPI_HSC_BASE_ADDR + 0x800); __raw_writel(0xF00, reg_hsc_mcd); /* CSI mode reserved*/ temp = __raw_readl(reg_hsc_mxt_conf); __raw_writel(temp | 0x0FF, reg_hsc_mxt_conf); temp = __raw_readl(reg_hsc_mxt_conf); __raw_writel(temp | 0x10000, reg_hsc_mxt_conf); #endif ipu_base = IPU_CTRL_BASE_ADDR; ipu_cpmem_base = (u32 *)(ipu_base + IPU_CPMEM_REG_BASE); ipu_dc_tmpl_reg = (u32 *)(ipu_base + IPU_DC_TMPL_REG_BASE); g_pixel_clk[0] = &pixel_clk[0]; g_pixel_clk[1] = &pixel_clk[1]; g_ipu_clk = &ipu_clk; debug("ipu_clk = %u\n", clk_get_rate(g_ipu_clk)); g_ldb_clk = &ldb_clk; debug("ldb_clk = %u\n", clk_get_rate(g_ldb_clk)); ipu_reset(); clk_set_parent(g_pixel_clk[0], g_ipu_clk); clk_set_parent(g_pixel_clk[1], g_ipu_clk); clk_enable(g_ipu_clk); g_di_clk[0] = NULL; g_di_clk[1] = NULL; __raw_writel(0x807FFFFF, IPU_MEM_RST); while (__raw_readl(IPU_MEM_RST) & 0x80000000) ; ipu_init_dc_mappings(); __raw_writel(0, IPU_INT_CTRL(5)); __raw_writel(0, IPU_INT_CTRL(6)); __raw_writel(0, IPU_INT_CTRL(9)); __raw_writel(0, IPU_INT_CTRL(10)); /* DMFC Init */ ipu_dmfc_init(DMFC_NORMAL, 1); /* Set sync refresh channels as high priority */ __raw_writel(0x18800000L, IDMAC_CHA_PRI(0)); /* Set MCU_T to divide MCU access window into 2 */ __raw_writel(0x00400000L | (IPU_MCU_T_DEFAULT << 18), IPU_DISP_GEN); clk_disable(g_ipu_clk); return 0; }
/* * This function is called by the driver framework to initialize the IPU * hardware. * * @param dev The device structure for the IPU passed in by the * driver framework. * * @return Returns 0 on success or negative error code on error */ int ipu_probe(int di, ipu_di_clk_parent_t di_clk_parent, int di_clk_val) { unsigned long ipu_base; #if defined(CONFIG_MXC_HSC) u32 temp; u32 *reg_hsc_mcd = (u32 *)MIPI_HSC_BASE_ADDR; u32 *reg_hsc_mxt_conf = (u32 *)(MIPI_HSC_BASE_ADDR + 0x800); __raw_writel(0xF00, reg_hsc_mcd); /* CSI mode reserved*/ temp = __raw_readl(reg_hsc_mxt_conf); __raw_writel(temp | 0x0FF, reg_hsc_mxt_conf); temp = __raw_readl(reg_hsc_mxt_conf); __raw_writel(temp | 0x10000, reg_hsc_mxt_conf); #endif ipu_base = IPU_CTRL_BASE_ADDR; ipu_cpmem_base = (u32 *)(ipu_base + IPU_CPMEM_REG_BASE); ipu_dc_tmpl_reg = (u32 *)(ipu_base + IPU_DC_TMPL_REG_BASE); ipu_csi_reg[0] = (u32 *)(ipu_base + IPU_CSI0_REG_BASE); ipu_csi_reg[1] = (u32 *)(ipu_base + IPU_CSI1_REG_BASE); ipu_smfc_reg = (u32 *)(ipu_base + IPU_SMFC_REG_BASE); ipu_ic_reg = (u32*)(ipu_base + IPU_IC_REG_BASE); g_pixel_clk[0] = &pixel_clk[0]; g_pixel_clk[1] = &pixel_clk[1]; g_di_clk[0] = &di_clk[0]; g_di_clk[1] = &di_clk[1]; g_di_clk[di]->rate = di_clk_val; g_ipu_clk = &ipu_clk; //printf("ipu_clk = %u\n", clk_get_rate(g_ipu_clk)); ipu_reset(); if (di_clk_parent == DI_PCLK_LDB) { clk_set_parent(g_pixel_clk[di], g_di_clk[di]); } else { clk_set_parent(g_pixel_clk[0], g_ipu_clk); // clk_set_parent(g_pixel_clk[1], g_ipu_clk); } clk_enable(g_ipu_clk); __raw_writel(0x807FFFFF, IPU_MEM_RST); while (__raw_readl(IPU_MEM_RST) & 0x80000000) ; ipu_init_dc_mappings(); __raw_writel(0, IPU_INT_CTRL(5)); __raw_writel(0, IPU_INT_CTRL(6)); __raw_writel(0, IPU_INT_CTRL(9)); __raw_writel(0, IPU_INT_CTRL(10)); /* DMFC Init */ ipu_dmfc_init(DMFC_NORMAL, 1); /* Set sync refresh channels as high priority */ __raw_writel(0x18900000L, IDMAC_CHA_PRI(0)); /* Set MCU_T to divide MCU access window into 2 */ __raw_writel(0x00400000L | (IPU_MCU_T_DEFAULT << 18), IPU_DISP_GEN); clk_disable(g_ipu_clk); return 0; }