/**
* Main entry point for the AMD_INIT_RESET function.
*
* This entry point is responsible for establishing the HT links to the program
* ROM and for performing basic processor initialization.
*
* @param[in,out] ResetParams Required input parameters for the AMD_INIT_RESET
* entry point.
*
* @return Aggregated status across all internal AMD reset calls invoked.
*
*/
AGESA_STATUS
AmdInitReset (
IN OUT AMD_RESET_PARAMS *ResetParams
)
{
AGESA_STATUS AgesaStatus;
AGESA_STATUS CalledAgesaStatus;
WARM_RESET_REQUEST Request;
UINT8 PrevRequestBit;
UINT8 PrevStateBits;
// Init Debug Print function
IDS_HDT_CONSOLE_INIT (&ResetParams->StdHeader);
IDS_HDT_CONSOLE (MAIN_FLOW, "\n*** %s ***\n\n", &UserOptions.VersionString);
IDS_HDT_CONSOLE_DEBUG_CODE (
{
extern CHAR8 *BldOptDebugOutput[];
UINT8 i;
for (i = 0; BldOptDebugOutput[i] != NULL; i++) {
IDS_HDT_CONSOLE (MAIN_FLOW, "\t%s\n", BldOptDebugOutput[i]);
}
}
)
/**
* Main entry point for the AMD_INIT_ENV function.
*
* This entry point is responsible for copying the heap contents from the
* temp RAM area to main memory.
*
* @param[in,out] EnvParams Required input parameters for the AMD_INIT_ENV
* entry point.
*
* @return Aggregated status across all internal AMD env calls invoked.
*
*/
AGESA_STATUS
AmdInitEnv (
IN OUT AMD_ENV_PARAMS *EnvParams
)
{
AGESA_STATUS AgesaStatus;
AGESA_STATUS AmdInitEnvStatus;
AGESA_TESTPOINT (TpIfAmdInitEnvEntry, &EnvParams->StdHeader);
ASSERT (EnvParams != NULL);
AmdInitEnvStatus = AGESA_SUCCESS;
//Copy Temp Ram heap content to Main Ram
AgesaStatus = CopyHeapToMainRamAtPost (&(EnvParams->StdHeader));
if (AgesaStatus > AmdInitEnvStatus) {
AmdInitEnvStatus = AgesaStatus;
}
EnvParams->StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
EnvParams->StdHeader.HeapBasePtr = HeapGetBaseAddress (&EnvParams->StdHeader);
// Any heap allocate/deallocate/locate buffer should be used after heap is rebuilt from here.
// After persistent heaps are transferred and rebuilt, HeapLocateBuffer can start to be used in IDS hook.
//Heap have been relocated, so Debug Print need be init again to get new address
IDS_PERF_TIMESTAMP (TP_BEGINPROCAMDINITENV, &EnvParams->StdHeader);
IDS_HDT_CONSOLE_INIT (&EnvParams->StdHeader);
IDS_HDT_CONSOLE (MAIN_FLOW, "Heap transfer End\n");
IDS_HDT_CONSOLE (MAIN_FLOW, "AmdInitEnv: Start\n\n");
IDS_OPTION_HOOK (IDS_PLATFORMCFG_OVERRIDE, &EnvParams->PlatformConfig, &(EnvParams->StdHeader));
IDS_OPTION_HOOK (IDS_BEFORE_PCI_INIT, EnvParams, &(EnvParams->StdHeader));
AgesaStatus = S3ScriptInit (&EnvParams->StdHeader);
if (AgesaStatus > AmdInitEnvStatus) {
AmdInitEnvStatus = AgesaStatus;
}
IDS_PERF_TIMESTAMP (TP_BEGININITENV, &EnvParams->StdHeader);
AgesaStatus = BldoptFchFunction.InitEnv (EnvParams);
AmdInitEnvStatus = (AgesaStatus > AmdInitEnvStatus) ? AgesaStatus : AmdInitEnvStatus;
IDS_PERF_TIMESTAMP (TP_ENDINITENV, &EnvParams->StdHeader);
IDS_PERF_TIMESTAMP (TP_BEGINGNBINITATENV, &EnvParams->StdHeader);
AgesaStatus = GnbInitAtEnv (EnvParams);
if (AgesaStatus > AmdInitEnvStatus) {
AmdInitEnvStatus = AgesaStatus;
}
IDS_PERF_TIMESTAMP (TP_ENDGNBINITATENV, &EnvParams->StdHeader);
AGESA_TESTPOINT (TpIfAmdInitEnvExit, &EnvParams->StdHeader);
IDS_HDT_CONSOLE (MAIN_FLOW, "\nAmdInitEnv: End\n");
IDS_PERF_TIMESTAMP (TP_ENDPROCAMDINITENV, &EnvParams->StdHeader);
IDS_HDT_CONSOLE_FLUSH_BUFFER (&EnvParams->StdHeader);
return AmdInitEnvStatus;
}
/**
* Main entry point for the AMD_INIT_RESET function.
*
* This entry point is responsible for establishing the HT links to the program
* ROM and for performing basic processor initialization.
*
* @param[in,out] ResetParams Required input parameters for the AMD_INIT_RESET
* entry point.
*
* @return Aggregated status across all internal AMD reset calls invoked.
*
*/
AGESA_STATUS
AmdInitReset (
IN OUT AMD_RESET_PARAMS *ResetParams
)
{
AGESA_STATUS AgesaStatus;
AGESA_STATUS CalledAgesaStatus;
WARM_RESET_REQUEST Request;
UINT8 PrevRequestBit;
UINT8 PrevStateBits;
AgesaStatus = AGESA_SUCCESS;
// Setup ROM execution cache
CalledAgesaStatus = AllocateExecutionCache (&ResetParams->StdHeader, &ResetParams->CacheRegion[0]);
if (CalledAgesaStatus > AgesaStatus) {
AgesaStatus = CalledAgesaStatus;
}
// IDS_EXTENDED_HOOK (IDS_INIT_RESET_BEFORE, NULL, NULL, &ResetParams->StdHeader);
// Init Debug Print function
IDS_HDT_CONSOLE_INIT (&ResetParams->StdHeader);
IDS_HDT_CONSOLE (MAIN_FLOW, "\nAmdInitReset: Start\n\n");
IDS_HDT_CONSOLE (MAIN_FLOW, "\n*** %s ***\n\n", (CHAR8 *)&UserOptions.VersionString);
AGESA_TESTPOINT (TpIfAmdInitResetEntry, &ResetParams->StdHeader);
ASSERT (ResetParams != NULL);
PrevRequestBit = FALSE;
PrevStateBits = WR_STATE_COLD;
if (IsBsp (&ResetParams->StdHeader, &AgesaStatus)) {
CalledAgesaStatus = BldoptFchFunction.InitReset (ResetParams);
AgesaStatus = (CalledAgesaStatus > AgesaStatus) ? CalledAgesaStatus : AgesaStatus;
}
// If a previously requested warm reset cannot be triggered in the
// current stage, store the previous state of request and reset the
// request struct to the current post stage
GetWarmResetFlag (&ResetParams->StdHeader, &Request);
if (Request.RequestBit == TRUE) {
if (Request.StateBits >= Request.PostStage) {
PrevRequestBit = Request.RequestBit;
PrevStateBits = Request.StateBits;
Request.RequestBit = FALSE;
Request.StateBits = Request.PostStage - 1;
SetWarmResetFlag (&ResetParams->StdHeader, &Request);
}
}
// Initialize the PCI MMIO access mechanism
InitializePciMmio (&ResetParams->StdHeader);
// Initialize Hyper Transport Registers
if (HtOptionInitReset.HtInitReset != NULL) {
IDS_HDT_CONSOLE (MAIN_FLOW, "HtInitReset: Start\n");
CalledAgesaStatus = HtOptionInitReset.HtInitReset (&ResetParams->StdHeader, &ResetParams->HtConfig);
IDS_HDT_CONSOLE (MAIN_FLOW, "HtInitReset: End\n");
if (CalledAgesaStatus > AgesaStatus) {
AgesaStatus = CalledAgesaStatus;
}
}
// Warm Reset, should be at the end of AmdInitReset
GetWarmResetFlag (&ResetParams->StdHeader, &Request);
// If a warm reset is requested in the current post stage, trigger the
// warm reset and ignore the previous request
if (Request.RequestBit == TRUE) {
if (Request.StateBits < Request.PostStage) {
AgesaDoReset (WARM_RESET_WHENEVER, &ResetParams->StdHeader);
}
} else {
// Otherwise, if there's a previous request, restore it
// so that the subsequent post stage can trigger the warm reset
if (PrevRequestBit == TRUE) {
Request.RequestBit = PrevRequestBit;
Request.StateBits = PrevStateBits;
SetWarmResetFlag (&ResetParams->StdHeader, &Request);
}
}
// Check for Cache As Ram Corruption
IDS_CAR_CORRUPTION_CHECK (&ResetParams->StdHeader);
IDS_HDT_CONSOLE (MAIN_FLOW, "\nAmdInitReset: End\n\n");
AGESA_TESTPOINT (TpIfAmdInitResetExit, &ResetParams->StdHeader);
return AgesaStatus;
}
/**
* Main entry point for the AMD_S3LATE_RESTORE function.
*
* This entry point is responsible for restoring saved registers and preparing the
* silicon components for OS restart.
*
* @param[in,out] S3LateParams Required input parameters for the AMD_S3LATE_RESTORE
* entry point.
*
* @return Aggregated status across all internal AMD S3 late restore calls invoked.
*
*/
AGESA_STATUS
AmdS3LateRestore (
IN OUT AMD_S3LATE_PARAMS *S3LateParams
)
{
UINT8 *BufferPointer;
VOID *OrMaskPtr;
VOID *LateContextPtr;
AGESA_STATUS ReturnStatus;
AGESA_STATUS CalledStatus;
AGESA_TESTPOINT (TpIfAmdS3LateRestoreEntry, &S3LateParams->StdHeader);
ReturnStatus = AGESA_SUCCESS;
ASSERT (S3LateParams != NULL);
BufferPointer = (UINT8 *) S3LateParams->S3DataBlock.VolatileStorage;
S3LateParams->StdHeader.HeapBasePtr = (UINT64) (intptr_t) ((UINT8 *)(&BufferPointer[(((S3_VOLATILE_STORAGE_HEADER *) S3LateParams->S3DataBlock.VolatileStorage)->HeapOffset)]));
ASSERT (S3LateParams->StdHeader.HeapBasePtr != 0);
IDS_HDT_CONSOLE_INIT (&S3LateParams->StdHeader);
IDS_HDT_CONSOLE (MAIN_FLOW, "AmdS3LateRestore: Start\n\n");
IDS_OPTION_HOOK (IDS_PLATFORMCFG_OVERRIDE, &S3LateParams->PlatformConfig, &S3LateParams->StdHeader);
IDS_OPTION_HOOK (IDS_BEFORE_S3_RESTORE, S3LateParams, &(S3LateParams->StdHeader));
if (((S3_VOLATILE_STORAGE_HEADER *) S3LateParams->S3DataBlock.VolatileStorage)->RegisterDataSize != 0) {
LateContextPtr = &BufferPointer[((S3_VOLATILE_STORAGE_HEADER *) S3LateParams->S3DataBlock.VolatileStorage)->RegisterDataOffset];
// Restore registers before exiting self refresh
RestorePreESRContext (&OrMaskPtr,
LateContextPtr,
S3_LATE_RESTORE,
&S3LateParams->StdHeader);
// Restore registers after exiting self refresh
RestorePostESRContext (OrMaskPtr,
LateContextPtr,
S3_LATE_RESTORE,
&S3LateParams->StdHeader);
}
// Dispatch any features needing to run at this time point
IDS_HDT_CONSOLE (CPU_TRACE, " Dispatch CPU features at S3 late restore end\n");
CalledStatus = DispatchCpuFeatures (CPU_FEAT_S3_LATE_RESTORE_END,
&S3LateParams->PlatformConfig,
&S3LateParams->StdHeader);
if (CalledStatus > ReturnStatus) {
ReturnStatus = CalledStatus;
}
CalledStatus = S3ScriptRestore (&S3LateParams->StdHeader);
if (CalledStatus > ReturnStatus) {
ReturnStatus = CalledStatus;
}
IDS_OPTION_HOOK (IDS_AFTER_S3_RESTORE, S3LateParams, &S3LateParams->StdHeader);
AGESA_TESTPOINT (TpIfAmdS3LateRestoreExit, &S3LateParams->StdHeader);
IDS_HDT_CONSOLE (MAIN_FLOW, "\nAmdS3LateRestore: End\n\n");
IDS_HDT_CONSOLE_S3_EXIT (&S3LateParams->StdHeader);
return ReturnStatus;
}
