static bool T3900_power_on(void)
{
DPRINTK("T3900_power_on\n");
if (g_bPowerOn) {
return true;
} else {
g_pStChInfo = vmalloc(sizeof(ST_SUBCH_INFO));
if (g_pStChInfo == NULL) {
return false;
} else {
__control_gpio(true);
if (INTERFACE_INIT(TDMB_I2C_ID80) != INC_SUCCESS) {
__control_gpio(false);
vfree(g_pStChInfo);
g_pStChInfo = NULL;
return false;
} else {
__control_irq(true);
g_bPowerOn = true;
return true;
}
}
}
}
int8 tunerbb_drv_lg2102_init(void)
{
INC_UINT8 nRet;
//tunerbb_drv_lg2102_rw_test( ); // for test
#if defined(STREAM_SLAVE_PARALLEL_UPLOAD) // if EBI interface
m_ucCommandMode = INC_EBI_CTRL;
m_ucUploadMode = STREAM_UPLOAD_SLAVE_PARALLEL;
#elif defined(STREAM_TS_UPLOAD) /* if TSIF interface */
m_ucCommandMode = INC_I2C_CTRL;
m_ucUploadMode = STREAM_UPLOAD_TS;
#elif defined(STREAM_SPI_UPLOAD) // if SPI interface
m_ucCommandMode = INC_SPI_CTRL;
m_ucUploadMode = STREAM_UPLOAD_SPI;
#endif
m_ucPLL_Mode = INPUT_CLOCK_24576KHZ;
m_ucMPI_CS_Active = INC_ACTIVE_HIGH;
m_ucMPI_CLK_Active = INC_ACTIVE_LOW;
m_unIntCtrl = (INC_INTERRUPT_POLARITY_LOW| \
INC_INTERRUPT_PULSE | \
INC_INTERRUPT_AUTOCLEAR_ENABLE| \
(INC_INTERRUPT_PULSE_COUNT&INC_INTERRUPT_PULSE_COUNT_MASK));
nRet = INTERFACE_INIT(TDMB_RFBB_DEV_ADDR);
if(nRet!=INC_SUCCESS)
{
printk("[LG2102] INTERFACE_INIT() = (%d)\n", nRet);
//return 1; // NOT_OK
}
return nRet;
}
static bool t3900_power_on(void)
{
DPRINTK("t3900_power_on\n");
if (t3900_pwr_on) {
return true;
} else {
st_ch_info = vmalloc(sizeof(struct ST_SUBCH_INFO));
if (st_ch_info == NULL) {
return false;
} else {
tdmb_control_gpio(true);
if (INTERFACE_INIT(TDMB_I2C_ID80) != INC_SUCCESS) {
tdmb_control_gpio(false);
vfree(st_ch_info);
st_ch_info = NULL;
return false;
} else {
tdmb_control_irq(true);
t3900_pwr_on = true;
return true;
}
}
}
}
int8 tunerbb_drv_t39fx_init(void)
{
INC_UINT8 nRet;
//tunerbb_drv_t39fx_rw_test( ); // for test
#if defined(STREAM_SLAVE_PARALLEL_UPLOAD) // if EBI interface
m_ucCommandMode = INC_EBI_CTRL;
m_ucUploadMode = STREAM_UPLOAD_SLAVE_PARALLEL;
#elif defined(STREAM_TS_UPLOAD) /* if TSIF interface */
m_ucCommandMode = INC_I2C_CTRL;
m_ucUploadMode = STREAM_UPLOAD_TS;
#elif defined(STREAM_SPI_UPLOAD) // if SPI interface
m_ucCommandMode = INC_SPI_CTRL;
m_ucUploadMode = STREAM_UPLOAD_SPI;
#endif
/* T39FX Inner X-tal clock is 24.576MHz */
m_ucPLL_Mode = INPUT_CLOCK_24576KHZ;
m_ucMPI_CS_Active = INC_ACTIVE_HIGH;
m_ucMPI_CLK_Active = INC_ACTIVE_LOW;
m_unIntCtrl = (INC_INTERRUPT_ACTIVE_POLALITY_LOW| \
INC_INTERRUPT_PULSE | \
INC_INTERRUPT_AUTOCLEAR_ENABLE| \
(INC_INTERRUPT_PULSE_COUNT&INC_INTERRUPT_PULSE_COUNT_MASK));
#if 0 /* ISR Level, ISR Auto Clear disable */
m_unIntCtrl = (INC_INTERRUPT_ACTIVE_POLALITY_LOW | \
INC_INTERRUPT_LEVEL | \
INC_INTERRUPT_AUTOCLEAR_DISABLE| \
(INC_INTERRUPT_PULSE_COUNT & INC_INTERRUPT_PULSE_COUNT_MASK));
#endif
nRet = INTERFACE_INIT(TDMB_RFBB_DEV_ADDR);
if(nRet != INC_SUCCESS)
{
printk("[T39fx] INTERFACE_INIT Error = (%d)\n", nRet);
}
return nRet;
}
