static int plt_sd_pad_change(unsigned int index, int clock)
{
/* LOW speed is the default state of SD pads */
static enum sd_pad_mode pad_mode = SD_PAD_MODE_LOW_SPEED;
int i = (index - 3) * SD_SPEED_CNT;
// pr_info("%s: index %d, clock %d\n", __func__, index, clock);
if (index != 3) {
pr_err("%s:no such SD host controller index %d\n", __func__, index);
return -EINVAL;
}
if (clock > 100000000) {
if (pad_mode == SD_PAD_MODE_HIGH_SPEED)
return 0;
pad_mode = SD_PAD_MODE_HIGH_SPEED;
i += _200MHZ;
} else if (clock > 52000000) {
if (pad_mode == SD_PAD_MODE_MED_SPEED)
return 0;
pad_mode = SD_PAD_MODE_MED_SPEED;
i += _100MHZ;
} else {
if (pad_mode == SD_PAD_MODE_LOW_SPEED)
return 0;
pad_mode = SD_PAD_MODE_LOW_SPEED;
i += _50MHZ;
}
return IOMUX_SETUP(sd_pads[i]);
}
static int plt_sd_pad_change(unsigned int index, int clock)
{
/* LOW speed is the default state of SD pads */
static enum sd_pad_mode pad_mode = SD_PAD_MODE_LOW_SPEED;
int i = (index - 1) * SD_SPEED_CNT;
if ((index < 1) || (index > 3)) {
printk(KERN_ERR "no such SD host controller index %d\n", index);
return -EINVAL;
}
if (clock > 100000000) {
if (pad_mode == SD_PAD_MODE_HIGH_SPEED)
return 0;
pad_mode = SD_PAD_MODE_HIGH_SPEED;
i += _200MHZ;
} else if (clock > 52000000) {
if (pad_mode == SD_PAD_MODE_MED_SPEED)
return 0;
pad_mode = SD_PAD_MODE_MED_SPEED;
i += _100MHZ;
} else {
if (pad_mode == SD_PAD_MODE_LOW_SPEED)
return 0;
pad_mode = SD_PAD_MODE_LOW_SPEED;
i += _50MHZ;
}
return IOMUX_SETUP(sd_pads[i]);
}
/*!
* Board specific initialization.
*/
static void __init mx6_board_init(void)
{
int ret = gpio_request_array(mx6_init_gpios,
ARRAY_SIZE(mx6_init_gpios));
if (ret) {
printk(KERN_ERR "%s gpio_request_array failed("
"%d) for mx6_init_gpios\n", __func__, ret);
}
IOMUX_SETUP(common_pads);
gp_reg_id = dvfscore_data.reg_id;
soc_reg_id = dvfscore_data.soc_id;
pu_reg_id = dvfscore_data.pu_id;
imx6q_add_imx_uart(0, NULL);
imx6q_add_imx_uart(1, NULL);
imx6q_add_imx_uart(2, &uart2_data);
imx6q_add_imx_uart(3, NULL);
imx6q_add_imx_snvs_rtc();
/* SPI */
imx6q_add_ecspi(0, &mx6_spi_data);
spi_device_init();
imx6q_add_anatop_thermal_imx(1, &mx6_anatop_thermal_data);
imx6_init_fec(fec_data);
imx6q_add_pm_imx(0, &mx6_pm_data);
imx6q_add_sdhci_usdhc_imx(3, &mx6_sd4_data);
imx6_init_usb();
platform_device_register(&mx6_vmmc_reg_devices);
imx6q_add_otp();
imx6q_add_viim();
imx6q_add_imx2_wdt(0, NULL);
imx6q_add_dma();
imx6q_add_dvfs_core(&dvfscore_data);
add_device_buttons();
imx6q_add_busfreq();
imx6q_add_flexcan0(&flexcan0_tja1040_pdata);
imx6q_add_pcie(&plat_pcie);
imx6q_add_perfmon(0);
imx6q_add_perfmon(1);
imx6q_add_perfmon(2);
// regulator_has_full_constraints();
}
static void ov5640_mipi_camera_io_init(void)
{
IOMUX_SETUP(mipi_pads);
pr_info("%s\n", __func__);
mipi_pwm = pwm_request(2, "mipi_clock");
if (IS_ERR(mipi_pwm)) {
pr_err("unable to request PWM for mipi_clock\n");
} else {
unsigned period = 1000/22;
pr_info("got pwm for mipi_clock\n");
pwm_config(mipi_pwm, period >> 1, period);
pwm_enable(mipi_pwm);
}
camera_reset(IMX_GPIO_NR(6, 9), 1, IMX_GPIO_NR(2, 5), IMX_GPIO_NR(6, 11));
/* for mx6dl, mipi virtual channel 1 connect to csi 1*/
if (cpu_is_mx6dl())
mxc_iomux_set_gpr_register(13, 3, 3, 1);
}
/*
* GPIO_6 GPIO[1]:6 (ov5642) - J5 - CSI0 power down
* GPIO_8 GPIO[1]:8 (ov5642) - J5 - CSI0 reset
* NANDF_CS0 GPIO[6]:11 (ov5642) - J5 - reset
* SD1_DAT0 GPIO[1]:16 (ov5642) - J5 - GP
*/
static void ov5642_io_init(void)
{
IOMUX_SETUP(csi0_sensor_pads);
camera_reset(GP_CSI0_PWN, 1, GP_CSI0_RST, IMX_GPIO_NR(6, 11));
/* For MX6Q GPR1 bit19 and bit20 meaning:
* Bit19: 0 - Enable mipi to IPU1 CSI0
* virtual channel is fixed to 0
* 1 - Enable parallel interface to IPU1 CSI0
* Bit20: 0 - Enable mipi to IPU2 CSI1
* virtual channel is fixed to 3
* 1 - Enable parallel interface to IPU2 CSI1
* IPU1 CSI1 directly connect to mipi csi2,
* virtual channel is fixed to 1
* IPU2 CSI0 directly connect to mipi csi2,
* virtual channel is fixed to 2
*/
if (cpu_is_mx6q())
mxc_iomux_set_gpr_register(1, 19, 1, 1);
else
mxc_iomux_set_gpr_register(13, 0, 3, 4);
}
/*!
* Board specific initialization.
*/
static void __init board_init(void)
{
int i, j;
struct clk *clko2;
struct clk *new_parent;
int rate;
int ret = gpio_request_array(board_gpios,
ARRAY_SIZE(board_gpios));
IOMUX_SETUP(common_pads);
if (ret) {
printk(KERN_ERR "%s gpio_request_array failed("
"%d) for board_gpios\n", __func__, ret);
}
printk(KERN_ERR "------------ Board type H\n");
gp_reg_id = plat_dvfscore.reg_id;
soc_reg_id = plat_dvfscore.soc_id;
pu_reg_id = plat_dvfscore.pu_id;
imx6q_add_imx_uart(0, NULL);
imx6q_add_imx_uart(1, NULL);
imx6q_add_imx_uart(2, &plat_uart2);
imx6q_add_ipuv3(0, &plat_ipu[0]);
if (cpu_is_mx6q()) {
imx6q_add_ipuv3(1, &plat_ipu[1]);
j = ARRAY_SIZE(plat_fb);
} else {
j = ARRAY_SIZE(plat_fb) / 2;
plat_ldb.ipu_id = 0;
plat_ldb.disp_id = 1;
plat_ldb.sec_ipu_id = 0;
plat_ldb.sec_disp_id = 0;
}
for (i = 0; i < j; i++)
fb_dev[i] = imx6q_add_ipuv3fb(i, &plat_fb[i]);
imx6q_add_vdoa();
imx6q_add_lcdif(&plat_lcdif);
imx6q_add_ldb(&plat_ldb);
imx6q_add_v4l2_output(0);
imx6q_add_v4l2_capture(0, &plat_capture);
imx6q_add_mipi_csi2(&plat_mipi_csi2);
imx6q_add_imx_snvs_rtc();
if (1 == caam_enabled)
imx6q_add_imx_caam();
imx6q_add_imx_i2c(0, &plat_i2c);
imx6q_add_imx_i2c(2, &plat_i2c);
i2c_register_board_info(0, mxc_i2c0_board_info,
ARRAY_SIZE(mxc_i2c0_board_info));
mxc_register_device(&platdev_i2c0mux, &plat_i2c0mux);
i2c_register_board_info(3, mxc_i2c3_board_info,
ARRAY_SIZE(mxc_i2c3_board_info));
i2c_register_board_info(4, mxc_i2c4_board_info,
ARRAY_SIZE(mxc_i2c4_board_info));
i2c_register_board_info(5, mxc_i2c5_board_info,
ARRAY_SIZE(mxc_i2c5_board_info));
mxc_register_device(&platdev_i2c2mux, &plat_i2c2mux);
i2c_register_board_info(6, mxc_i2c6_board_info,
ARRAY_SIZE(mxc_i2c6_board_info));
i2c_register_board_info(7, mxc_i2c7_board_info,
ARRAY_SIZE(mxc_i2c7_board_info));
/* SPI */
imx6q_add_ecspi(0, &plat_spi);
spi_device_init();
imx6q_add_anatop_thermal_imx(1, &plat_anatop_thermal);
imx6_init_fec(plat_fec);
imx6q_add_pm_imx(0, &plat_pm);
imx6q_add_sdhci_usdhc_imx(2, &plat_sd3);
imx6q_add_sdhci_usdhc_imx(3, &plat_sd4);
imx_add_viv_gpu(&imx6_gpu_data, &plat_gpu);
init_usb();
if (cpu_is_mx6q())
imx6q_add_ahci(0, &plat_sata);
imx6q_add_vpu();
init_audio();
platform_device_register(&platdev_vmmc_reg_devices);
plat_asrc.asrc_core_clk = clk_get(NULL, "asrc_clk");
plat_asrc.asrc_audio_clk = clk_get(NULL, "asrc_serial_clk");
imx6q_add_asrc(&plat_asrc);
/* release USB Hub reset */
gpio_set_value(GP_USB_HUB_RESET, 1);
imx6q_add_mxc_pwm(0); /* RGB backlight */
imx6q_add_mxc_pwm(1); /* Buzzer */
imx6q_add_mxc_pwm(2); /* LVDS1 baclight */
imx6q_add_mxc_pwm(3); /* LVDS0 baclight */
imx6q_add_mxc_pwm_backlight(0, &plat_di0_backlight);
imx6q_add_mxc_pwm_backlight(2, &plat_lvds1_backlight);
imx6q_add_mxc_pwm_backlight(3, &plat_lvds0_backlight);
imx6q_add_otp();
imx6q_add_viim();
imx6q_add_imx2_wdt(0, NULL);
imx6q_add_dma();
imx6q_add_dvfs_core(&plat_dvfscore);
add_device_buttons();
clko2 = clk_get(NULL, "clko2_clk");
if (IS_ERR(clko2))
pr_err("can't get CLKO2 clock.\n");
new_parent = clk_get(NULL, "osc_clk");
if (!IS_ERR(new_parent)) {
clk_set_parent(clko2, new_parent);
clk_put(new_parent);
}
rate = clk_round_rate(clko2, 24000000);
clk_set_rate(clko2, rate);
clk_enable(clko2);
pm_power_off = poweroff;
imx6q_add_busfreq();
gpio_set_value(GP_WL_EN, 1); /* momentarily enable */
gpio_set_value(GP_WL_BT_REG_EN, 1);
mdelay(2);
gpio_set_value(GP_WL_EN, 0);
gpio_set_value(GP_WL_BT_REG_EN, 0);
gpio_free(GP_WL_BT_RESET);
gpio_free(GP_WL_EN);
gpio_free(GP_WL_BT_REG_EN);
mdelay(1);
imx6q_add_sdhci_usdhc_imx(1, &plat_sd2);
platform_device_register(&platdev_vwifi_reg_devices);
platform_device_register(&platdev_leds_pwd);
imx6q_add_pcie(&plat_pcie);
imx6q_add_perfmon(0);
imx6q_add_perfmon(1);
imx6q_add_perfmon(2);
}
static void hdmi_disable_ddc_pin(void)
{
IOMUX_SETUP(i2c2_pads);
}
static void hdmi_enable_ddc_pin(void)
{
IOMUX_SETUP(hdmi_ddc_pads);
}
/*!
* Board specific initialization.
*/
static void __init board_init(void)
{
int i, j;
int ret;
struct clk *clko2;
struct clk *new_parent;
int rate;
int isn6 ;
IOMUX_SETUP(common_pads);
isn6 = is_nitrogen6w();
if (isn6) {
audio_data.ext_port = 3;
sd3_data.wp_gpio = -1 ;
IOMUX_SETUP(nitrogen6x_pads);
} else {
IOMUX_SETUP(sabrelite_pads);
}
printk(KERN_ERR "------------ Board type %s\n",
isn6 ? "Nitrogen6X/W" : "Sabre Lite");
#ifdef CONFIG_FEC_1588
/* Set GPIO_16 input for IEEE-1588 ts_clk and RMII reference clock
* For MX6 GPR1 bit21 meaning:
* Bit21: 0 - GPIO_16 pad output
* 1 - GPIO_16 pad input
*/
mxc_iomux_set_gpr_register(1, 21, 1, 1);
#endif
gp_reg_id = dvfscore_data.reg_id;
soc_reg_id = dvfscore_data.soc_id;
pu_reg_id = dvfscore_data.pu_id;
imx6q_add_imx_uart(0, NULL);
imx6q_add_imx_uart(1, NULL);
if (isn6)
imx6q_add_imx_uart(2, &mx6_arm2_uart2_data);
#if !(defined(CONFIG_MXC_CAMERA_OV5642) || defined(CONFIG_MXC_CAMERA_OV5642_MODULE))
imx6q_add_imx_uart(3, &mx6_arm2_uart3_data);
imx6q_add_imx_uart(4, &mx6_arm2_uart4_data);
#endif
if (!cpu_is_mx6q()) {
ldb_data.ipu_id = 0;
ldb_data.sec_ipu_id = 0;
}
imx6q_add_mxc_hdmi_core(&hdmi_core_data);
imx6q_add_ipuv3(0, &ipu_data[0]);
if (cpu_is_mx6q()) {
imx6q_add_ipuv3(1, &ipu_data[1]);
j = ARRAY_SIZE(fb_data);
} else {
j = (ARRAY_SIZE(fb_data) + 1) / 2;
adv7180_data.ipu = 0;
}
for (i = 0; i < j; i++)
imx6q_add_ipuv3fb(i, &fb_data[i]);
imx6q_add_vdoa();
imx6q_add_lcdif(&lcdif_data);
imx6q_add_ldb(&ldb_data);
imx6q_add_v4l2_output(0);
imx6q_add_bt656(&bt656_data);
for (i = 0; i < ARRAY_SIZE(capture_data); i++) {
if (!cpu_is_mx6q())
capture_data[i].ipu = 0;
imx6q_add_v4l2_capture(i, &capture_data[i]);
}
imx6q_add_mipi_csi2(&mipi_csi2_pdata);
imx6q_add_imx_snvs_rtc();
if (1 == caam_enabled)
imx6q_add_imx_caam();
imx6q_add_imx_i2c(0, &i2c_data);
imx6q_add_imx_i2c(1, &i2c_data);
imx6q_add_imx_i2c(2, &i2c_data);
/*
* SABRE Lite does not have an ISL1208 RTC
*/
i2c_register_board_info(0, mxc_i2c0_board_info,
isn6 ? ARRAY_SIZE(mxc_i2c0_board_info)
: ARRAY_SIZE(mxc_i2c0_board_info)-1);
i2c_register_board_info(1, mxc_i2c1_board_info,
ARRAY_SIZE(mxc_i2c1_board_info));
i2c_register_board_info(2, mxc_i2c2_board_info,
ARRAY_SIZE(mxc_i2c2_board_info));
/* SPI */
imx6q_add_ecspi(0, &spi_data);
spi_device_init();
imx6q_add_mxc_hdmi(&hdmi_data);
imx6q_add_anatop_thermal_imx(1, &anatop_thermal_data);
imx6_init_fec(fec_data);
imx6q_add_pm_imx(0, &pm_data);
imx6q_add_sdhci_usdhc_imx(2, &sd3_data);
imx6q_add_sdhci_usdhc_imx(3, &sd4_data);
imx_add_viv_gpu(&imx6_gpu_data, &imx6_gpu_pdata);
init_usb();
if (cpu_is_mx6q())
imx6q_add_ahci(0, &sata_data);
imx6q_add_vpu();
imx6_init_audio();
platform_device_register(&vmmc_reg_devices);
imx_asrc_data.asrc_core_clk = clk_get(NULL, "asrc_clk");
imx_asrc_data.asrc_audio_clk = clk_get(NULL, "asrc_serial_clk");
imx6q_add_asrc(&imx_asrc_data);
/* release USB Hub reset */
gpio_set_value(GP_USB_HUB_RESET, 1);
imx6q_add_mxc_pwm(0);
imx6q_add_mxc_pwm(1);
imx6q_add_mxc_pwm_pdata(2, &pwm3_data);
imx6q_add_mxc_pwm(3);
imx6q_add_mxc_pwm_backlight(0, &pwm1_backlight_data);
imx6q_add_mxc_pwm_backlight(3, &pwm4_backlight_data);
imx6q_add_otp();
imx6q_add_viim();
imx6q_add_imx2_wdt(0, NULL);
imx6q_add_dma();
imx6q_add_dvfs_core(&dvfscore_data);
add_device_buttons();
imx6q_add_hdmi_soc();
imx6q_add_hdmi_soc_dai();
ret = gpio_request_array(flexcan_gpios,
ARRAY_SIZE(flexcan_gpios));
if (ret) {
pr_err("failed to request flexcan1-gpios: %d\n", ret);
} else {
int ret = gpio_get_value(GP_CAN1_ERR);
if (ret == 0) {
imx6q_add_flexcan0(&flexcan0_tja1040_pdata);
pr_info("Flexcan NXP tja1040\n");
} else if (ret == 1) {
IOMUX_SETUP(mc33902_flexcan_pads);
imx6q_add_flexcan0(&flexcan0_mc33902_pdata);
pr_info("Flexcan Freescale mc33902\n");
} else {
pr_info("Flexcan gpio_get_value CAN1_ERR failed\n");
}
}
clko2 = clk_get(NULL, "clko2_clk");
if (IS_ERR(clko2))
pr_err("can't get CLKO2 clock.\n");
new_parent = clk_get(NULL, "osc_clk");
if (!IS_ERR(new_parent)) {
clk_set_parent(clko2, new_parent);
clk_put(new_parent);
}
rate = clk_round_rate(clko2, 24000000);
clk_set_rate(clko2, rate);
clk_enable(clko2);
imx6q_add_busfreq();
#ifdef CONFIG_WL12XX_PLATFORM_DATA
if (isn6) {
imx6q_add_sdhci_usdhc_imx(1, &sd2_data);
/* WL12xx WLAN Init */
if (wl12xx_set_platform_data(&n6q_wlan_data))
pr_err("error setting wl12xx data\n");
platform_device_register(&n6q_vwl1271_reg_devices);
gpio_set_value(N6_WL1271_WL_EN, 1); /* momentarily enable */
gpio_set_value(N6_WL1271_BT_EN, 1);
mdelay(2);
gpio_set_value(N6_WL1271_WL_EN, 0);
gpio_set_value(N6_WL1271_BT_EN, 0);
gpio_free(N6_WL1271_WL_EN);
gpio_free(N6_WL1271_BT_EN);
mdelay(1);
}
#endif
imx6q_add_pcie(&pcie_data);
imx6q_add_perfmon(0);
imx6q_add_perfmon(1);
imx6q_add_perfmon(2);
}
