{ GRDATA (CADL, cmdadl, DEV_RDX, 16, 0) },
{ GRDATA (CADH, cmdadh, DEV_RDX, 16, 0) },
{ GRDATA (CLNT, cmdlnt, DEV_RDX, 16, 0) },
{ GRDATA (MHDR, msghdr, DEV_RDX, 16, 0) },
{ GRDATA (MRFC, msgrfc, DEV_RDX, 16, 0) },
{ GRDATA (MXS0, msgxs0, DEV_RDX, 16, 0) },
{ GRDATA (MXS1, msgxs1, DEV_RDX, 16, 0) },
{ GRDATA (MXS2, msgxs2, DEV_RDX, 16, 0) },
{ GRDATA (MXS3, msgxs3, DEV_RDX, 16, 0) },
{ GRDATA (MSX4, msgxs4, DEV_RDX, 16, 0) },
{ GRDATA (WADL, wchadl, DEV_RDX, 16, 0) },
{ GRDATA (WADH, wchadh, DEV_RDX, 16, 0) },
{ GRDATA (WLNT, wchlnt, DEV_RDX, 16, 0) },
{ GRDATA (WOPT, wchopt, DEV_RDX, 16, 0) },
{ GRDATA (WXOPT, wchxopt, DEV_RDX, 16, 0) },
{ FLDATA (INT, IREQ (TS), INT_V_TS) },
{ FLDATA (ATTN, ts_qatn, 0) },
{ FLDATA (BOOT, ts_bcmd, 0) },
{ FLDATA (OWNC, ts_ownc, 0) },
{ FLDATA (OWNM, ts_ownm, 0) },
{ DRDATA (TIME, ts_time, 24), PV_LEFT + REG_NZ },
{ DRDATA (POS, ts_unit.pos, T_ADDR_W), PV_LEFT + REG_RO },
{ GRDATA (DEVADDR, ts_dib.ba, DEV_RDX, 32, 0), REG_HRO },
{ GRDATA (DEVVEC, ts_dib.vec, DEV_RDX, 16, 0), REG_HRO },
{ NULL }
};
MTAB ts_mod[] = {
{ MTUF_WLK, 0, "write enabled", "WRITEENABLED", NULL },
{ MTUF_WLK, MTUF_WLK, "write locked", "LOCKED", NULL },
{ MTAB_XTD|MTAB_VUN, 0, "FORMAT", "FORMAT",
*/
#define IOLN_PCLK 006
DIB pclk_dib = {
IOBA_AUTO, IOLN_PCLK, &pclk_rd, &pclk_wr,
1, IVCL (PCLK), VEC_AUTO, { NULL }
};
UNIT pclk_unit = { UDATA (&pclk_svc, UNIT_IDLE, 0) };
REG pclk_reg[] = {
{ ORDATA (CSR, pclk_csr, 16) },
{ ORDATA (CSB, pclk_csb, 16) },
{ ORDATA (CNT, pclk_ctr, 16) },
{ FLDATA (INT, IREQ (PCLK), INT_V_PCLK) },
{ FLDATA (OVFL, pclk_csr, CSR_V_ERR) },
{ FLDATA (DONE, pclk_csr, CSR_V_DONE) },
{ FLDATA (IE, pclk_csr, CSR_V_IE) },
{ FLDATA (UPDN, pclk_csr, CSR_V_UPDN) },
{ FLDATA (MODE, pclk_csr, CSR_V_MODE) },
{ FLDATA (RUN, pclk_csr, CSR_V_GO) },
{ BRDATA (TIME, xtim, 10, 32, 4), REG_NZ + PV_LEFT },
{ BRDATA (TPS, rate, 10, 32, 4), REG_NZ + PV_LEFT },
{ ORDATA (DEVADDR, pclk_dib.ba, 32), REG_HRO },
{ ORDATA (DEVVEC, pclk_dib.vec, 16), REG_HRO },
{ NULL }
};
MTAB pclk_mod[] = {
{ UNIT_LINE50HZ, UNIT_LINE50HZ, "50 Hz Line Frequency", "50HZ", &pclk_set_line },
tti_dev TTI device descriptor
tti_unit TTI unit descriptor
tti_reg TTI register list
*/
DIB tti_dib = {
IOBA_TTI, IOLN_TTI, &tti_rd, &tti_wr,
1, IVCL (TTI), VEC_TTI, { NULL }
};
UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE, 0), 0 };
REG tti_reg[] = {
{ ORDATA (BUF, tti_unit.buf, 8) },
{ ORDATA (CSR, tti_csr, 16) },
{ FLDATA (INT, IREQ (TTI), INT_V_TTI) },
{ FLDATA (ERR, tti_csr, CSR_V_ERR) },
{ FLDATA (DONE, tti_csr, CSR_V_DONE) },
{ FLDATA (IE, tti_csr, CSR_V_IE) },
{ DRDATA (POS, tti_unit.pos, T_ADDR_W), PV_LEFT },
{ DRDATA (TIME, tti_unit.wait, 24), PV_LEFT },
{ NULL }
};
MTAB tti_mod[] = {
{ TT_MODE, TT_MODE_UC, "UC", "UC", &tty_set_mode },
{ TT_MODE, TT_MODE_7B, "7b", "7B", &tty_set_mode },
{ TT_MODE, TT_MODE_8B, "8b", "8B", &tty_set_mode },
{ TT_MODE, TT_MODE_7P, "7b", NULL, NULL },
{ MTAB_XTD|MTAB_VDV, 0, "ADDRESS", NULL,
NULL, &show_addr, NULL },
{ UDATA (&rx_svc,
UNIT_FIX+UNIT_ATTABLE+UNIT_BUFABLE+UNIT_MUSTBUF, RX_SIZE) },
{ UDATA (&rx_svc,
UNIT_FIX+UNIT_ATTABLE+UNIT_BUFABLE+UNIT_MUSTBUF, RX_SIZE) }
};
REG rx_reg[] = {
{ ORDATA (RXCS, rx_csr, 16) },
{ ORDATA (RXDB, rx_dbr, 8) },
{ ORDATA (RXES, rx_esr, 8) },
{ ORDATA (RXERR, rx_ecode, 8) },
{ ORDATA (RXTA, rx_track, 8) },
{ ORDATA (RXSA, rx_sector, 8) },
{ DRDATA (STAPTR, rx_state, 3), REG_RO },
{ DRDATA (BUFPTR, rx_bptr, 7) },
{ FLDATA (INT, IREQ (RX), INT_V_RX) },
{ FLDATA (ERR, rx_csr, RXCS_V_ERR) },
{ FLDATA (TR, rx_csr, RXCS_V_TR) },
{ FLDATA (IE, rx_csr, RXCS_V_IE) },
{ FLDATA (DONE, rx_csr, RXCS_V_DONE) },
{ DRDATA (CTIME, rx_cwait, 24), PV_LEFT },
{ DRDATA (STIME, rx_swait, 24), PV_LEFT },
{ DRDATA (XTIME, rx_xwait, 24), PV_LEFT },
{ FLDATA (STOP_IOE, rx_stopioe, 0) },
{ BRDATA (SBUF, rx_buf, 8, 8, RX_NUMBY) },
{ ORDATA (DEVADDR, rx_dib.ba, 32), REG_HRO },
{ ORDATA (DEVVEC, rx_dib.vec, 16), REG_HRO },
{ NULL }
};
MTAB rx_mod[] = {
RY_SIZE) },
{ UDATA (&ry_svc, UNIT_DEN+UNIT_FIX+UNIT_ATTABLE+UNIT_BUFABLE+UNIT_MUSTBUF,
RY_SIZE) }
};
REG ry_reg[] = {
{ GRDATA (RYCS, ry_csr, DEV_RDX, 16, 0) },
{ GRDATA (RYBA, ry_ba, DEV_RDX, 16, 0) },
{ GRDATA (RYWC, ry_wc, DEV_RDX, 8, 0) },
{ GRDATA (RYDB, ry_dbr, DEV_RDX, 16, 0) },
{ GRDATA (RYES, ry_esr, DEV_RDX, 12, 0) },
{ GRDATA (RYERR, ry_ecode, DEV_RDX, 8, 0) },
{ GRDATA (RYTA, ry_track, DEV_RDX, 8, 0) },
{ GRDATA (RYSA, ry_sector, DEV_RDX, 8, 0) },
{ DRDATA (STAPTR, ry_state, 4), REG_RO },
{ FLDATA (INT, IREQ (RY), INT_V_RY) },
{ FLDATA (ERR, ry_csr, RYCS_V_ERR) },
{ FLDATA (TR, ry_csr, RYCS_V_TR) },
{ FLDATA (IE, ry_csr, RYCS_V_IE) },
{ FLDATA (DONE, ry_csr, RYCS_V_DONE) },
{ DRDATA (CTIME, ry_cwait, 24), PV_LEFT },
{ DRDATA (STIME, ry_swait, 24), PV_LEFT },
{ DRDATA (XTIME, ry_xwait, 24), PV_LEFT },
{ BRDATA (SBUF, rx2xb, 8, 8, RY_NUMBY) },
{ FLDATA (STOP_IOE, ry_stopioe, 0) },
{ URDATA (CAPAC, ry_unit[0].capac, 10, T_ADDR_W, 0,
RX_NUMDR, REG_HRO | PV_LEFT) },
{ GRDATA (DEVADDR, ry_dib.ba, DEV_RDX, 32, 0), REG_HRO },
{ GRDATA (DEVVEC, ry_dib.vec, DEV_RDX, 16, 0), REG_HRO },
{ NULL }
};
tti_dev TTI device descriptor
tti_unit TTI unit descriptor
tti_reg TTI register list
*/
DIB tti_dib = {
IOBA_TTI, IOLN_TTI, &tti_rd, &tti_wr,
1, IVCL (TTI), VEC_TTI, { NULL }
};
UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE, 0), SERIAL_IN_WAIT };
REG tti_reg[] = {
{ HRDATAD (BUF, tti_unit.buf, 8, "last data item processed") },
{ HRDATAD (CSR, tti_csr, 16, "control/status register") },
{ FLDATAD (INT, IREQ (TTI), INT_V_TTI, "interrupt pending flag") },
{ FLDATAD (DONE, tti_csr, CSR_V_DONE, "device done flag (CSR<7>)") },
{ FLDATAD (ERR, tti_csr, CSR_V_ERR, "device error flag (CSR<15>)") },
{ FLDATAD (IE, tti_csr, CSR_V_IE, "interrupt enable flag (CSR<6>)") },
{ DRDATAD (POS, tti_unit.pos, T_ADDR_W, "number of characters input"), PV_LEFT },
{ DRDATAD (TIME, tti_unit.wait, 24, "input polling interval"), PV_LEFT },
{ NULL }
};
MTAB tti_mod[] = {
{ TT_MODE, TT_MODE_UC, "UC", "UC", &tty_set_mode },
{ TT_MODE, TT_MODE_7B, "7b", "7B", &tty_set_mode },
{ TT_MODE, TT_MODE_8B, "8b", "8B", &tty_set_mode },
{ TT_MODE, TT_MODE_7P, "7b", NULL, NULL },
{ MTAB_XTD|MTAB_VDV, 0, "ADDRESS", NULL,
NULL, &show_addr, NULL },
{ GRDATAD (CADL, cmdadl, DEV_RDX, 16, 0, "command packet low address or count") },
{ GRDATAD (CADH, cmdadh, DEV_RDX, 16, 0, "command packet high address") },
{ GRDATAD (CLNT, cmdlnt, DEV_RDX, 16, 0, "command packet length") },
{ GRDATAD (MHDR, msghdr, DEV_RDX, 16, 0, "message packet header") },
{ GRDATAD (MRFC, msgrfc, DEV_RDX, 16, 0, "message packet residual frame count") },
{ GRDATAD (MXS0, msgxs0, DEV_RDX, 16, 0, "message packet extended status 0") },
{ GRDATAD (MXS1, msgxs1, DEV_RDX, 16, 0, "message packet extended status 1") },
{ GRDATAD (MXS2, msgxs2, DEV_RDX, 16, 0, "message packet extended status 2") },
{ GRDATAD (MXS3, msgxs3, DEV_RDX, 16, 0, "message packet extended status 3") },
{ GRDATAD (MSX4, msgxs4, DEV_RDX, 16, 0, "message packet extended status 4") },
{ GRDATAD (WADL, wchadl, DEV_RDX, 16, 0, "write char packet low address") },
{ GRDATAD (WADH, wchadh, DEV_RDX, 16, 0, "write char packet high address") },
{ GRDATAD (WLNT, wchlnt, DEV_RDX, 16, 0, "write char packet length") },
{ GRDATAD (WOPT, wchopt, DEV_RDX, 16, 0, "write char packet options") },
{ GRDATAD (WXOPT, wchxopt, DEV_RDX, 16, 0, "write char packet extended options") },
{ FLDATAD (INT, IREQ (TS), INT_V_TS, "interrupt pending") },
{ FLDATAD (ATTN, ts_qatn, 0, "attention message pending") },
{ FLDATAD (BOOT, ts_bcmd, 0, "boot request pending") },
{ FLDATAD (OWNC, ts_ownc, 0, "if set, tape owns command buffer") },
{ FLDATAD (OWNM, ts_ownm, 0, "if set, tape owns message buffer") },
{ DRDATAD (TIME, ts_time, 24, "delay"), PV_LEFT + REG_NZ },
{ DRDATAD (POS, ts_unit.pos, T_ADDR_W, "position"), PV_LEFT + REG_RO },
{ GRDATA (DEVADDR, ts_dib.ba, DEV_RDX, 32, 0), REG_HRO },
{ GRDATA (DEVVEC, ts_dib.vec, DEV_RDX, 16, 0), REG_HRO },
{ NULL }
};
MTAB ts_mod[] = {
{ MTUF_WLK, 0, "write enabled", "WRITEENABLED",
NULL, NULL, NULL, "Write enable tape drive" },
{ MTUF_WLK, MTUF_WLK, "write locked", "LOCKED",
lpt_reg LPT register list
*/
DIB lpt_dib = {
IOBA_LPT, IOLN_LPT, &lpt_rd, &lpt_wr,
1, IVCL(LPT), VEC_LPT, {NULL}
};
UNIT lpt_unit = {
UDATA(&lpt_svc, UNIT_SEQ + UNIT_ATTABLE + UNIT_TEXT, 0), SERIAL_OUT_WAIT
};
REG lpt_reg[] = {
{GRDATA(BUF, lpt_unit.buf, DEV_RDX, 8, 0)},
{GRDATA(CSR, lpt_csr, DEV_RDX, 16, 0)},
{FLDATA(INT, IREQ(LPT), INT_V_LPT)},
{FLDATA(ERR, lpt_csr, CSR_V_ERR)},
{FLDATA(DONE, lpt_csr, CSR_V_DONE)},
{FLDATA(IE, lpt_csr, CSR_V_IE)},
{DRDATA(POS, lpt_unit.pos, T_ADDR_W), PV_LEFT},
{DRDATA(TIME, lpt_unit.wait, 24), PV_LEFT},
{FLDATA(STOP_IOE, lpt_stopioe, 0)},
{GRDATA(DEVADDR, lpt_dib.ba, DEV_RDX, 32, 0), REG_HRO},
{GRDATA(DEVVEC, lpt_dib.vec, DEV_RDX, 16, 0), REG_HRO},
{NULL}
};
MTAB lpt_mod[] = {
{MTAB_XTD | MTAB_VDV, 004, "ADDRESS", "ADDRESS",
&set_addr, &show_addr, NULL},
{MTAB_XTD | MTAB_VDV, 0, "VECTOR", "VECTOR",
