void dump_chip_info(HAL_VERSION ChipVersion)
{
if(IS_81XXC(ChipVersion)){
DBG_871X("Chip Version Info: %s_",IS_92C_SERIAL(ChipVersion)?"CHIP_8192C":"CHIP_8188C");
}
else if(IS_92D(ChipVersion)){
DBG_871X("Chip Version Info: CHIP_8192D_");
}
else if(IS_8723_SERIES(ChipVersion)){
DBG_871X("Chip Version Info: CHIP_8723A_");
}
else if(IS_8188E(ChipVersion)){
DBG_871X("Chip Version Info: CHIP_8188E_");
}
DBG_871X("%s_",IS_NORMAL_CHIP(ChipVersion)?"Normal_Chip":"Test_Chip");
DBG_871X("%s_",IS_CHIP_VENDOR_TSMC(ChipVersion)?"TSMC":"UMC");
if(IS_A_CUT(ChipVersion)) DBG_871X("A_CUT_");
else if(IS_B_CUT(ChipVersion)) DBG_871X("B_CUT_");
else if(IS_C_CUT(ChipVersion)) DBG_871X("C_CUT_");
else if(IS_D_CUT(ChipVersion)) DBG_871X("D_CUT_");
else if(IS_E_CUT(ChipVersion)) DBG_871X("E_CUT_");
else DBG_871X("UNKNOWN_CUT(%d)_",ChipVersion.CUTVersion);
if(IS_1T1R(ChipVersion)) DBG_871X("1T1R_");
else if(IS_1T2R(ChipVersion)) DBG_871X("1T2R_");
else if(IS_2T2R(ChipVersion)) DBG_871X("2T2R_");
else DBG_871X("UNKNOWN_RFTYPE(%d)_",ChipVersion.RFType);
DBG_871X("RomVer(%d)\n",ChipVersion.ROMVer);
}
static int rtl92cu_init_sw_vars(struct ieee80211_hw *hw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
int err;
rtlpriv->dm.dm_initialgain_enable = true;
rtlpriv->dm.dm_flag = 0;
rtlpriv->dm.disable_framebursting = false;
rtlpriv->dm.thermalvalue = 0;
rtlpriv->dbg.global_debuglevel = rtlpriv->cfg->mod_params->debug;
/* for firmware buf */
rtlpriv->rtlhal.pfirmware = vzalloc(0x4000);
if (!rtlpriv->rtlhal.pfirmware) {
RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
"Can't alloc buffer for fw\n");
return 1;
}
if (IS_VENDOR_UMC_A_CUT(rtlpriv->rtlhal.version) &&
!IS_92C_SERIAL(rtlpriv->rtlhal.version)) {
rtlpriv->cfg->fw_name = "rtlwifi/rtl8192cufw_A.bin";
} else if (IS_81xxC_VENDOR_UMC_B_CUT(rtlpriv->rtlhal.version)) {
rtlpriv->cfg->fw_name = "rtlwifi/rtl8192cufw_B.bin";
} else {
rtlpriv->cfg->fw_name = "rtlwifi/rtl8192cufw_TMSC.bin";
}
/* provide name of alternative file */
rtlpriv->cfg->alt_fw_name = "rtlwifi/rtl8192cufw.bin";
pr_info("Loading firmware %s\n", rtlpriv->cfg->fw_name);
rtlpriv->max_fw_size = 0x4000;
err = request_firmware_nowait(THIS_MODULE, 1,
rtlpriv->cfg->fw_name, rtlpriv->io.dev,
GFP_KERNEL, hw, rtl_fw_cb);
return err;
}
bool rtl92cu_phy_config_rf_with_headerfile( struct ieee80211_hw *hw,
enum radio_path rfpath )
{
int i;
u32 *radioa_array_table;
u32 *radiob_array_table;
u16 radioa_arraylen, radiob_arraylen;
struct rtl_priv *rtlpriv = rtl_priv( hw );
struct rtl_hal *rtlhal = rtl_hal( rtl_priv( hw ) );
struct rtl_phy *rtlphy = &( rtlpriv->phy );
if ( IS_92C_SERIAL( rtlhal->version ) ) {
radioa_arraylen = rtlphy->hwparam_tables[RADIOA_2T].length;
radioa_array_table = rtlphy->hwparam_tables[RADIOA_2T].pdata;
radiob_arraylen = rtlphy->hwparam_tables[RADIOB_2T].length;
radiob_array_table = rtlphy->hwparam_tables[RADIOB_2T].pdata;
RT_TRACE( rtlpriv, COMP_INIT, DBG_TRACE,
"Radio_A:RTL8192CERADIOA_2TARRAY\n" );
RT_TRACE( rtlpriv, COMP_INIT, DBG_TRACE,
"Radio_B:RTL8192CE_RADIOB_2TARRAY\n" );
} else {
radioa_arraylen = rtlphy->hwparam_tables[RADIOA_1T].length;
radioa_array_table = rtlphy->hwparam_tables[RADIOA_1T].pdata;
radiob_arraylen = rtlphy->hwparam_tables[RADIOB_1T].length;
radiob_array_table = rtlphy->hwparam_tables[RADIOB_1T].pdata;
RT_TRACE( rtlpriv, COMP_INIT, DBG_TRACE,
"Radio_A:RTL8192CE_RADIOA_1TARRAY\n" );
RT_TRACE( rtlpriv, COMP_INIT, DBG_TRACE,
"Radio_B:RTL8192CE_RADIOB_1TARRAY\n" );
}
RT_TRACE( rtlpriv, COMP_INIT, DBG_TRACE, "Radio No %x\n", rfpath );
switch ( rfpath ) {
case RF90_PATH_A:
for ( i = 0; i < radioa_arraylen; i = i + 2 ) {
rtl_rfreg_delay( hw, rfpath, radioa_array_table[i],
RFREG_OFFSET_MASK,
radioa_array_table[i + 1] );
}
break;
case RF90_PATH_B:
for ( i = 0; i < radiob_arraylen; i = i + 2 ) {
rtl_rfreg_delay( hw, rfpath, radiob_array_table[i],
RFREG_OFFSET_MASK,
radiob_array_table[i + 1] );
}
break;
case RF90_PATH_C:
RT_TRACE( rtlpriv, COMP_ERR, DBG_EMERG,
"switch case not processed\n" );
break;
case RF90_PATH_D:
RT_TRACE( rtlpriv, COMP_ERR, DBG_EMERG,
"switch case not processed\n" );
break;
default:
break;
}
return true;
}
bool _rtl92cu_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
u8 configtype)
{
int i;
u32 *phy_regarray_table;
u32 *agctab_array_table;
u16 phy_reg_arraylen, agctab_arraylen;
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
struct rtl_phy *rtlphy = &(rtlpriv->phy);
if (IS_92C_SERIAL(rtlhal->version)) {
agctab_arraylen = rtlphy->hwparam_tables[AGCTAB_2T].length;
agctab_array_table = rtlphy->hwparam_tables[AGCTAB_2T].pdata;
phy_reg_arraylen = rtlphy->hwparam_tables[PHY_REG_2T].length;
phy_regarray_table = rtlphy->hwparam_tables[PHY_REG_2T].pdata;
} else {
agctab_arraylen = rtlphy->hwparam_tables[AGCTAB_1T].length;
agctab_array_table = rtlphy->hwparam_tables[AGCTAB_1T].pdata;
phy_reg_arraylen = rtlphy->hwparam_tables[PHY_REG_1T].length;
phy_regarray_table = rtlphy->hwparam_tables[PHY_REG_1T].pdata;
}
if (configtype == BASEBAND_CONFIG_PHY_REG) {
for (i = 0; i < phy_reg_arraylen; i = i + 2) {
if (phy_regarray_table[i] == 0xfe)
mdelay(50);
else if (phy_regarray_table[i] == 0xfd)
mdelay(5);
else if (phy_regarray_table[i] == 0xfc)
mdelay(1);
else if (phy_regarray_table[i] == 0xfb)
udelay(50);
else if (phy_regarray_table[i] == 0xfa)
udelay(5);
else if (phy_regarray_table[i] == 0xf9)
udelay(1);
rtl_set_bbreg(hw, phy_regarray_table[i], MASKDWORD,
phy_regarray_table[i + 1]);
udelay(1);
RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
("The phy_regarray_table[0] is %x"
" Rtl819XPHY_REGArray[1] is %x\n",
phy_regarray_table[i],
phy_regarray_table[i + 1]));
}
} else if (configtype == BASEBAND_CONFIG_AGC_TAB) {
for (i = 0; i < agctab_arraylen; i = i + 2) {
rtl_set_bbreg(hw, agctab_array_table[i], MASKDWORD,
agctab_array_table[i + 1]);
udelay(1);
RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
("The agctab_array_table[0] is "
"%x Rtl819XPHY_REGArray[1] is %x\n",
agctab_array_table[i],
agctab_array_table[i + 1]));
}
}
return true;
}
bool rtl92c_phy_mac_config(struct ieee80211_hw *hw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
bool is92c = IS_92C_SERIAL(rtlhal->version);
bool rtstatus = _rtl92c_phy_config_mac_with_headerfile(hw);
if (is92c)
rtl_write_byte(rtlpriv, 0x14, 0x71);
return rtstatus;
}
bool _rtl92ce_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
u8 configtype)
{
int i;
u32 *phy_regarray_table;
u32 *agctab_array_table;
u16 phy_reg_arraylen, agctab_arraylen;
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
if (IS_92C_SERIAL(rtlhal->version)) {
agctab_arraylen = AGCTAB_2TARRAYLENGTH;
agctab_array_table = RTL8192CEAGCTAB_2TARRAY;
phy_reg_arraylen = PHY_REG_2TARRAY_LENGTH;
phy_regarray_table = RTL8192CEPHY_REG_2TARRAY;
} else {
agctab_arraylen = AGCTAB_1TARRAYLENGTH;
agctab_array_table = RTL8192CEAGCTAB_1TARRAY;
phy_reg_arraylen = PHY_REG_1TARRAY_LENGTH;
phy_regarray_table = RTL8192CEPHY_REG_1TARRAY;
}
if (configtype == BASEBAND_CONFIG_PHY_REG) {
for (i = 0; i < phy_reg_arraylen; i = i + 2) {
rtl_addr_delay(phy_regarray_table[i]);
rtl_set_bbreg(hw, phy_regarray_table[i], MASKDWORD,
phy_regarray_table[i + 1]);
udelay(1);
RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
"The phy_regarray_table[0] is %x Rtl819XPHY_REGArray[1] is %x\n",
phy_regarray_table[i],
phy_regarray_table[i + 1]);
}
} else if (configtype == BASEBAND_CONFIG_AGC_TAB) {
for (i = 0; i < agctab_arraylen; i = i + 2) {
rtl_set_bbreg(hw, agctab_array_table[i], MASKDWORD,
agctab_array_table[i + 1]);
udelay(1);
RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
"The agctab_array_table[0] is %x Rtl819XPHY_REGArray[1] is %x\n",
agctab_array_table[i],
agctab_array_table[i + 1]);
}
}
return true;
}
static int rtl92cu_init_sw_vars(struct ieee80211_hw *hw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
int err;
char *fw_name;
rtlpriv->dm.dm_initialgain_enable = true;
rtlpriv->dm.dm_flag = 0;
rtlpriv->dm.disable_framebursting = false;
rtlpriv->dm.thermalvalue = 0;
rtlpriv->cfg->mod_params->sw_crypto =
rtlpriv->cfg->mod_params->sw_crypto;
/* for firmware buf */
rtlpriv->rtlhal.pfirmware = vzalloc(0x4000);
if (!rtlpriv->rtlhal.pfirmware) {
pr_err("Can't alloc buffer for fw\n");
return 1;
}
if (IS_VENDOR_UMC_A_CUT(rtlpriv->rtlhal.version) &&
!IS_92C_SERIAL(rtlpriv->rtlhal.version)) {
fw_name = "rtlwifi/rtl8192cufw_A.bin";
} else if (IS_81XXC_VENDOR_UMC_B_CUT(rtlpriv->rtlhal.version)) {
fw_name = "rtlwifi/rtl8192cufw_B.bin";
} else {
fw_name = "rtlwifi/rtl8192cufw_TMSC.bin";
}
/* provide name of alternative file */
rtlpriv->cfg->alt_fw_name = "rtlwifi/rtl8192cufw.bin";
pr_info("Loading firmware %s\n", fw_name);
rtlpriv->max_fw_size = 0x4000;
err = request_firmware_nowait(THIS_MODULE, 1,
fw_name, rtlpriv->io.dev,
GFP_KERNEL, hw, rtl_fw_cb);
if (err) {
vfree(rtlpriv->rtlhal.pfirmware);
rtlpriv->rtlhal.pfirmware = NULL;
}
return err;
}
VOID
odm_PathDiversityAfterLink_92C(
IN PADAPTER Adapter
)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
pPD_T pDM_PDTable = &Adapter->DM_PDTable;
u1Byte DefaultRespPath=0;
if((!(pHalData->CVID_Version==VERSION_1_BEFORE_8703B && IS_92C_SERIAL(pHalData->VersionID))) || (pHalData->PathDivCfg != 1) || (pHalData->eRFPowerState == eRfOff))
{
if(pHalData->PathDivCfg == 0)
{
RT_TRACE( COMP_INIT, DBG_LOUD, ("No ODM_TXPathDiversity()\n"));
}
else
{
RT_TRACE( COMP_INIT, DBG_LOUD, ("2T ODM_TXPathDiversity()\n"));
}
return;
}
if(!odm_IsConnected_92C(Adapter))
{
RT_TRACE( COMP_INIT, DBG_LOUD, ("ODM_TXPathDiversity(): No Connections\n"));
return;
}
if(pDM_PDTable->TrainingState == 0)
{
RT_TRACE( COMP_INIT, DBG_LOUD, ("ODM_TXPathDiversity() ==>\n"));
odm_OFDMTXPathDiversity_92C(Adapter);
if((pDM_PDTable->CCKPathDivEnable == TRUE) && (pDM_PDTable->OFDM_Pkt_Cnt < 100))
{
//RT_TRACE( COMP_INIT, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: TrainingState=0\n"));
if(pDM_PDTable->CCK_Pkt_Cnt > 300)
pDM_PDTable->Timer = 20;
else if(pDM_PDTable->CCK_Pkt_Cnt > 100)
pDM_PDTable->Timer = 60;
else
pDM_PDTable->Timer = 250;
RT_TRACE( COMP_INIT, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: timer=%d\n",pDM_PDTable->Timer));
PHY_SetBBReg(Adapter, rCCK0_AFESetting , 0x0F000000, 0x00); // RX path = PathA
pDM_PDTable->TrainingState = 1;
pHalData->RSSI_test = TRUE;
ODM_SetTimer( pDM_Odm, &pDM_Odm->CCKPathDiversityTimer, pDM_PDTable->Timer); //ms
}
else
{
pDM_PDTable->CCKTXPath = pDM_PDTable->OFDMTXPath;
DefaultRespPath = pDM_PDTable->OFDMDefaultRespPath;
RT_TRACE( COMP_INIT, DBG_LOUD, ("odm_SetRespPath_92C: Skip odm_CCKTXPathDiversity_92C, DefaultRespPath is OFDM\n"));
odm_SetRespPath_92C(Adapter, DefaultRespPath);
odm_ResetPathDiversity_92C(Adapter);
RT_TRACE( COMP_INIT, DBG_LOUD, ("ODM_TXPathDiversity() <==\n"));
}
}
else if(pDM_PDTable->TrainingState == 1)
{
//RT_TRACE( COMP_INIT, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: TrainingState=1\n"));
PHY_SetBBReg(Adapter, rCCK0_AFESetting , 0x0F000000, 0x05); // RX path = PathB
pDM_PDTable->TrainingState = 2;
ODM_SetTimer( pDM_Odm, &pDM_Odm->CCKPathDiversityTimer, pDM_PDTable->Timer); //ms
}
else
{
//RT_TRACE( COMP_INIT, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: TrainingState=2\n"));
pDM_PDTable->TrainingState = 0;
odm_CCKTXPathDiversity_92C(Adapter);
if(pDM_PDTable->OFDM_Pkt_Cnt != 0)
{
DefaultRespPath = pDM_PDTable->OFDMDefaultRespPath;
RT_TRACE( COMP_INIT, DBG_LOUD, ("odm_SetRespPath_92C: DefaultRespPath is OFDM\n"));
}
else
{
DefaultRespPath = pDM_PDTable->CCKDefaultRespPath;
RT_TRACE( COMP_INIT, DBG_LOUD, ("odm_SetRespPath_92C: DefaultRespPath is CCK\n"));
}
odm_SetRespPath_92C(Adapter, DefaultRespPath);
odm_ResetPathDiversity_92C(Adapter);
RT_TRACE( COMP_INIT, DBG_LOUD, ("ODM_TXPathDiversity() <==\n"));
}
}
BOOLEAN
ODM_PathDiversityBeforeLink92C(
//IN PADAPTER Adapter
IN PDM_ODM_T pDM_Odm
)
{
#if (RT_MEM_SIZE_LEVEL != RT_MEM_SIZE_MINIMUM)
PADAPTER Adapter = pDM_Odm->Adapter;
HAL_DATA_TYPE* pHalData = NULL;
PMGNT_INFO pMgntInfo = NULL;
//pSWAT_T pDM_SWAT_Table = &Adapter->DM_SWAT_Table;
pPD_T pDM_PDTable = NULL;
s1Byte Score = 0;
PRT_WLAN_BSS pTmpBssDesc;
PRT_WLAN_BSS pTestBssDesc;
u1Byte target_chnl = 0;
u2Byte index;
if (pDM_Odm->Adapter == NULL) //For BSOD when plug/unplug fast. //By YJ,120413
{ // The ODM structure is not initialized.
return FALSE;
}
pHalData = GET_HAL_DATA(Adapter);
pMgntInfo = &Adapter->MgntInfo;
pDM_PDTable = &Adapter->DM_PDTable;
// Condition that does not need to use path diversity.
if((!(pHalData->CVID_Version==VERSION_1_BEFORE_8703B && IS_92C_SERIAL(pHalData->VersionID))) || (pHalData->PathDivCfg!=1) || pMgntInfo->AntennaTest )
{
RT_TRACE(COMP_INIT, DBG_LOUD,
("ODM_PathDiversityBeforeLink92C(): No PathDiv Mechanism before link.\n"));
return FALSE;
}
// Since driver is going to set BB register, it shall check if there is another thread controlling BB/RF.
PlatformAcquireSpinLock(Adapter, RT_RF_STATE_SPINLOCK);
if(pHalData->eRFPowerState!=eRfOn || pMgntInfo->RFChangeInProgress || pMgntInfo->bMediaConnect)
{
PlatformReleaseSpinLock(Adapter, RT_RF_STATE_SPINLOCK);
RT_TRACE(COMP_INIT, DBG_LOUD,
("ODM_PathDiversityBeforeLink92C(): RFChangeInProgress(%x), eRFPowerState(%x)\n",
pMgntInfo->RFChangeInProgress,
pHalData->eRFPowerState));
//pDM_SWAT_Table->SWAS_NoLink_State = 0;
pDM_PDTable->PathDiv_NoLink_State = 0;
return FALSE;
}
else
{
PlatformReleaseSpinLock(Adapter, RT_RF_STATE_SPINLOCK);
}
//1 Run AntDiv mechanism "Before Link" part.
//if(pDM_SWAT_Table->SWAS_NoLink_State == 0)
if(pDM_PDTable->PathDiv_NoLink_State == 0)
{
//1 Prepare to do Scan again to check current antenna state.
// Set check state to next step.
//pDM_SWAT_Table->SWAS_NoLink_State = 1;
pDM_PDTable->PathDiv_NoLink_State = 1;
// Copy Current Scan list.
Adapter->MgntInfo.tmpNumBssDesc = pMgntInfo->NumBssDesc;
PlatformMoveMemory((PVOID)Adapter->MgntInfo.tmpbssDesc, (PVOID)pMgntInfo->bssDesc, sizeof(RT_WLAN_BSS)*MAX_BSS_DESC);
// Switch Antenna to another one.
if(pDM_PDTable->DefaultRespPath == 0)
{
PHY_SetBBReg(Adapter, rCCK0_AFESetting , 0x0F000000, 0x05); // TRX path = PathB
odm_SetRespPath_92C(Adapter, 1);
pDM_PDTable->OFDMTXPath = 0xFFFFFFFF;
pDM_PDTable->CCKTXPath = 0xFFFFFFFF;
}
else
{
PHY_SetBBReg(Adapter, rCCK0_AFESetting , 0x0F000000, 0x00); // TRX path = PathA
odm_SetRespPath_92C(Adapter, 0);
pDM_PDTable->OFDMTXPath = 0x0;
pDM_PDTable->CCKTXPath = 0x0;
}
#if 0
pDM_SWAT_Table->PreAntenna = pDM_SWAT_Table->CurAntenna;
pDM_SWAT_Table->CurAntenna = (pDM_SWAT_Table->CurAntenna==Antenna_A)?Antenna_B:Antenna_A;
RT_TRACE(COMP_INIT, DBG_LOUD,
("ODM_SwAntDivCheckBeforeLink: Change to Ant(%s) for testing.\n", (pDM_SWAT_Table->CurAntenna==Antenna_A)?"A":"B"));
//PHY_SetBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, 0x300, DM_SWAT_Table.CurAntenna);
pDM_SWAT_Table->SWAS_NoLink_BK_Reg860 = ((pDM_SWAT_Table->SWAS_NoLink_BK_Reg860 & 0xfffffcff) | (pDM_SWAT_Table->CurAntenna<<8));
PHY_SetBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, bMaskDWord, pDM_SWAT_Table->SWAS_NoLink_BK_Reg860);
#endif
// Go back to scan function again.
RT_TRACE(COMP_INIT, DBG_LOUD, ("ODM_PathDiversityBeforeLink92C: Scan one more time\n"));
pMgntInfo->ScanStep=0;
target_chnl = odm_SwAntDivSelectScanChnl(Adapter);
odm_SwAntDivConstructScanChnl(Adapter, target_chnl);
PlatformSetTimer(Adapter, &pMgntInfo->ScanTimer, 5);
return TRUE;
}
else
{
//1 ScanComple() is called after antenna swiched.
//1 Check scan result and determine which antenna is going
//1 to be used.
for(index=0; index<Adapter->MgntInfo.tmpNumBssDesc; index++)
{
pTmpBssDesc = &(Adapter->MgntInfo.tmpbssDesc[index]);
pTestBssDesc = &(pMgntInfo->bssDesc[index]);
if(PlatformCompareMemory(pTestBssDesc->bdBssIdBuf, pTmpBssDesc->bdBssIdBuf, 6)!=0)
{
RT_TRACE(COMP_INIT, DBG_LOUD, ("ODM_PathDiversityBeforeLink92C(): ERROR!! This shall not happen.\n"));
continue;
}
if(pTmpBssDesc->RecvSignalPower > pTestBssDesc->RecvSignalPower)
{
RT_TRACE(COMP_INIT, DBG_LOUD, ("ODM_PathDiversityBeforeLink92C: Compare scan entry: Score++\n"));
RT_PRINT_STR(COMP_INIT, DBG_LOUD, "SSID: ", pTestBssDesc->bdSsIdBuf, pTestBssDesc->bdSsIdLen);
RT_TRACE(COMP_INIT, DBG_LOUD, ("Original: %d, Test: %d\n", pTmpBssDesc->RecvSignalPower, pTestBssDesc->RecvSignalPower));
Score++;
PlatformMoveMemory(pTestBssDesc, pTmpBssDesc, sizeof(RT_WLAN_BSS));
}
else if(pTmpBssDesc->RecvSignalPower < pTestBssDesc->RecvSignalPower)
{
RT_TRACE(COMP_INIT, DBG_LOUD, ("ODM_PathDiversityBeforeLink92C: Compare scan entry: Score--\n"));
RT_PRINT_STR(COMP_INIT, DBG_LOUD, "SSID: ", pTestBssDesc->bdSsIdBuf, pTestBssDesc->bdSsIdLen);
RT_TRACE(COMP_INIT, DBG_LOUD, ("Original: %d, Test: %d\n", pTmpBssDesc->RecvSignalPower, pTestBssDesc->RecvSignalPower));
Score--;
}
}
if(pMgntInfo->NumBssDesc!=0 && Score<=0)
{
RT_TRACE(COMP_INIT, DBG_LOUD,
("ODM_PathDiversityBeforeLink92C(): DefaultRespPath=%d\n", pDM_PDTable->DefaultRespPath));
//pDM_SWAT_Table->PreAntenna = pDM_SWAT_Table->CurAntenna;
}
else
{
RT_TRACE(COMP_INIT, DBG_LOUD,
("ODM_PathDiversityBeforeLink92C(): DefaultRespPath=%d\n", pDM_PDTable->DefaultRespPath));
if(pDM_PDTable->DefaultRespPath == 0)
{
pDM_PDTable->OFDMTXPath = 0xFFFFFFFF;
pDM_PDTable->CCKTXPath = 0xFFFFFFFF;
odm_SetRespPath_92C(Adapter, 1);
}
else
{
pDM_PDTable->OFDMTXPath = 0x0;
pDM_PDTable->CCKTXPath = 0x0;
odm_SetRespPath_92C(Adapter, 0);
}
PHY_SetBBReg(Adapter, rCCK0_AFESetting , 0x0F000000, 0x01); // RX path = PathAB
//pDM_SWAT_Table->CurAntenna = pDM_SWAT_Table->PreAntenna;
//PHY_SetBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, 0x300, DM_SWAT_Table.CurAntenna);
//pDM_SWAT_Table->SWAS_NoLink_BK_Reg860 = ((pDM_SWAT_Table->SWAS_NoLink_BK_Reg860 & 0xfffffcff) | (pDM_SWAT_Table->CurAntenna<<8));
//PHY_SetBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, bMaskDWord, pDM_SWAT_Table->SWAS_NoLink_BK_Reg860);
}
// Check state reset to default and wait for next time.
//pDM_SWAT_Table->SWAS_NoLink_State = 0;
pDM_PDTable->PathDiv_NoLink_State = 0;
return FALSE;
}
#else
return FALSE;
#endif
}
void rtl92c_read_chip_version(struct ieee80211_hw *hw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_phy *rtlphy = &(rtlpriv->phy);
struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
enum version_8192c chip_version = VERSION_UNKNOWN;
const char *versionid;
u32 value32;
value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG);
if (value32 & TRP_VAUX_EN) {
chip_version = (value32 & TYPE_ID) ? VERSION_TEST_CHIP_92C :
VERSION_TEST_CHIP_88C;
} else {
/* Normal mass production chip. */
chip_version = NORMAL_CHIP;
chip_version |= ((value32 & TYPE_ID) ? CHIP_92C : 0);
chip_version |= ((value32 & VENDOR_ID) ? CHIP_VENDOR_UMC : 0);
/* RTL8723 with BT function. */
chip_version |= ((value32 & BT_FUNC) ? CHIP_8723 : 0);
if (IS_VENDOR_UMC(chip_version))
chip_version |= ((value32 & CHIP_VER_RTL_MASK) ?
CHIP_VENDOR_UMC_B_CUT : 0);
if (IS_92C_SERIAL(chip_version)) {
value32 = rtl_read_dword(rtlpriv, REG_HPON_FSM);
chip_version |= ((CHIP_BONDING_IDENTIFIER(value32) ==
CHIP_BONDING_92C_1T2R) ? CHIP_92C_1T2R : 0);
} else if (IS_8723_SERIES(chip_version)) {
value32 = rtl_read_dword(rtlpriv, REG_GPIO_OUTSTS);
chip_version |= ((value32 & RF_RL_ID) ?
CHIP_8723_DRV_REV : 0);
}
}
rtlhal->version = (enum version_8192c)chip_version;
pr_info("Chip version 0x%x\n", chip_version);
switch (rtlhal->version) {
case VERSION_NORMAL_TSMC_CHIP_92C_1T2R:
versionid = "NORMAL_B_CHIP_92C";
break;
case VERSION_NORMAL_TSMC_CHIP_92C:
versionid = "NORMAL_TSMC_CHIP_92C";
break;
case VERSION_NORMAL_TSMC_CHIP_88C:
versionid = "NORMAL_TSMC_CHIP_88C";
break;
case VERSION_NORMAL_UMC_CHIP_92C_1T2R_A_CUT:
versionid = "NORMAL_UMC_CHIP_i92C_1T2R_A_CUT";
break;
case VERSION_NORMAL_UMC_CHIP_92C_A_CUT:
versionid = "NORMAL_UMC_CHIP_92C_A_CUT";
break;
case VERSION_NORMAL_UMC_CHIP_88C_A_CUT:
versionid = "NORMAL_UMC_CHIP_88C_A_CUT";
break;
case VERSION_NORMAL_UMC_CHIP_92C_1T2R_B_CUT:
versionid = "NORMAL_UMC_CHIP_92C_1T2R_B_CUT";
break;
case VERSION_NORMAL_UMC_CHIP_92C_B_CUT:
versionid = "NORMAL_UMC_CHIP_92C_B_CUT";
break;
case VERSION_NORMAL_UMC_CHIP_88C_B_CUT:
versionid = "NORMAL_UMC_CHIP_88C_B_CUT";
break;
case VERSION_NORMA_UMC_CHIP_8723_1T1R_A_CUT:
versionid = "NORMAL_UMC_CHIP_8723_1T1R_A_CUT";
break;
case VERSION_NORMA_UMC_CHIP_8723_1T1R_B_CUT:
versionid = "NORMAL_UMC_CHIP_8723_1T1R_B_CUT";
break;
case VERSION_TEST_CHIP_92C:
versionid = "TEST_CHIP_92C";
break;
case VERSION_TEST_CHIP_88C:
versionid = "TEST_CHIP_88C";
break;
default:
versionid = "UNKNOWN";
break;
}
RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
"Chip Version ID: %s\n", versionid);
if (IS_92C_SERIAL(rtlhal->version))
rtlphy->rf_type =
(IS_92C_1T2R(rtlhal->version)) ? RF_1T2R : RF_2T2R;
else
rtlphy->rf_type = RF_1T1R;
RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
"Chip RF Type: %s\n",
rtlphy->rf_type == RF_2T2R ? "RF_2T2R" : "RF_1T1R");
if (get_rf_type(rtlphy) == RF_1T1R)
rtlpriv->dm.rfpath_rxenable[0] = true;
else
rtlpriv->dm.rfpath_rxenable[0] =
rtlpriv->dm.rfpath_rxenable[1] = true;
RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n",
rtlhal->version);
}
int rtl92c_init_sw_vars(struct ieee80211_hw *hw)
{
int err;
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
rtl8192ce_bt_reg_init(hw);
rtlpriv->dm.dm_initialgain_enable = true;
rtlpriv->dm.dm_flag = 0;
rtlpriv->dm.disable_framebursting = false;
rtlpriv->dm.thermalvalue = 0;
rtlpci->transmit_config = CFENDFORM | BIT(12) | BIT(13);
/* compatible 5G band 88ce just 2.4G band & smsp */
rtlpriv->rtlhal.current_bandtype = BAND_ON_2_4G;
rtlpriv->rtlhal.bandset = BAND_ON_2_4G;
rtlpriv->rtlhal.macphymode = SINGLEMAC_SINGLEPHY;
rtlpci->receive_config = (RCR_APPFCS |
RCR_AMF |
RCR_ADF |
RCR_APP_MIC |
RCR_APP_ICV |
RCR_AICV |
RCR_ACRC32 |
RCR_AB |
RCR_AM |
RCR_APM |
RCR_APP_PHYST_RXFF | RCR_HTC_LOC_CTRL | 0);
rtlpci->irq_mask[0] =
(u32) (IMR_ROK |
IMR_VODOK |
IMR_VIDOK |
IMR_BEDOK |
IMR_BKDOK |
IMR_MGNTDOK |
IMR_HIGHDOK | IMR_BDOK | IMR_RDU | IMR_RXFOVW | 0);
rtlpci->irq_mask[1] = (u32) (IMR_CPWM | IMR_C2HCMD | 0);
/* for debug level */
rtlpriv->dbg.global_debuglevel = rtlpriv->cfg->mod_params->debug;
/* for LPS & IPS */
rtlpriv->psc.inactiveps = rtlpriv->cfg->mod_params->inactiveps;
rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps;
rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps;
if (!rtlpriv->psc.inactiveps)
pr_info("rtl8192ce: Power Save off (module option)\n");
if (!rtlpriv->psc.fwctrl_lps)
pr_info("rtl8192ce: FW Power Save off (module option)\n");
rtlpriv->psc.reg_fwctrl_lps = 3;
rtlpriv->psc.reg_max_lps_awakeintvl = 5;
/* for ASPM, you can close aspm through
* set const_support_pciaspm = 0 */
rtl92c_init_aspm_vars(hw);
if (rtlpriv->psc.reg_fwctrl_lps == 1)
rtlpriv->psc.fwctrl_psmode = FW_PS_MIN_MODE;
else if (rtlpriv->psc.reg_fwctrl_lps == 2)
rtlpriv->psc.fwctrl_psmode = FW_PS_MAX_MODE;
else if (rtlpriv->psc.reg_fwctrl_lps == 3)
rtlpriv->psc.fwctrl_psmode = FW_PS_DTIM_MODE;
/* for firmware buf */
rtlpriv->rtlhal.pfirmware = vzalloc(0x4000);
if (!rtlpriv->rtlhal.pfirmware) {
RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
"Can't alloc buffer for fw\n");
return 1;
}
/* request fw */
if (IS_VENDOR_UMC_A_CUT(rtlhal->version) &&
!IS_92C_SERIAL(rtlhal->version)) {
rtlpriv->cfg->fw_name = "rtlwifi/rtl8192cfwU.bin";
} else if (IS_81xxC_VENDOR_UMC_B_CUT(rtlhal->version)) {
rtlpriv->cfg->fw_name = "rtlwifi/rtl8192cfwU_B.bin";
pr_info("****** This B_CUT device may not work with kernels 3.6 and earlier\n");
}
rtlpriv->max_fw_size = 0x4000;
pr_info("Using firmware %s\n", rtlpriv->cfg->fw_name);
err = request_firmware_nowait(THIS_MODULE, 1, rtlpriv->cfg->fw_name,
rtlpriv->io.dev, GFP_KERNEL, hw,
rtl_fw_cb);
if (err) {
RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
"Failed to request firmware!\n");
return 1;
}
return 0;
}
//
// Description:
// Download 8192C firmware code.
//
//
int FirmwareDownload92C(
IN PADAPTER Adapter
)
{
int rtStatus = _SUCCESS;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
char R92CFwImageFileName_TSMC[] ={RTL8192C_FW_TSMC_IMG};
char R92CFwImageFileName_UMC[] ={RTL8192C_FW_UMC_IMG};
char R8723FwImageFileName_UMC[] ={RTL8723_FW_UMC_IMG};
char * FwImage;
u32 FwImageLen;
char* pFwImageFileName;
//vivi, merge 92c and 92s into one driver, 20090817
//vivi modify this temply, consider it later!!!!!!!!
//PRT_FIRMWARE pFirmware = GET_FIRMWARE_819X(Adapter);
//PRT_FIRMWARE_92C pFirmware = GET_FIRMWARE_8192C(Adapter);
PRT_FIRMWARE_92C pFirmware = NULL;
PRT_8192C_FIRMWARE_HDR pFwHdr = NULL;
u8 *pFirmwareBuf;
u32 FirmwareLen;
pFirmware = (PRT_FIRMWARE_92C)_rtw_malloc(sizeof(RT_FIRMWARE_92C));
if(!pFirmware)
{
rtStatus = _FAIL;
goto Exit;
}
//RT_TRACE(COMP_INIT, DBG_LOUD, (" ===> FirmwareDownload91C() fw:%s\n", pFwImageFileName));
#ifdef CONFIG_EMBEDDED_FWIMG
pFirmware->eFWSource = FW_SOURCE_HEADER_FILE;
#else
pFirmware->eFWSource = FW_SOURCE_IMG_FILE;
#endif
if(IS_NORMAL_CHIP(pHalData->VersionID))
{
if(IS_VENDOR_UMC_A_CUT(pHalData->VersionID) && !IS_92C_SERIAL(pHalData->VersionID))// UMC , 8188
{
pFwImageFileName = R92CFwImageFileName_UMC;
FwImage = Rtl819XFwUMCImageArray;
FwImageLen = UMCImgArrayLength;
DBG_871X(" ===> FirmwareDownload91C() fw:Rtl819XFwImageArray_UMC\n");
}
else
{
pFwImageFileName = R92CFwImageFileName_TSMC;
FwImage = Rtl819XFwTSMCImageArray;
FwImageLen = TSMCImgArrayLength;
DBG_871X(" ===> FirmwareDownload91C() fw:Rtl819XFwImageArray_TSMC\n");
}
}
else
{
#if 0
pFwImageFileName = TestChipFwFile;
FwImage = Rtl8192CTestFwImg;
FwImageLen = Rtl8192CTestFwImgLen;
RT_TRACE(COMP_INIT, DBG_LOUD, (" ===> FirmwareDownload91C() fw:Rtl8192CTestFwImg\n"));
#endif
}
switch(pFirmware->eFWSource)
{
case FW_SOURCE_IMG_FILE:
//TODO:load fw bin file
break;
case FW_SOURCE_HEADER_FILE:
if(TSMCImgArrayLength > FW_8192C_SIZE){
rtStatus = _FAIL;
//RT_TRACE(COMP_INIT, DBG_SERIOUS, ("Firmware size exceed 0x%X. Check it.\n", FW_8192C_SIZE) );
DBG_871X("Firmware size exceed 0x%X. Check it.\n", FW_8192C_SIZE);
goto Exit;
}
_rtw_memcpy(pFirmware->szFwBuffer, FwImage, FwImageLen);
pFirmware->ulFwLength = FwImageLen;
break;
}
pFirmwareBuf = pFirmware->szFwBuffer;
FirmwareLen = pFirmware->ulFwLength;
// To Check Fw header.
pFwHdr = (PRT_8192C_FIRMWARE_HDR)pFirmware->szFwBuffer;
pHalData->FirmwareVersion = le16_to_cpu(pFwHdr->Version);
pHalData->FirmwareSubVersion = le16_to_cpu(pFwHdr->Subversion);
//RT_TRACE(COMP_INIT, DBG_LOUD, (" FirmwareVersion(%#x), Signature(%#x)\n",
// Adapter->MgntInfo.FirmwareVersion, pFwHdr->Signature));
DBG_8192C("fw_ver=v%d, fw_subver=%d, sig=0x%x\n",
pHalData->FirmwareVersion, pHalData->FirmwareSubVersion, le16_to_cpu(pFwHdr->Signature)&0xFFF0);
if(IS_FW_HEADER_EXIST(pFwHdr))
{
//RT_TRACE(COMP_INIT, DBG_LOUD,("Shift 32 bytes for FW header!!\n"));
pFirmwareBuf = pFirmwareBuf + 32;
FirmwareLen = FirmwareLen -32;
}
// Suggested by Filen. If 8051 is running in RAM code, driver should inform Fw to reset by itself,
// or it will cause download Fw fail. 2010.02.01. by tynli.
if(rtw_read8(Adapter, REG_MCUFWDL)&BIT7) //8051 RAM code
{
DBG_8192C("8051 in Ram......prepare to reset by itself\n");
_FirmwareSelfReset(Adapter);
rtw_write8(Adapter, REG_MCUFWDL, 0x00);
}
_FWDownloadEnable(Adapter, _TRUE);
_WriteFW(Adapter, pFirmwareBuf, FirmwareLen);
_FWDownloadEnable(Adapter, _FALSE);
rtStatus = _FWFreeToGo(Adapter);
if(_SUCCESS != rtStatus){
//RT_TRACE(COMP_INIT, DBG_SERIOUS, ("DL Firmware failed!\n") );
goto Exit;
}
//RT_TRACE(COMP_INIT, DBG_LOUD, (" Firmware is ready to run!\n"));
Exit:
if(pFirmware)
_rtw_mfree((u8*)pFirmware, sizeof(RT_FIRMWARE_92C));
//RT_TRACE(COMP_INIT, DBG_LOUD, (" <=== FirmwareDownload91C()\n"));
return rtStatus;
}
int
phy_RF6052_Config_ParaFile(
IN PADAPTER Adapter
)
{
u32 u4RegValue;
u8 eRFPath;
BB_REGISTER_DEFINITION_T *pPhyReg;
int rtStatus = _SUCCESS;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
static char sz88CRadioAFile[] = RTL8188C_PHY_RADIO_A;
static char sz88CRadioBFile[] = RTL8188C_PHY_RADIO_B;
static char sz92CRadioAFile[] = RTL8192C_PHY_RADIO_A;
static char sz92CRadioBFile[] = RTL8192C_PHY_RADIO_B;
static char sz88CTestRadioAFile[] = RTL8188C_PHY_RADIO_A;
static char sz88CTestRadioBFile[] = RTL8188C_PHY_RADIO_B;
static char sz92CTestRadioAFile[] = RTL8192C_PHY_RADIO_A;
static char sz92CTestRadioBFile[] = RTL8192C_PHY_RADIO_B;
static char sz92DRadioAFile[] = RTL8192D_PHY_RADIO_A;
static char sz92DRadioBFile[] = RTL8192D_PHY_RADIO_B;
static char sz92DTestRadioAFile[] = RTL8192D_PHY_RADIO_A;
static char sz92DTestRadioBFile[] = RTL8192D_PHY_RADIO_B;
u8 *pszRadioAFile, *pszRadioBFile;
u8 u1bTmp;
BOOLEAN bMac1NeedInitRadioAFirst = _FALSE;
BOOLEAN bNeedPowerDownRadioA = _FALSE;
// 92D RF config zhiyuan 2010/04/07
// Single phy mode: use radio_a radio_b config path_A path_B seperately by MAC0, and MAC1 needn't configure RF;
// Dual PHY mode:MAC0 use radio_a config 1st phy path_A, MAC1 use radio_b config 2nd PHY path_A.
if(IS_HARDWARE_TYPE_8192D(pHalData)){
if(IS_NORMAL_CHIP(pHalData->VersionID))
{
pszRadioAFile = sz92DRadioAFile;
pszRadioBFile = sz92DRadioBFile;
if(pHalData->interfaceIndex==1)
{
if(pHalData->MacPhyMode92D==DUALMAC_DUALPHY)
pszRadioAFile = sz92DRadioBFile;
else
return rtStatus;
}
}
else
{
pszRadioAFile = sz92DTestRadioAFile;
pszRadioBFile = sz92DTestRadioBFile;
if(pHalData->interfaceIndex==1)
{
//
// when 92D test chip dual mac dual phy mode, if enable MAC1 first, before init RF radio B,
// also init RF radio A, and then let radio A go to power down mode.
// Note: normal chip need do this or not will be considerred later.
//
if(pHalData->MacPhyMode92D==DUALMAC_DUALPHY)
{
u1bTmp = read8(Adapter, REG_MAC0);
if (!(u1bTmp&MAC0_ON))
{
// MAC0 not enabled, also init radio A before init radio B.
// Enable BB and RF
#if (DEV_BUS_TYPE == PCI_INTERFACE)
//PlatformEFIOWrite1Byte(Adapter, REG_SYS_FUNC_EN, 0xE0);
#if 0
MpWritePCIDwordDBI8192C(Adapter,
(REG_SYS_FUNC_EN - 2),
MpReadPCIDwordDBI8192C(Adapter, (REG_SYS_FUNC_EN - 2), BIT3)&0xFFFCFFFF,
BIT3);
#endif
//u2bTmp = PlatformEFIORead2Byte(Adapter, REG_SYS_FUNC_EN);
//PlatformEFIOWrite2Byte(Adapter, REG_SYS_FUNC_EN, u2bTmp|BIT13|BIT0|BIT1);
MpWritePCIDwordDBI8192C(Adapter,
(REG_SYS_FUNC_EN - 2),
MpReadPCIDwordDBI8192C(Adapter, (REG_SYS_FUNC_EN - 2), BIT3)|BIT29|BIT16|BIT17,
BIT3);
#elif (DEV_BUS_TYPE == USB_INTERFACE)
pHalData->bDuringMac1InitRadioA = _TRUE;
write16(Adapter, REG_SYS_FUNC_EN, read16(Adapter, REG_SYS_FUNC_EN)&0xFFFC);
write16(Adapter, REG_SYS_FUNC_EN, read16(Adapter, REG_SYS_FUNC_EN)|BIT13|BIT0|BIT1);
pHalData->bDuringMac1InitRadioA = _FALSE;
#endif
pHalData->NumTotalRFPath = 2;
bMac1NeedInitRadioAFirst = _TRUE;
}
else
{
// MAC0 enabled, only init radia B.
pszRadioAFile = sz92DTestRadioBFile;
}
}
else
{
return rtStatus;
}
}
}
}
else{
if(IS_92C_SERIAL( pHalData->VersionID))// 88c's IPA is different from 92c's
{
if(IS_NORMAL_CHIP(pHalData->VersionID))
{
pszRadioAFile = sz92CRadioAFile;
pszRadioBFile = sz92CRadioBFile;
}
else
{
pszRadioAFile = sz92CTestRadioAFile;
pszRadioBFile = sz92CTestRadioBFile;
}
}
else
{
if(IS_NORMAL_CHIP(pHalData->VersionID))
{
pszRadioAFile = sz88CRadioAFile;
pszRadioBFile = sz88CRadioBFile;
}
else
{
pszRadioAFile = sz88CTestRadioAFile;
pszRadioBFile = sz88CTestRadioBFile;
}
}
}
//3//-----------------------------------------------------------------
//3// <2> Initialize RF
//3//-----------------------------------------------------------------
//for(eRFPath = RF90_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
for(eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
{
if (IS_HARDWARE_TYPE_8192D(pHalData) && bMac1NeedInitRadioAFirst)
{
if (eRFPath == RF90_PATH_A)
{
pHalData->bDuringMac1InitRadioA = _TRUE;
bNeedPowerDownRadioA = _TRUE;
}
if (eRFPath == RF90_PATH_B)
{
pHalData->bDuringMac1InitRadioA = _FALSE;
bMac1NeedInitRadioAFirst = _FALSE;
eRFPath = RF90_PATH_A;
pszRadioAFile = sz92DTestRadioBFile;
pHalData->NumTotalRFPath = 1;
}
}
pPhyReg = &pHalData->PHYRegDef[eRFPath];
/*----Store original RFENV control type----*/
switch(eRFPath)
{
case RF90_PATH_A:
case RF90_PATH_C:
u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV);
break;
case RF90_PATH_B :
case RF90_PATH_D:
u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV<<16);
break;
}
/*----Set RF_ENV enable----*/
PHY_SetBBReg(Adapter, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1);
udelay_os(1);//PlatformStallExecution(1);
/*----Set RF_ENV output high----*/
PHY_SetBBReg(Adapter, pPhyReg->rfintfo, bRFSI_RFENV, 0x1);
udelay_os(1);//PlatformStallExecution(1);
/* Set bit number of Address and Data for RF register */
PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); // Set 1 to 4 bits for 8255
udelay_os(1);//PlatformStallExecution(1);
PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); // Set 0 to 12 bits for 8255
udelay_os(1);//PlatformStallExecution(1);
/*----Initialize RF fom connfiguration file----*/
switch(eRFPath)
{
case RF90_PATH_A:
#ifdef CONFIG_EMBEDDED_FWIMG
rtStatus= PHY_ConfigRFWithHeaderFile(Adapter,(RF90_RADIO_PATH_E)eRFPath);
#else
rtStatus = PHY_ConfigRFWithParaFile(Adapter, pszRadioAFile, (RF90_RADIO_PATH_E)eRFPath);
#endif
break;
case RF90_PATH_B:
#ifdef CONFIG_EMBEDDED_FWIMG
rtStatus= PHY_ConfigRFWithHeaderFile(Adapter,(RF90_RADIO_PATH_E)eRFPath);
#else
rtStatus = PHY_ConfigRFWithParaFile(Adapter, pszRadioBFile, (RF90_RADIO_PATH_E)eRFPath);
#endif
break;
case RF90_PATH_C:
break;
case RF90_PATH_D:
break;
}
/*----Restore RFENV control type----*/;
switch(eRFPath)
{
case RF90_PATH_A:
case RF90_PATH_C:
PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue);
break;
case RF90_PATH_B :
case RF90_PATH_D:
PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV<<16, u4RegValue);
break;
}
if(rtStatus != _SUCCESS){
//RT_TRACE(COMP_FPGA, DBG_LOUD, ("phy_RF6052_Config_ParaFile():Radio[%d] Fail!!", eRFPath));
goto phy_RF6052_Config_ParaFile_Fail;
}
}
if (IS_HARDWARE_TYPE_8192D(pHalData) && bNeedPowerDownRadioA)
{
// check MAC0 enable or not again now, if enabled, not power down radio A.
u1bTmp = read8(Adapter, REG_MAC0);
if (!(u1bTmp&MAC0_ON))
{
// power down RF radio A according to YuNan's advice.
#if (DEV_BUS_TYPE == PCI_INTERFACE)
MpWritePCIDwordDBI8192C(Adapter,
rFPGA0_XA_LSSIParameter,
0x00000000,
BIT3);
#elif (DEV_BUS_TYPE == USB_INTERFACE)
pHalData->bDuringMac1InitRadioA = _TRUE;
write32(Adapter, rFPGA0_XA_LSSIParameter, 0x00000000);
pHalData->bDuringMac1InitRadioA = _FALSE;
#endif
}
bNeedPowerDownRadioA = _FALSE;
}
//RT_TRACE(COMP_INIT, DBG_LOUD, ("<---phy_RF6052_Config_ParaFile()\n"));
return rtStatus;
phy_RF6052_Config_ParaFile_Fail:
return rtStatus;
}
int rtl92c_init_sw_vars(struct ieee80211_hw *hw)
{
int err = 0;
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
const struct firmware *firmware;
struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
char *fw_name = NULL;
rtl8192ce_bt_reg_init(hw);
rtlpriv->dm.b_dm_initialgain_enable = 1;
rtlpriv->dm.dm_flag = 0;
rtlpriv->dm.b_disable_framebursting = 0;;
rtlpriv->dm.thermalvalue = 0;
rtlpci->transmit_config = CFENDFORM | BIT(12) | BIT(13);
/* compatible 5G band 88ce just 2.4G band & smsp */
rtlpriv->rtlhal.current_bandtype = BAND_ON_2_4G;
rtlpriv->rtlhal.bandset = BAND_ON_2_4G;
rtlpriv->rtlhal.macphymode = SINGLEMAC_SINGLEPHY;
rtlpci->receive_config = (RCR_APPFCS |
RCR_AMF |
RCR_ADF |
RCR_APP_MIC |
RCR_APP_ICV |
RCR_AICV |
RCR_ACRC32 |
RCR_AB |
RCR_AM |
RCR_APM |
RCR_APP_PHYST_RXFF | RCR_HTC_LOC_CTRL | 0);
rtlpci->irq_mask[0] =
(u32) (IMR_ROK |
IMR_VODOK |
IMR_VIDOK |
IMR_BEDOK |
IMR_BKDOK |
IMR_MGNTDOK |
IMR_HIGHDOK | IMR_BDOK | IMR_RDU | IMR_RXFOVW | 0);
rtlpci->irq_mask[1] = (u32) (IMR_CPWM | IMR_C2HCMD | 0);
/* for LPS & IPS */
rtlpriv->psc.b_inactiveps = rtlpriv->cfg->mod_params->b_inactiveps;
rtlpriv->psc.b_swctrl_lps = rtlpriv->cfg->mod_params->b_swctrl_lps;
rtlpriv->psc.b_fwctrl_lps = rtlpriv->cfg->mod_params->b_fwctrl_lps;
rtlpriv->psc.b_reg_fwctrl_lps = 3;
rtlpriv->psc.reg_max_lps_awakeintvl = 5;
/* for ASPM, you can close aspm through
* set const_support_pciaspm = 0 */
rtl92c_init_aspm_vars(hw);
if (rtlpriv->psc.b_reg_fwctrl_lps == 1)
rtlpriv->psc.fwctrl_psmode = FW_PS_MIN_MODE;
else if (rtlpriv->psc.b_reg_fwctrl_lps == 2)
rtlpriv->psc.fwctrl_psmode = FW_PS_MAX_MODE;
else if (rtlpriv->psc.b_reg_fwctrl_lps == 3)
rtlpriv->psc.fwctrl_psmode = FW_PS_DTIM_MODE;
/* for firmware buf */
rtlpriv->rtlhal.pfirmware = (u8 *) vmalloc(0x4000);
if (!rtlpriv->rtlhal.pfirmware) {
RT_TRACE(COMP_ERR, DBG_EMERG,
("Can't alloc buffer for fw.\n"));
return 1;
}
if (IS_VENDOR_UMC_A_CUT(rtlhal->version) && !IS_92C_SERIAL(rtlhal->version))
fw_name = "rtlwifi/rtl8192cfwU.bin";
else if (IS_81xxC_VENDOR_UMC_B_CUT(rtlhal->version))
fw_name = "rtlwifi/rtl8192cfwU_B.bin";
else
fw_name = rtlpriv->cfg->fw_name;
err = request_firmware(&firmware, fw_name, rtlpriv->io.dev);
if (err) {
RT_TRACE(COMP_ERR, DBG_EMERG,
("Failed to request firmware!\n"));
return 1;
}
if (firmware->size > 0x4000) {
RT_TRACE(COMP_ERR, DBG_EMERG,
("Firmware is too big!\n"));
release_firmware(firmware);
return 1;
}
memcpy(rtlpriv->rtlhal.pfirmware, firmware->data, firmware->size);
rtlpriv->rtlhal.fwsize = firmware->size;
release_firmware(firmware);
return err;
}
bool rtl92c_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
enum radio_path rfpath)
{
int i;
bool rtstatus = true;
u32 *radioa_array_table;
u32 *radiob_array_table;
u16 radioa_arraylen, radiob_arraylen;
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
if (IS_92C_SERIAL(rtlhal->version)) {
radioa_arraylen = RADIOA_2TARRAYLENGTH;
radioa_array_table = RTL8192CERADIOA_2TARRAY;
radiob_arraylen = RADIOB_2TARRAYLENGTH;
radiob_array_table = RTL8192CE_RADIOB_2TARRAY;
RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
("Radio_A:RTL8192CERADIOA_2TARRAY\n"));
RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
("Radio_B:RTL8192CE_RADIOB_2TARRAY\n"));
} else {
radioa_arraylen = RADIOA_1TARRAYLENGTH;
radioa_array_table = RTL8192CE_RADIOA_1TARRAY;
radiob_arraylen = RADIOB_1TARRAYLENGTH;
radiob_array_table = RTL8192CE_RADIOB_1TARRAY;
RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
("Radio_A:RTL8192CE_RADIOA_1TARRAY\n"));
RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
("Radio_B:RTL8192CE_RADIOB_1TARRAY\n"));
}
RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("Radio No %x\n", rfpath));
rtstatus = true;
switch (rfpath) {
case RF90_PATH_A:
for (i = 0; i < radioa_arraylen; i = i + 2) {
if (radioa_array_table[i] == 0xfe)
mdelay(50);
else if (radioa_array_table[i] == 0xfd)
mdelay(5);
else if (radioa_array_table[i] == 0xfc)
mdelay(1);
else if (radioa_array_table[i] == 0xfb)
udelay(50);
else if (radioa_array_table[i] == 0xfa)
udelay(5);
else if (radioa_array_table[i] == 0xf9)
udelay(1);
else {
rtl_set_rfreg(hw, rfpath, radioa_array_table[i],
RFREG_OFFSET_MASK,
radioa_array_table[i + 1]);
udelay(1);
}
}
break;
case RF90_PATH_B:
for (i = 0; i < radiob_arraylen; i = i + 2) {
if (radiob_array_table[i] == 0xfe) {
mdelay(50);
} else if (radiob_array_table[i] == 0xfd)
mdelay(5);
else if (radiob_array_table[i] == 0xfc)
mdelay(1);
else if (radiob_array_table[i] == 0xfb)
udelay(50);
else if (radiob_array_table[i] == 0xfa)
udelay(5);
else if (radiob_array_table[i] == 0xf9)
udelay(1);
else {
rtl_set_rfreg(hw, rfpath, radiob_array_table[i],
RFREG_OFFSET_MASK,
radiob_array_table[i + 1]);
udelay(1);
}
}
break;
case RF90_PATH_C:
RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
("switch case not process\n"));
break;
case RF90_PATH_D:
RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
("switch case not process\n"));
break;
}
return true;
}
static int
phy_RF6052_Config_ParaFile(
IN PADAPTER Adapter
)
{
u32 u4RegValue;
u8 eRFPath;
BB_REGISTER_DEFINITION_T *pPhyReg;
int rtStatus = _SUCCESS;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
static char sz88CRadioAFile[] = RTL8188C_PHY_RADIO_A;
static char sz88CRadioBFile[] = RTL8188C_PHY_RADIO_B;
#ifdef CONFIG_USB_HCI
static char sz88CRadioAFile_mCard[] = RTL8188C_PHY_RADIO_A_mCard;
static char sz88CRadioBFile_mCard[] = RTL8188C_PHY_RADIO_B_mCard;
static char sz88CRadioAFile_HP[] = RTL8188C_PHY_RADIO_A_HP;
#endif
static char sz92CRadioAFile[] = RTL8192C_PHY_RADIO_A;
static char sz92CRadioBFile[] = RTL8192C_PHY_RADIO_B;
static char sz8723RadioAFile[] = RTL8723_PHY_RADIO_A;
static char sz8723RadioBFile[] = RTL8723_PHY_RADIO_B;
char *pszRadioAFile, *pszRadioBFile;
if(IS_HARDWARE_TYPE_8192C(Adapter))
{
if(IS_92C_SERIAL( pHalData->VersionID))// 88c's IPA is different from 92c's
{
if(IS_NORMAL_CHIP(pHalData->VersionID))
{
pszRadioAFile = sz92CRadioAFile;
pszRadioBFile = sz92CRadioBFile;
}
else
{
rtStatus = _FAIL;
return rtStatus;
}
}
else
{
if(IS_NORMAL_CHIP(pHalData->VersionID))
{
pszRadioAFile = sz88CRadioAFile;
pszRadioBFile = sz88CRadioBFile;
#ifdef CONFIG_USB_HCI
if( BOARD_MINICARD == pHalData->BoardType)
{
pszRadioAFile = sz88CRadioAFile_mCard;
pszRadioBFile = sz88CRadioBFile_mCard;
}
else if( BOARD_USB_High_PA == pHalData->BoardType)
{
pszRadioAFile = sz88CRadioAFile_HP;
}
#endif
}
else
{
rtStatus = _FAIL;
return rtStatus;
}
}
}
else if(IS_HARDWARE_TYPE_8723(Adapter))
{
pszRadioAFile = sz8723RadioAFile;
pszRadioBFile = sz8723RadioBFile;
}
//3//-----------------------------------------------------------------
//3// <2> Initialize RF
//3//-----------------------------------------------------------------
//for(eRFPath = RF90_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
for(eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
{
pPhyReg = &pHalData->PHYRegDef[eRFPath];
/*----Store original RFENV control type----*/
switch(eRFPath)
{
case RF90_PATH_A:
case RF90_PATH_C:
u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV);
break;
case RF90_PATH_B :
case RF90_PATH_D:
u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV<<16);
break;
}
/*----Set RF_ENV enable----*/
PHY_SetBBReg(Adapter, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1);
rtw_udelay_os(1);//PlatformStallExecution(1);
/*----Set RF_ENV output high----*/
PHY_SetBBReg(Adapter, pPhyReg->rfintfo, bRFSI_RFENV, 0x1);
rtw_udelay_os(1);//PlatformStallExecution(1);
/* Set bit number of Address and Data for RF register */
PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); // Set 1 to 4 bits for 8255
rtw_udelay_os(1);//PlatformStallExecution(1);
PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); // Set 0 to 12 bits for 8255
rtw_udelay_os(1);//PlatformStallExecution(1);
/*----Initialize RF fom connfiguration file----*/
switch(eRFPath)
{
case RF90_PATH_A:
#ifdef CONFIG_EMBEDDED_FWIMG
rtStatus= rtl8192c_PHY_ConfigRFWithHeaderFile(Adapter,(RF90_RADIO_PATH_E)eRFPath);
#else
rtStatus = rtl8192c_PHY_ConfigRFWithParaFile(Adapter, pszRadioAFile, (RF90_RADIO_PATH_E)eRFPath);
#endif
break;
case RF90_PATH_B:
#ifdef CONFIG_EMBEDDED_FWIMG
rtStatus = rtl8192c_PHY_ConfigRFWithHeaderFile(Adapter,(RF90_RADIO_PATH_E)eRFPath);
#else
rtStatus = rtl8192c_PHY_ConfigRFWithParaFile(Adapter, pszRadioBFile, (RF90_RADIO_PATH_E)eRFPath);
#endif
break;
case RF90_PATH_C:
break;
case RF90_PATH_D:
break;
}
/*----Restore RFENV control type----*/;
switch(eRFPath)
{
case RF90_PATH_A:
case RF90_PATH_C:
PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue);
break;
case RF90_PATH_B :
case RF90_PATH_D:
PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV<<16, u4RegValue);
break;
}
if(rtStatus != _SUCCESS){
//RT_TRACE(COMP_FPGA, DBG_LOUD, ("phy_RF6052_Config_ParaFile():Radio[%d] Fail!!", eRFPath));
goto phy_RF6052_Config_ParaFile_Fail;
}
}
//RT_TRACE(COMP_INIT, DBG_LOUD, ("<---phy_RF6052_Config_ParaFile()\n"));
return rtStatus;
phy_RF6052_Config_ParaFile_Fail:
return rtStatus;
}
//-------------------------------------------------------------------
//
// EEPROM/EFUSE Content Parsing
//
//-------------------------------------------------------------------
static VERSION_8192C
ReadChipVersion(
IN PADAPTER Adapter
)
{
u32 value32;
VERSION_8192C version;
u8 ChipVersion=0;
value32 = rtw_read32(Adapter, REG_SYS_CFG);
if (value32 & TRP_VAUX_EN){
version = (value32 & TYPE_ID) ?VERSION_TEST_CHIP_92C :VERSION_TEST_CHIP_88C;
}
else{
ChipVersion = NORMAL_CHIP;
ChipVersion |= ((value32 & TYPE_ID) ? CHIP_92C : 0);
ChipVersion |= ((value32 & VENDOR_ID) ? CHIP_VENDOR_UMC : 0);
ChipVersion |= ((value32 & BT_FUNC) ? CHIP_8723: 0); // RTL8723 with BT function.
#if 0
if(IS_VENDOR_UMC(ChipVersion))
ChipVersion |= ((value32 & CHIP_VER_RTL_MASK) ? CHIP_VENDOR_UMC_B_CUT : 0);
#else
// 88/92C UMC B-cut IC will not set the SYS_CFG[19] to UMC
// because we do not want the custmor to know. by tynli. 2011.01.17.
if((!IS_VENDOR_UMC(ChipVersion) )&& (value32 & CHIP_VER_RTL_MASK))
{
ChipVersion |= CHIP_VENDOR_UMC;
ChipVersion |= CHIP_VENDOR_UMC_B_CUT;
}
#endif
if(IS_92C_SERIAL(ChipVersion))
{
value32 = rtw_read32(Adapter, REG_HPON_FSM);
ChipVersion |= ((CHIP_BONDING_IDENTIFIER(value32) == CHIP_BONDING_92C_1T2R) ? CHIP_92C_1T2R : 0);
}
else if(IS_8723_SERIES(ChipVersion))
{
value32 = rtw_read32(Adapter, REG_GPIO_OUTSTS);
ChipVersion |= ((value32 & RF_RL_ID) ? CHIP_8723_DRV_REV : 0);
}
version = (VERSION_8192C)ChipVersion;
}
switch(version)
{
case VERSION_NORMAL_TSMC_CHIP_92C_1T2R:
MSG_8192C("Chip Version ID: VERSION_NORMAL_TSMC_CHIP_92C_1T2R.\n");
break;
case VERSION_NORMAL_TSMC_CHIP_92C:
MSG_8192C("Chip Version ID: VERSION_NORMAL_TSMC_CHIP_92C.\n");
break;
case VERSION_NORMAL_TSMC_CHIP_88C:
MSG_8192C("Chip Version ID: VERSION_NORMAL_TSMC_CHIP_88C.\n");
break;
case VERSION_NORMAL_UMC_CHIP_92C_1T2R_A_CUT:
MSG_8192C("Chip Version ID: VERSION_NORMAL_UMC_CHIP_92C_1T2R_A_CUT.\n");
break;
case VERSION_NORMAL_UMC_CHIP_92C_A_CUT:
MSG_8192C("Chip Version ID: VERSION_NORMAL_UMC_CHIP_92C_A_CUT.\n");
break;
case VERSION_NORMAL_UMC_CHIP_88C_A_CUT:
MSG_8192C("Chip Version ID: VERSION_NORMAL_UMC_CHIP_88C_A_CUT.\n");
break;
case VERSION_NORMAL_UMC_CHIP_92C_1T2R_B_CUT:
MSG_8192C("Chip Version ID: VERSION_NORMAL_UMC_CHIP_92C_1T2R_B_CUT.\n");
break;
case VERSION_NORMAL_UMC_CHIP_92C_B_CUT:
MSG_8192C("Chip Version ID: VERSION_NORMAL_UMC_CHIP_92C_B_CUT.\n");
break;
case VERSION_NORMAL_UMC_CHIP_88C_B_CUT:
MSG_8192C("Chip Version ID: VERSION_NORMAL_UMC_CHIP_88C_B_CUT.\n");
break;
case VERSION_TEST_CHIP_92C:
MSG_8192C("Chip Version ID: VERSION_TEST_CHIP_92C.\n");
break;
case VERSION_TEST_CHIP_88C:
MSG_8192C("Chip Version ID: VERSION_TEST_CHIP_88C.\n");
break;
case VERSION_NORMA_UMC_CHIP_8723_1T1R_A_CUT:
MSG_8192C("Chip Version ID: VERSION_NORMA_UMC_CHIP_8723_1T1R_A_CUT.\n");
break;
case VERSION_NORMA_UMC_CHIP_8723_1T1R_B_CUT:
MSG_8192C("Chip Version ID: VERSION_NORMA_UMC_CHIP_8723_1T1R_B_CUT.\n");
break;
default:
MSG_8192C("Chip Version ID: ???????????????.\n");
break;
}
return version;
}
