/**
* @brief Initializes the DAC according to the specified parameters.
* @param DAC_Channel : the selected DAC channel from @ref DAC_Channel_TypeDef
* enumeration.
* @param DAC_Trigger : the selected DAC trigger from @ref DAC_Trigger_TypeDef
* enumeration.
* @param DAC_OutputBuffer : the status of DAC load Buffer from
* @ref DAC_OutputBuffer_TypeDef enumeration.
* @retval None
*/
void DAC_Init(DAC_Channel_TypeDef DAC_Channel,
DAC_Trigger_TypeDef DAC_Trigger,
DAC_OutputBuffer_TypeDef DAC_OutputBuffer)
{
uint8_t tmpreg = 0;
uint16_t tmpreg2 = 0;
/* Check the DAC parameters */
assert_param(IS_DAC_CHANNEL(DAC_Channel));
assert_param(IS_DAC_TRIGGER(DAC_Trigger));
assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_OutputBuffer));
/* Get the DAC CHxCR1 value */
tmpreg2 = (uint16_t)((uint8_t)((uint8_t)DAC_Channel << 1));
tmpreg = *(uint8_t*)((uint16_t)(DAC_BASE + CR1_Offset + tmpreg2));
/* Clear BOFFx, TENx, TSELx bits */
tmpreg &= (uint8_t)~(DAC_CR1_BOFF | DAC_CR1_TEN | DAC_CR1_TSEL );
/* Set BOFFx bit according to DAC_OutputBuffer value */
tmpreg |= (uint8_t)(DAC_OutputBuffer);
/* Configure for the selected DAC channel trigger*/
if (DAC_Trigger != DAC_Trigger_None)
{
/* Set TSELx and TEN bits according to DAC_Trigger value */
tmpreg |= (uint8_t)(DAC_CR1_TEN | DAC_Trigger) ;
}
/* Write to DAC CHxCR1 */
*(uint8_t*)((uint16_t)(DAC_BASE + CR1_Offset + tmpreg2)) = (uint8_t)tmpreg;
}
/**
* @brief Configures the selected DAC channel.
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @param sConfig: DAC configuration structure.
* @param Channel: The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC Channel1 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel)
{
uint32_t tmpreg1 = 0, tmpreg2 = 0;
/* Check the DAC parameters */
assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger));
assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer));
assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger));
assert_param(IS_DAC_CHANNEL(Channel));
/* Process locked */
__HAL_LOCK(hdac);
/* Change DAC state */
hdac->State = HAL_DAC_STATE_BUSY;
/* Get the DAC CR value */
tmpreg1 = DAC->CR;
/* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
// tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) << Channel);
tmpreg1 &= ~(((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) << Channel);
/* Configure for the selected DAC channel: buffer output, trigger */
/* Set TSELx and TENx bits according to DAC_Trigger value */
/* Set BOFFx bit according to DAC_OutputBuffer value */
tmpreg2 = (sConfig->DAC_Trigger | sConfig->DAC_OutputBuffer);
/* Calculate CR register value depending on DAC_Channel */
tmpreg1 |= tmpreg2 << Channel;
/* Write to DAC CR */
DAC->CR = tmpreg1;
/* Disable wave generation */
// DAC->CR &= ~(DAC_CR_WAVE1 << Channel);
/* Change DAC state */
hdac->State = HAL_DAC_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hdac);
/* Return function status */
return HAL_OK;
}
/**
* @brief Configures the selected DAC channel.
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @param sConfig: DAC configuration structure.
* @param Channel: The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC Channel1 selected
* @arg DAC_CHANNEL_2: DAC Channel2 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel)
{
uint32_t tmpreg1 = 0, tmpreg2 = 0;
uint32_t tickstart = 0;
/* Check the DAC parameters */
assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger));
assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer));
assert_param(IS_DAC_CHIP_CONNECTION(sConfig->DAC_ConnectOnChipPeripheral));
assert_param(IS_DAC_TRIMMING(sConfig->DAC_UserTrimming));
if ((sConfig->DAC_UserTrimming) == DAC_TRIMMING_USER)
{
assert_param(IS_DAC_TRIMMINGVALUE(sConfig->DAC_TrimmingValue));
}
assert_param(IS_DAC_SAMPLEANDHOLD(sConfig->DAC_SampleAndHold));
if ((sConfig->DAC_SampleAndHold) == DAC_SAMPLEANDHOLD_ENABLE)
{
assert_param(IS_DAC_SAMPLETIME(sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime));
assert_param(IS_DAC_HOLDTIME(sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime));
assert_param(IS_DAC_REFRESHTIME(sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime));
}
assert_param(IS_DAC_CHANNEL(Channel));
/* Process locked */
__HAL_LOCK(hdac);
/* Change DAC state */
hdac->State = HAL_DAC_STATE_BUSY;
if(sConfig->DAC_SampleAndHold == DAC_SAMPLEANDHOLD_ENABLE)
/* Sample on old configuration */
{
/* SampleTime */
if (Channel == DAC_CHANNEL_1)
{
/* Get timeout */
tickstart = HAL_GetTick();
/* SHSR1 can be written when BWST1 equals RESET */
while (((hdac->Instance->SR) & DAC_SR_BWST1)!= RESET)
{
/* Check for the Timeout */
if((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG)
{
/* Update error code */
SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT);
/* Change the DMA state */
hdac->State = HAL_DAC_STATE_TIMEOUT;
return HAL_TIMEOUT;
}
}
HAL_Delay(1);
hdac->Instance->SHSR1 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime;
}
else /* Channel 2 */
{
/* SHSR2 can be written when BWST2 equals RESET */
while (((hdac->Instance->SR) & DAC_SR_BWST2)!= RESET)
{
/* Check for the Timeout */
if((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG)
{
/* Update error code */
SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT);
/* Change the DMA state */
hdac->State = HAL_DAC_STATE_TIMEOUT;
return HAL_TIMEOUT;
}
}
HAL_Delay(1);
hdac->Instance->SHSR2 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime;
}
/* HoldTime */
hdac->Instance->SHHR = (sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime)<<Channel;
/* RefreshTime */
hdac->Instance->SHRR = (sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime)<<Channel;
}
if(sConfig->DAC_UserTrimming == DAC_TRIMMING_USER)
/* USER TRIMMING */
{
/* Get the DAC CCR value */
tmpreg1 = hdac->Instance->CCR;
/* Clear trimming value */
tmpreg1 &= ~(((uint32_t)(DAC_CCR_OTRIM1)) << Channel);
/* Configure for the selected trimming offset */
tmpreg2 = sConfig->DAC_TrimmingValue;
/* Calculate CCR register value depending on DAC_Channel */
tmpreg1 |= tmpreg2 << Channel;
/* Write to DAC CCR */
hdac->Instance->CCR = tmpreg1;
}
/* else factory trimming is used (factory setting are available at reset)*/
/* SW Nothing has nothing to do */
/* Get the DAC MCR value */
tmpreg1 = hdac->Instance->MCR;
/* Clear DAC_MCR_MODE2_0, DAC_MCR_MODE2_1 and DAC_MCR_MODE2_2 bits */
tmpreg1 &= ~(((uint32_t)(DAC_MCR_MODE1)) << Channel);
/* Configure for the selected DAC channel: mode, buffer output & on chip peripheral connect */
tmpreg2 = (sConfig->DAC_SampleAndHold | sConfig->DAC_OutputBuffer | sConfig->DAC_ConnectOnChipPeripheral);
/* Calculate MCR register value depending on DAC_Channel */
tmpreg1 |= tmpreg2 << Channel;
/* Write to DAC MCR */
hdac->Instance->MCR = tmpreg1;
/* DAC in normal operating mode hence clear DAC_CR_CENx bit */
CLEAR_BIT (hdac->Instance->CR, DAC_CR_CEN1 << Channel);
/* Get the DAC CR value */
tmpreg1 = hdac->Instance->CR;
/* Clear TENx, TSELx, WAVEx and MAMPx bits */
tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1)) << Channel);
/* Configure for the selected DAC channel: trigger */
/* Set TSELx and TENx bits according to DAC_Trigger value */
tmpreg2 = (sConfig->DAC_Trigger);
/* Calculate CR register value depending on DAC_Channel */
tmpreg1 |= tmpreg2 << Channel;
/* Write to DAC CR */
hdac->Instance->CR = tmpreg1;
/* Disable wave generation */
hdac->Instance->CR &= ~(DAC_CR_WAVE1 << Channel);
/* Change DAC state */
hdac->State = HAL_DAC_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hdac);
/* Return function status */
return HAL_OK;
}
HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel)
{
uint32_t tmpreg1 = 0U, tmpreg2 = 0U;
/* Check the DAC parameters */
assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger));
#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
if ((hdac->Instance == DAC1) && (Channel == DAC_CHANNEL_1))
{
/* Output Buffer (BOFF1) control */
assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer));
}
else /* DAC1 channel 2U & DAC2 channel 1U */
{
/* Output Switch (OUTEN) control */
assert_param(IS_DAC_OUTPUT_SWITCH_STATE(sConfig->DAC_OutputSwitch));
}
#else
assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer));
#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
assert_param(IS_DAC_CHANNEL(Channel));
/* Process locked */
__HAL_LOCK(hdac);
/* Change DAC state */
hdac->State = HAL_DAC_STATE_BUSY;
/* Get the DAC CR value */
tmpreg1 = hdac->Instance->CR;
/* Clear BOFFx-OUTENx, TENx, TSELx, WAVEx and MAMPx bits */
/* Configure for the selected DAC channel: buffer output or switch output, trigger */
/* Set TSELx and TENx bits according to DAC_Trigger value */
/* Set BOFFx bit according to DAC_OutputBuffer value OR */
/* Set OUTEN bit according to DAC_OutputSwitch value */
#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
if ((hdac->Instance == DAC1) && (Channel == DAC_CHANNEL_1))
{
/* Output Buffer (BOFF1) control */
tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) << Channel);
tmpreg2 = (sConfig->DAC_Trigger | sConfig->DAC_OutputBuffer);
}
else /* DAC1 channel 2U & DAC2 channel 1U */
{
/* Output Switch (OUTEN) control */
tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_OUTEN1)) << Channel);
tmpreg2 = (sConfig->DAC_Trigger | sConfig->DAC_OutputSwitch);
}
#else
tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) << Channel);
tmpreg2 = (sConfig->DAC_Trigger | sConfig->DAC_OutputBuffer);
#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
/* Calculate CR register value depending on DAC_Channel */
tmpreg1 |= tmpreg2 << Channel;
/* Write to DAC CR */
hdac->Instance->CR = tmpreg1;
/* Disable wave generation */
hdac->Instance->CR &= ~(DAC_CR_WAVE1 << Channel);
/* Change DAC state */
hdac->State = HAL_DAC_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hdac);
/* Return function status */
return HAL_OK;
}
