/* pass zero in check_rpl if no needed selector RPL checking for
non-conforming segments */
void BX_CPU_C::check_cs(bx_descriptor_t *descriptor, Bit16u cs_raw, Bit8u check_rpl, Bit8u check_cpl)
{
// descriptor AR byte must indicate code segment else #GP(selector)
if (descriptor->valid==0 || descriptor->segment==0 ||
IS_DATA_SEGMENT(descriptor->type))
{
BX_ERROR(("check_cs: not a valid code segment !"));
exception(BX_GP_EXCEPTION, cs_raw & 0xfffc, 0);
}
#if BX_SUPPORT_X86_64
if (descriptor->u.segment.l)
{
if (! BX_CPU_THIS_PTR efer.lma) {
BX_PANIC(("check_cs: attempt to jump to long mode without enabling EFER.LMA !"));
}
if (descriptor->u.segment.d_b) {
BX_ERROR(("check_cs: Both L and D bits enabled for segment descriptor !"));
exception(BX_GP_EXCEPTION, cs_raw & 0xfffc, 0);
}
}
#endif
// if non-conforming, code segment descriptor DPL must = CPL else #GP(selector)
if (IS_CODE_SEGMENT_NON_CONFORMING(descriptor->type)) {
if (descriptor->dpl != check_cpl) {
BX_ERROR(("check_cs: non-conforming code seg descriptor dpl != cpl"));
exception(BX_GP_EXCEPTION, cs_raw & 0xfffc, 0);
}
/* RPL of destination selector must be <= CPL else #GP(selector) */
if (check_rpl > check_cpl) {
BX_ERROR(("check_cs: non-conforming code seg selector rpl > cpl"));
exception(BX_GP_EXCEPTION, cs_raw & 0xfffc, 0);
}
}
// if conforming, then code segment descriptor DPL must <= CPL else #GP(selector)
else {
if (descriptor->dpl > check_cpl) {
BX_ERROR(("check_cs: conforming code seg descriptor dpl > cpl"));
exception(BX_GP_EXCEPTION, cs_raw & 0xfffc, 0);
}
}
// code segment must be present else #NP(selector)
if (! descriptor->p) {
BX_ERROR(("check_cs: code segment not present !"));
exception(BX_NP_EXCEPTION, cs_raw & 0xfffc, 0);
}
}
void BX_CPU_C::task_switch_load_selector(bx_segment_reg_t *seg,
bx_selector_t *selector, Bit16u raw_selector, Bit8u cs_rpl)
{
bx_descriptor_t descriptor;
Bit32u dword1, dword2;
// NULL selector is OK, will leave cache invalid
if ((raw_selector & 0xfffc) != 0)
{
bx_bool good = fetch_raw_descriptor2(selector, &dword1, &dword2);
if (!good) {
BX_ERROR(("task_switch(%s): bad selector fetch !", strseg(seg)));
exception(BX_TS_EXCEPTION, raw_selector & 0xfffc, 0);
}
parse_descriptor(dword1, dword2, &descriptor);
/* AR byte must indicate data or readable code segment else #TS(selector) */
if (descriptor.segment==0 || (IS_CODE_SEGMENT(descriptor.type) &&
IS_CODE_SEGMENT_READABLE(descriptor.type) == 0))
{
BX_ERROR(("task_switch(%s): not data or readable code !", strseg(seg)));
exception(BX_TS_EXCEPTION, raw_selector & 0xfffc, 0);
}
/* If data or non-conforming code, then both the RPL and the CPL
* must be less than or equal to DPL in AR byte else #GP(selector) */
if (IS_DATA_SEGMENT(descriptor.type) ||
IS_CODE_SEGMENT_NON_CONFORMING(descriptor.type))
{
if ((selector->rpl > descriptor.dpl) || (cs_rpl > descriptor.dpl)) {
BX_ERROR(("load_seg_reg(%s): RPL & CPL must be <= DPL", strseg(seg)));
exception(BX_TS_EXCEPTION, raw_selector & 0xfffc, 0);
}
}
if (! IS_PRESENT(descriptor)) {
BX_ERROR(("task_switch(%s): descriptor not present !", strseg(seg)));
exception(BX_NP_EXCEPTION, raw_selector & 0xfffc, 0);
}
// All checks pass, fill in shadow cache
seg->cache = descriptor;
}
}
void BX_CPU_C::long_mode_int(Bit8u vector, unsigned soft_int, bx_bool push_error, Bit16u error_code)
{
bx_descriptor_t gate_descriptor, cs_descriptor;
bx_selector_t cs_selector;
// interrupt vector must be within IDT table limits,
// else #GP(vector*8 + 2 + EXT)
if ((vector*16 + 15) > BX_CPU_THIS_PTR idtr.limit) {
BX_ERROR(("interrupt(long mode): vector must be within IDT table limits, IDT.limit = 0x%x", BX_CPU_THIS_PTR idtr.limit));
exception(BX_GP_EXCEPTION, vector*8 + 2);
}
Bit64u desctmp1 = system_read_qword(BX_CPU_THIS_PTR idtr.base + vector*16);
Bit64u desctmp2 = system_read_qword(BX_CPU_THIS_PTR idtr.base + vector*16 + 8);
if (desctmp2 & BX_CONST64(0x00001F0000000000)) {
BX_ERROR(("interrupt(long mode): IDT entry extended attributes DWORD4 TYPE != 0"));
exception(BX_GP_EXCEPTION, vector*8 + 2);
}
Bit32u dword1 = GET32L(desctmp1);
Bit32u dword2 = GET32H(desctmp1);
Bit32u dword3 = GET32L(desctmp2);
parse_descriptor(dword1, dword2, &gate_descriptor);
if ((gate_descriptor.valid==0) || gate_descriptor.segment)
{
BX_ERROR(("interrupt(long mode): gate descriptor is not valid sys seg"));
exception(BX_GP_EXCEPTION, vector*8 + 2);
}
// descriptor AR byte must indicate interrupt gate, trap gate,
// or task gate, else #GP(vector*8 + 2 + EXT)
if (gate_descriptor.type != BX_386_INTERRUPT_GATE &&
gate_descriptor.type != BX_386_TRAP_GATE)
{
BX_ERROR(("interrupt(long mode): unsupported gate type %u",
(unsigned) gate_descriptor.type));
exception(BX_GP_EXCEPTION, vector*8 + 2);
}
// if software interrupt, then gate descripor DPL must be >= CPL,
// else #GP(vector * 8 + 2 + EXT)
if (soft_int && gate_descriptor.dpl < CPL)
{
BX_ERROR(("interrupt(long mode): soft_int && gate.dpl < CPL"));
exception(BX_GP_EXCEPTION, vector*8 + 2);
}
// Gate must be present, else #NP(vector * 8 + 2 + EXT)
if (! IS_PRESENT(gate_descriptor)) {
BX_ERROR(("interrupt(long mode): gate.p == 0"));
exception(BX_NP_EXCEPTION, vector*8 + 2);
}
Bit16u gate_dest_selector = gate_descriptor.u.gate.dest_selector;
Bit64u gate_dest_offset = ((Bit64u)dword3 << 32) |
gate_descriptor.u.gate.dest_offset;
unsigned ist = gate_descriptor.u.gate.param_count & 0x7;
// examine CS selector and descriptor given in gate descriptor
// selector must be non-null else #GP(EXT)
if ((gate_dest_selector & 0xfffc) == 0) {
BX_ERROR(("int_trap_gate(long mode): selector null"));
exception(BX_GP_EXCEPTION, 0);
}
parse_selector(gate_dest_selector, &cs_selector);
// selector must be within its descriptor table limits
// else #GP(selector+EXT)
fetch_raw_descriptor(&cs_selector, &dword1, &dword2, BX_GP_EXCEPTION);
parse_descriptor(dword1, dword2, &cs_descriptor);
// descriptor AR byte must indicate code seg
// and code segment descriptor DPL<=CPL, else #GP(selector+EXT)
if (cs_descriptor.valid==0 || cs_descriptor.segment==0 ||
IS_DATA_SEGMENT(cs_descriptor.type) ||
cs_descriptor.dpl > CPL)
{
BX_ERROR(("interrupt(long mode): not accessible or not code segment"));
exception(BX_GP_EXCEPTION, cs_selector.value & 0xfffc);
}
// check that it's a 64 bit segment
if (! IS_LONG64_SEGMENT(cs_descriptor) || cs_descriptor.u.segment.d_b)
{
BX_ERROR(("interrupt(long mode): must be 64 bit segment"));
exception(BX_GP_EXCEPTION, cs_selector.value & 0xfffc);
}
// segment must be present, else #NP(selector + EXT)
if (! IS_PRESENT(cs_descriptor)) {
BX_ERROR(("interrupt(long mode): segment not present"));
exception(BX_NP_EXCEPTION, cs_selector.value & 0xfffc);
}
Bit64u RSP_for_cpl_x;
Bit64u old_CS = BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value;
Bit64u old_RIP = RIP;
Bit64u old_SS = BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.value;
Bit64u old_RSP = RSP;
// if code segment is non-conforming and DPL < CPL then
// INTERRUPT TO INNER PRIVILEGE:
if (IS_CODE_SEGMENT_NON_CONFORMING(cs_descriptor.type) && cs_descriptor.dpl < CPL)
{
BX_DEBUG(("interrupt(long mode): INTERRUPT TO INNER PRIVILEGE"));
// check selector and descriptor for new stack in current TSS
if (ist > 0) {
BX_DEBUG(("interrupt(long mode): trap to IST, vector = %d", ist));
RSP_for_cpl_x = get_RSP_from_TSS(ist+3);
}
else {
RSP_for_cpl_x = get_RSP_from_TSS(cs_descriptor.dpl);
}
// align stack
RSP_for_cpl_x &= BX_CONST64(0xfffffffffffffff0);
// push old stack long pointer onto new stack
write_new_stack_qword_64(RSP_for_cpl_x - 8, cs_descriptor.dpl, old_SS);
write_new_stack_qword_64(RSP_for_cpl_x - 16, cs_descriptor.dpl, old_RSP);
write_new_stack_qword_64(RSP_for_cpl_x - 24, cs_descriptor.dpl, read_eflags());
// push long pointer to return address onto new stack
write_new_stack_qword_64(RSP_for_cpl_x - 32, cs_descriptor.dpl, old_CS);
write_new_stack_qword_64(RSP_for_cpl_x - 40, cs_descriptor.dpl, old_RIP);
RSP_for_cpl_x -= 40;
if (push_error) {
RSP_for_cpl_x -= 8;
write_new_stack_qword_64(RSP_for_cpl_x, cs_descriptor.dpl, error_code);
}
// load CS:RIP (guaranteed to be in 64 bit mode)
branch_far64(&cs_selector, &cs_descriptor, gate_dest_offset, cs_descriptor.dpl);
// set up null SS descriptor
load_null_selector(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS], cs_descriptor.dpl);
}
else if(IS_CODE_SEGMENT_CONFORMING(cs_descriptor.type) || cs_descriptor.dpl==CPL)
{
// if code segment is conforming OR code segment DPL = CPL then
// INTERRUPT TO SAME PRIVILEGE LEVEL:
BX_DEBUG(("interrupt(long mode): INTERRUPT TO SAME PRIVILEGE"));
// check selector and descriptor for new stack in current TSS
if (ist > 0) {
BX_DEBUG(("interrupt(long mode): trap to IST, vector = %d", ist));
RSP_for_cpl_x = get_RSP_from_TSS(ist+3);
}
else {
RSP_for_cpl_x = RSP;
}
// align stack
RSP_for_cpl_x &= BX_CONST64(0xfffffffffffffff0);
// push flags onto stack
// push current CS selector onto stack
// push return offset onto stack
write_new_stack_qword_64(RSP_for_cpl_x - 8, cs_descriptor.dpl, old_SS);
write_new_stack_qword_64(RSP_for_cpl_x - 16, cs_descriptor.dpl, old_RSP);
write_new_stack_qword_64(RSP_for_cpl_x - 24, cs_descriptor.dpl, read_eflags());
// push long pointer to return address onto new stack
write_new_stack_qword_64(RSP_for_cpl_x - 32, cs_descriptor.dpl, old_CS);
write_new_stack_qword_64(RSP_for_cpl_x - 40, cs_descriptor.dpl, old_RIP);
RSP_for_cpl_x -= 40;
if (push_error) {
RSP_for_cpl_x -= 8;
write_new_stack_qword_64(RSP_for_cpl_x, cs_descriptor.dpl, error_code);
}
// set the RPL field of CS to CPL
branch_far64(&cs_selector, &cs_descriptor, gate_dest_offset, CPL);
}
else {
BX_ERROR(("interrupt(long mode): bad descriptor type %u (CS.DPL=%u CPL=%u)",
(unsigned) cs_descriptor.type, (unsigned) cs_descriptor.dpl, (unsigned) CPL));
exception(BX_GP_EXCEPTION, cs_selector.value & 0xfffc);
}
RSP = RSP_for_cpl_x;
// if interrupt gate then set IF to 0
if (!(gate_descriptor.type & 1)) // even is int-gate
BX_CPU_THIS_PTR clear_IF();
BX_CPU_THIS_PTR clear_TF();
//BX_CPU_THIS_PTR clear_VM(); // VM is clear in long mode
BX_CPU_THIS_PTR clear_RF();
BX_CPU_THIS_PTR clear_NT();
}
void BX_CPU_C::protected_mode_int(Bit8u vector, unsigned soft_int, bx_bool push_error, Bit16u error_code)
{
bx_descriptor_t gate_descriptor, cs_descriptor;
bx_selector_t cs_selector;
Bit16u raw_tss_selector;
bx_selector_t tss_selector;
bx_descriptor_t tss_descriptor;
Bit16u gate_dest_selector;
Bit32u gate_dest_offset;
// interrupt vector must be within IDT table limits,
// else #GP(vector*8 + 2 + EXT)
if ((vector*8 + 7) > BX_CPU_THIS_PTR idtr.limit) {
BX_ERROR(("interrupt(): vector must be within IDT table limits, IDT.limit = 0x%x", BX_CPU_THIS_PTR idtr.limit));
exception(BX_GP_EXCEPTION, vector*8 + 2);
}
Bit64u desctmp = system_read_qword(BX_CPU_THIS_PTR idtr.base + vector*8);
Bit32u dword1 = GET32L(desctmp);
Bit32u dword2 = GET32H(desctmp);
parse_descriptor(dword1, dword2, &gate_descriptor);
if ((gate_descriptor.valid==0) || gate_descriptor.segment) {
BX_ERROR(("interrupt(): gate descriptor is not valid sys seg (vector=0x%02x)", vector));
exception(BX_GP_EXCEPTION, vector*8 + 2);
}
// descriptor AR byte must indicate interrupt gate, trap gate,
// or task gate, else #GP(vector*8 + 2 + EXT)
switch (gate_descriptor.type) {
case BX_TASK_GATE:
case BX_286_INTERRUPT_GATE:
case BX_286_TRAP_GATE:
case BX_386_INTERRUPT_GATE:
case BX_386_TRAP_GATE:
break;
default:
BX_ERROR(("interrupt(): gate.type(%u) != {5,6,7,14,15}",
(unsigned) gate_descriptor.type));
exception(BX_GP_EXCEPTION, vector*8 + 2);
}
// if software interrupt, then gate descripor DPL must be >= CPL,
// else #GP(vector * 8 + 2 + EXT)
if (soft_int && gate_descriptor.dpl < CPL) {
BX_ERROR(("interrupt(): soft_int && (gate.dpl < CPL)"));
exception(BX_GP_EXCEPTION, vector*8 + 2);
}
// Gate must be present, else #NP(vector * 8 + 2 + EXT)
if (! IS_PRESENT(gate_descriptor)) {
BX_ERROR(("interrupt(): gate not present"));
exception(BX_NP_EXCEPTION, vector*8 + 2);
}
switch (gate_descriptor.type) {
case BX_TASK_GATE:
// examine selector to TSS, given in task gate descriptor
raw_tss_selector = gate_descriptor.u.taskgate.tss_selector;
parse_selector(raw_tss_selector, &tss_selector);
// must specify global in the local/global bit,
// else #GP(TSS selector)
if (tss_selector.ti) {
BX_ERROR(("interrupt(): tss_selector.ti=1 from gate descriptor - #GP(tss_selector)"));
exception(BX_GP_EXCEPTION, raw_tss_selector & 0xfffc);
}
// index must be within GDT limits, else #TS(TSS selector)
fetch_raw_descriptor(&tss_selector, &dword1, &dword2, BX_GP_EXCEPTION);
parse_descriptor(dword1, dword2, &tss_descriptor);
// AR byte must specify available TSS,
// else #GP(TSS selector)
if (tss_descriptor.valid==0 || tss_descriptor.segment) {
BX_ERROR(("interrupt(): TSS selector points to invalid or bad TSS - #GP(tss_selector)"));
exception(BX_GP_EXCEPTION, raw_tss_selector & 0xfffc);
}
if (tss_descriptor.type!=BX_SYS_SEGMENT_AVAIL_286_TSS &&
tss_descriptor.type!=BX_SYS_SEGMENT_AVAIL_386_TSS)
{
BX_ERROR(("interrupt(): TSS selector points to bad TSS - #GP(tss_selector)"));
exception(BX_GP_EXCEPTION, raw_tss_selector & 0xfffc);
}
// TSS must be present, else #NP(TSS selector)
if (! IS_PRESENT(tss_descriptor)) {
BX_ERROR(("interrupt(): TSS descriptor.p == 0"));
exception(BX_NP_EXCEPTION, raw_tss_selector & 0xfffc);
}
// switch tasks with nesting to TSS
task_switch(0, &tss_selector, &tss_descriptor,
BX_TASK_FROM_INT, dword1, dword2);
RSP_SPECULATIVE;
// if interrupt was caused by fault with error code
// stack limits must allow push of 2 more bytes, else #SS(0)
// push error code onto stack
if (push_error) {
if (tss_descriptor.type >= 9) // TSS386
push_32(error_code);
else
push_16(error_code);
}
// instruction pointer must be in CS limit, else #GP(0)
if (EIP > BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled) {
BX_ERROR(("interrupt(): EIP > CS.limit"));
exception(BX_GP_EXCEPTION, 0);
}
RSP_COMMIT;
return;
case BX_286_INTERRUPT_GATE:
case BX_286_TRAP_GATE:
case BX_386_INTERRUPT_GATE:
case BX_386_TRAP_GATE:
gate_dest_selector = gate_descriptor.u.gate.dest_selector;
gate_dest_offset = gate_descriptor.u.gate.dest_offset;
// examine CS selector and descriptor given in gate descriptor
// selector must be non-null else #GP(EXT)
if ((gate_dest_selector & 0xfffc) == 0) {
BX_ERROR(("int_trap_gate(): selector null"));
exception(BX_GP_EXCEPTION, 0);
}
parse_selector(gate_dest_selector, &cs_selector);
// selector must be within its descriptor table limits
// else #GP(selector+EXT)
fetch_raw_descriptor(&cs_selector, &dword1, &dword2, BX_GP_EXCEPTION);
parse_descriptor(dword1, dword2, &cs_descriptor);
// descriptor AR byte must indicate code seg
// and code segment descriptor DPL<=CPL, else #GP(selector+EXT)
if (cs_descriptor.valid==0 || cs_descriptor.segment==0 ||
IS_DATA_SEGMENT(cs_descriptor.type) ||
cs_descriptor.dpl > CPL)
{
BX_ERROR(("interrupt(): not accessible or not code segment cs=0x%04x", cs_selector.value));
exception(BX_GP_EXCEPTION, cs_selector.value & 0xfffc);
}
// segment must be present, else #NP(selector + EXT)
if (! IS_PRESENT(cs_descriptor)) {
BX_ERROR(("interrupt(): segment not present"));
exception(BX_NP_EXCEPTION, cs_selector.value & 0xfffc);
}
// if code segment is non-conforming and DPL < CPL then
// INTERRUPT TO INNER PRIVILEGE
if(IS_CODE_SEGMENT_NON_CONFORMING(cs_descriptor.type) && cs_descriptor.dpl < CPL)
{
Bit16u old_SS, old_CS, SS_for_cpl_x;
Bit32u ESP_for_cpl_x, old_EIP, old_ESP;
bx_descriptor_t ss_descriptor;
bx_selector_t ss_selector;
int is_v8086_mode = v8086_mode();
BX_DEBUG(("interrupt(): INTERRUPT TO INNER PRIVILEGE"));
// check selector and descriptor for new stack in current TSS
get_SS_ESP_from_TSS(cs_descriptor.dpl,
&SS_for_cpl_x, &ESP_for_cpl_x);
if (is_v8086_mode && cs_descriptor.dpl != 0) {
// if code segment DPL != 0 then #GP(new code segment selector)
BX_ERROR(("interrupt(): code segment DPL(%d) != 0 in v8086 mode", cs_descriptor.dpl));
exception(BX_GP_EXCEPTION, cs_selector.value & 0xfffc);
}
// Selector must be non-null else #TS(EXT)
if ((SS_for_cpl_x & 0xfffc) == 0) {
BX_ERROR(("interrupt(): SS selector null"));
exception(BX_TS_EXCEPTION, 0); /* TS(ext) */
}
// selector index must be within its descriptor table limits
// else #TS(SS selector + EXT)
parse_selector(SS_for_cpl_x, &ss_selector);
// fetch 2 dwords of descriptor; call handles out of limits checks
fetch_raw_descriptor(&ss_selector, &dword1, &dword2, BX_TS_EXCEPTION);
parse_descriptor(dword1, dword2, &ss_descriptor);
// selector rpl must = dpl of code segment,
// else #TS(SS selector + ext)
if (ss_selector.rpl != cs_descriptor.dpl) {
BX_ERROR(("interrupt(): SS.rpl != CS.dpl"));
exception(BX_TS_EXCEPTION, SS_for_cpl_x & 0xfffc);
}
// stack seg DPL must = DPL of code segment,
// else #TS(SS selector + ext)
if (ss_descriptor.dpl != cs_descriptor.dpl) {
BX_ERROR(("interrupt(): SS.dpl != CS.dpl"));
exception(BX_TS_EXCEPTION, SS_for_cpl_x & 0xfffc);
}
// descriptor must indicate writable data segment,
// else #TS(SS selector + EXT)
if (ss_descriptor.valid==0 || ss_descriptor.segment==0 ||
IS_CODE_SEGMENT(ss_descriptor.type) ||
!IS_DATA_SEGMENT_WRITEABLE(ss_descriptor.type))
{
BX_ERROR(("interrupt(): SS is not writable data segment"));
exception(BX_TS_EXCEPTION, SS_for_cpl_x & 0xfffc);
}
// seg must be present, else #SS(SS selector + ext)
if (! IS_PRESENT(ss_descriptor)) {
BX_ERROR(("interrupt(): SS not present"));
exception(BX_SS_EXCEPTION, SS_for_cpl_x & 0xfffc);
}
// IP must be within CS segment boundaries, else #GP(0)
if (gate_dest_offset > cs_descriptor.u.segment.limit_scaled) {
BX_ERROR(("interrupt(): gate EIP > CS.limit"));
exception(BX_GP_EXCEPTION, 0);
}
old_ESP = ESP;
old_SS = BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.value;
old_EIP = EIP;
old_CS = BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value;
// Prepare new stack segment
bx_segment_reg_t new_stack;
new_stack.selector = ss_selector;
new_stack.cache = ss_descriptor;
new_stack.selector.rpl = cs_descriptor.dpl;
// add cpl to the selector value
new_stack.selector.value = (0xfffc & new_stack.selector.value) |
new_stack.selector.rpl;
if (ss_descriptor.u.segment.d_b) {
Bit32u temp_ESP = ESP_for_cpl_x;
if (is_v8086_mode)
{
if (gate_descriptor.type>=14) { // 386 int/trap gate
write_new_stack_dword_32(&new_stack, temp_ESP-4, cs_descriptor.dpl,
BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].selector.value);
write_new_stack_dword_32(&new_stack, temp_ESP-8, cs_descriptor.dpl,
BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].selector.value);
write_new_stack_dword_32(&new_stack, temp_ESP-12, cs_descriptor.dpl,
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].selector.value);
write_new_stack_dword_32(&new_stack, temp_ESP-16, cs_descriptor.dpl,
BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].selector.value);
temp_ESP -= 16;
}
else {
write_new_stack_word_32(&new_stack, temp_ESP-2, cs_descriptor.dpl,
BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].selector.value);
write_new_stack_word_32(&new_stack, temp_ESP-4, cs_descriptor.dpl,
BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].selector.value);
write_new_stack_word_32(&new_stack, temp_ESP-6, cs_descriptor.dpl,
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].selector.value);
write_new_stack_word_32(&new_stack, temp_ESP-8, cs_descriptor.dpl,
BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].selector.value);
temp_ESP -= 8;
}
}
if (gate_descriptor.type>=14) { // 386 int/trap gate
// push long pointer to old stack onto new stack
write_new_stack_dword_32(&new_stack, temp_ESP-4, cs_descriptor.dpl, old_SS);
write_new_stack_dword_32(&new_stack, temp_ESP-8, cs_descriptor.dpl, old_ESP);
write_new_stack_dword_32(&new_stack, temp_ESP-12, cs_descriptor.dpl, read_eflags());
write_new_stack_dword_32(&new_stack, temp_ESP-16, cs_descriptor.dpl, old_CS);
write_new_stack_dword_32(&new_stack, temp_ESP-20, cs_descriptor.dpl, old_EIP);
temp_ESP -= 20;
if (push_error) {
temp_ESP -= 4;
write_new_stack_dword_32(&new_stack, temp_ESP, cs_descriptor.dpl, error_code);
}
}
else { // 286 int/trap gate
// push long pointer to old stack onto new stack
write_new_stack_word_32(&new_stack, temp_ESP-2, cs_descriptor.dpl, old_SS);
write_new_stack_word_32(&new_stack, temp_ESP-4, cs_descriptor.dpl, (Bit16u) old_ESP);
write_new_stack_word_32(&new_stack, temp_ESP-6, cs_descriptor.dpl, (Bit16u) read_eflags());
write_new_stack_word_32(&new_stack, temp_ESP-8, cs_descriptor.dpl, old_CS);
write_new_stack_word_32(&new_stack, temp_ESP-10, cs_descriptor.dpl, (Bit16u) old_EIP);
temp_ESP -= 10;
if (push_error) {
temp_ESP -= 2;
write_new_stack_word_32(&new_stack, temp_ESP, cs_descriptor.dpl, error_code);
}
}
ESP = temp_ESP;
}
else {
Bit16u temp_SP = (Bit16u) ESP_for_cpl_x;
if (is_v8086_mode)
{
if (gate_descriptor.type>=14) { // 386 int/trap gate
write_new_stack_dword_32(&new_stack, (Bit16u)(temp_SP-4), cs_descriptor.dpl,
BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].selector.value);
write_new_stack_dword_32(&new_stack, (Bit16u)(temp_SP-8), cs_descriptor.dpl,
BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].selector.value);
write_new_stack_dword_32(&new_stack, (Bit16u)(temp_SP-12), cs_descriptor.dpl,
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].selector.value);
write_new_stack_dword_32(&new_stack, (Bit16u)(temp_SP-16), cs_descriptor.dpl,
BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].selector.value);
temp_SP -= 16;
}
else {
write_new_stack_word_32(&new_stack, (Bit16u)(temp_SP-2), cs_descriptor.dpl,
BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].selector.value);
write_new_stack_word_32(&new_stack, (Bit16u)(temp_SP-4), cs_descriptor.dpl,
BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].selector.value);
write_new_stack_word_32(&new_stack, (Bit16u)(temp_SP-6), cs_descriptor.dpl,
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].selector.value);
write_new_stack_word_32(&new_stack, (Bit16u)(temp_SP-8), cs_descriptor.dpl,
BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].selector.value);
temp_SP -= 8;
}
}
if (gate_descriptor.type>=14) { // 386 int/trap gate
// push long pointer to old stack onto new stack
write_new_stack_dword_32(&new_stack, (Bit16u)(temp_SP-4), cs_descriptor.dpl, old_SS);
write_new_stack_dword_32(&new_stack, (Bit16u)(temp_SP-8), cs_descriptor.dpl, old_ESP);
write_new_stack_dword_32(&new_stack, (Bit16u)(temp_SP-12), cs_descriptor.dpl, read_eflags());
write_new_stack_dword_32(&new_stack, (Bit16u)(temp_SP-16), cs_descriptor.dpl, old_CS);
write_new_stack_dword_32(&new_stack, (Bit16u)(temp_SP-20), cs_descriptor.dpl, old_EIP);
temp_SP -= 20;
if (push_error) {
temp_SP -= 4;
write_new_stack_dword_32(&new_stack, temp_SP, cs_descriptor.dpl, error_code);
}
}
else { // 286 int/trap gate
// push long pointer to old stack onto new stack
write_new_stack_word_32(&new_stack, (Bit16u)(temp_SP-2), cs_descriptor.dpl, old_SS);
write_new_stack_word_32(&new_stack, (Bit16u)(temp_SP-4), cs_descriptor.dpl, (Bit16u) old_ESP);
write_new_stack_word_32(&new_stack, (Bit16u)(temp_SP-6), cs_descriptor.dpl, (Bit16u) read_eflags());
write_new_stack_word_32(&new_stack, (Bit16u)(temp_SP-8), cs_descriptor.dpl, old_CS);
write_new_stack_word_32(&new_stack, (Bit16u)(temp_SP-10), cs_descriptor.dpl, (Bit16u) old_EIP);
temp_SP -= 10;
if (push_error) {
temp_SP -= 2;
write_new_stack_word_32(&new_stack, temp_SP, cs_descriptor.dpl, error_code);
}
}
SP = temp_SP;
}
// load new CS:eIP values from gate
// set CPL to new code segment DPL
// set RPL of CS to CPL
load_cs(&cs_selector, &cs_descriptor, cs_descriptor.dpl);
// load new SS:eSP values from TSS
load_ss(&ss_selector, &ss_descriptor, cs_descriptor.dpl);
if (is_v8086_mode)
{
BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].cache.valid = 0;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].selector.value = 0;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].cache.valid = 0;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].selector.value = 0;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.valid = 0;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].selector.value = 0;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.valid = 0;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].selector.value = 0;
}
}
else
{
BX_DEBUG(("interrupt(): INTERRUPT TO SAME PRIVILEGE"));
if (v8086_mode() && (IS_CODE_SEGMENT_CONFORMING(cs_descriptor.type) || cs_descriptor.dpl != 0)) {
// if code segment DPL != 0 then #GP(new code segment selector)
BX_ERROR(("interrupt(): code segment conforming or DPL(%d) != 0 in v8086 mode", cs_descriptor.dpl));
exception(BX_GP_EXCEPTION, cs_selector.value & 0xfffc);
}
// EIP must be in CS limit else #GP(0)
if (gate_dest_offset > cs_descriptor.u.segment.limit_scaled) {
BX_ERROR(("interrupt(): IP > CS descriptor limit"));
exception(BX_GP_EXCEPTION, 0);
}
// push flags onto stack
// push current CS selector onto stack
// push return offset onto stack
if (gate_descriptor.type >= 14) { // 386 gate
push_32(read_eflags());
push_32(BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value);
push_32(EIP);
if (push_error)
push_32(error_code);
}
else { // 286 gate
push_16((Bit16u) read_eflags());
push_16(BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value);
push_16(IP);
if (push_error)
push_16(error_code);
}
// load CS:IP from gate
// load CS descriptor
// set the RPL field of CS to CPL
load_cs(&cs_selector, &cs_descriptor, CPL);
}
EIP = gate_dest_offset;
// if interrupt gate then set IF to 0
if (!(gate_descriptor.type & 1)) // even is int-gate
BX_CPU_THIS_PTR clear_IF();
BX_CPU_THIS_PTR clear_TF();
BX_CPU_THIS_PTR clear_NT();
BX_CPU_THIS_PTR clear_VM();
BX_CPU_THIS_PTR clear_RF();
return;
default:
BX_PANIC(("bad descriptor type in interrupt()!"));
break;
}
}
void BX_CPU_C::task_switch(bx_selector_t *tss_selector,
bx_descriptor_t *tss_descriptor, unsigned source,
Bit32u dword1, Bit32u dword2)
{
Bit32u obase32; // base address of old TSS
Bit32u nbase32; // base address of new TSS
Bit32u temp32, newCR3;
Bit16u raw_cs_selector, raw_ss_selector, raw_ds_selector, raw_es_selector,
raw_fs_selector, raw_gs_selector, raw_ldt_selector;
Bit16u temp16, trap_word;
bx_selector_t cs_selector, ss_selector, ds_selector, es_selector,
fs_selector, gs_selector, ldt_selector;
bx_descriptor_t cs_descriptor, ss_descriptor, ldt_descriptor;
Bit32u old_TSS_max, new_TSS_max, old_TSS_limit, new_TSS_limit;
Bit32u newEAX, newECX, newEDX, newEBX;
Bit32u newESP, newEBP, newESI, newEDI;
Bit32u newEFLAGS, newEIP;
BX_DEBUG(("TASKING: ENTER"));
invalidate_prefetch_q();
// Discard any traps and inhibits for new context; traps will
// resume upon return.
BX_CPU_THIS_PTR debug_trap = 0;
BX_CPU_THIS_PTR inhibit_mask = 0;
// STEP 1: The following checks are made before calling task_switch(),
// for JMP & CALL only. These checks are NOT made for exceptions,
// interrupts & IRET.
//
// 1) TSS DPL must be >= CPL
// 2) TSS DPL must be >= TSS selector RPL
// 3) TSS descriptor is not busy.
// TSS must be present, else #NP(TSS selector)
if (tss_descriptor->p==0) {
BX_ERROR(("task_switch: TSS descriptor is not present !"));
exception(BX_NP_EXCEPTION, tss_selector->value & 0xfffc, 0);
}
// STEP 2: The processor performs limit-checking on the target TSS
// to verify that the TSS limit is greater than or equal
// to 67h (2Bh for 16-bit TSS).
// Gather info about old TSS
if (BX_CPU_THIS_PTR tr.cache.type <= 3) {
old_TSS_max = 0x29;
}
else {
old_TSS_max = 0x5F;
}
// Gather info about new TSS
if (tss_descriptor->type <= 3) { // {1,3}
new_TSS_max = 0x2B;
}
else { // tss_descriptor->type = {9,11}
new_TSS_max = 0x67;
}
obase32 = (Bit32u) BX_CPU_THIS_PTR tr.cache.u.system.base; // old TSS.base
old_TSS_limit = BX_CPU_THIS_PTR tr.cache.u.system.limit_scaled;
nbase32 = (Bit32u) tss_descriptor->u.system.base; // new TSS.base
new_TSS_limit = tss_descriptor->u.system.limit_scaled;
// TSS must have valid limit, else #TS(TSS selector)
if (tss_selector->ti || tss_descriptor->valid==0 ||
new_TSS_limit < new_TSS_max)
{
BX_ERROR(("task_switch(): new TSS limit < %d", new_TSS_max));
exception(BX_TS_EXCEPTION, tss_selector->value & 0xfffc, 0);
}
if (old_TSS_limit < old_TSS_max) {
BX_ERROR(("task_switch(): old TSS limit < %d", old_TSS_max));
exception(BX_TS_EXCEPTION, BX_CPU_THIS_PTR tr.selector.value & 0xfffc, 0);
}
if (obase32 == nbase32) {
BX_INFO(("TASK SWITCH: switching to the same TSS !"));
}
// Check that old TSS, new TSS, and all segment descriptors
// used in the task switch are paged in.
if (BX_CPU_THIS_PTR cr0.get_PG())
{
dtranslate_linear(obase32, 0, BX_WRITE); // new TSS
dtranslate_linear(obase32 + old_TSS_max, 0, BX_WRITE);
dtranslate_linear(nbase32, 0, BX_READ); // old TSS
dtranslate_linear(nbase32 + new_TSS_max, 0, BX_READ);
// ??? Humm, we check the new TSS region with READ above,
// but sometimes we need to write the link field in that
// region. We also sometimes update other fields, perhaps
// we need to WRITE check them here also, so that we keep
// the written state consistent (ie, we don't encounter a
// page fault in the middle).
if (source == BX_TASK_FROM_CALL_OR_INT)
{
dtranslate_linear(nbase32, 0, BX_WRITE);
dtranslate_linear(nbase32 + 2, 0, BX_WRITE);
}
}
// Privilege and busy checks done in CALL, JUMP, INT, IRET
// STEP 3: Save the current task state in the TSS. Up to this point,
// any exception that occurs aborts the task switch without
// changing the processor state.
/* save current machine state in old task's TSS */
Bit32u oldEFLAGS = read_eflags();
/* if moving to busy task, clear NT bit */
if (tss_descriptor->type == BX_SYS_SEGMENT_BUSY_286_TSS ||
tss_descriptor->type == BX_SYS_SEGMENT_BUSY_386_TSS)
{
oldEFLAGS &= ~EFlagsNTMask;
}
if (BX_CPU_THIS_PTR tr.cache.type <= 3) {
temp16 = IP; access_write_linear(Bit32u(obase32 + 14), 2, 0, &temp16);
temp16 = oldEFLAGS; access_write_linear(Bit32u(obase32 + 16), 2, 0, &temp16);
temp16 = AX; access_write_linear(Bit32u(obase32 + 18), 2, 0, &temp16);
temp16 = CX; access_write_linear(Bit32u(obase32 + 20), 2, 0, &temp16);
temp16 = DX; access_write_linear(Bit32u(obase32 + 22), 2, 0, &temp16);
temp16 = BX; access_write_linear(Bit32u(obase32 + 24), 2, 0, &temp16);
temp16 = SP; access_write_linear(Bit32u(obase32 + 26), 2, 0, &temp16);
temp16 = BP; access_write_linear(Bit32u(obase32 + 28), 2, 0, &temp16);
temp16 = SI; access_write_linear(Bit32u(obase32 + 30), 2, 0, &temp16);
temp16 = DI; access_write_linear(Bit32u(obase32 + 32), 2, 0, &temp16);
temp16 = BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].selector.value;
access_write_linear(Bit32u(obase32 + 34), 2, 0, &temp16);
temp16 = BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value;
access_write_linear(Bit32u(obase32 + 36), 2, 0, &temp16);
temp16 = BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.value;
access_write_linear(Bit32u(obase32 + 38), 2, 0, &temp16);
temp16 = BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].selector.value;
access_write_linear(Bit32u(obase32 + 40), 2, 0, &temp16);
}
else {
temp32 = EIP; access_write_linear(Bit32u(obase32 + 0x20), 4, 0, &temp32);
temp32 = oldEFLAGS; access_write_linear(Bit32u(obase32 + 0x24), 4, 0, &temp32);
temp32 = EAX; access_write_linear(Bit32u(obase32 + 0x28), 4, 0, &temp32);
temp32 = ECX; access_write_linear(Bit32u(obase32 + 0x2c), 4, 0, &temp32);
temp32 = EDX; access_write_linear(Bit32u(obase32 + 0x30), 4, 0, &temp32);
temp32 = EBX; access_write_linear(Bit32u(obase32 + 0x34), 4, 0, &temp32);
temp32 = ESP; access_write_linear(Bit32u(obase32 + 0x38), 4, 0, &temp32);
temp32 = EBP; access_write_linear(Bit32u(obase32 + 0x3c), 4, 0, &temp32);
temp32 = ESI; access_write_linear(Bit32u(obase32 + 0x40), 4, 0, &temp32);
temp32 = EDI; access_write_linear(Bit32u(obase32 + 0x44), 4, 0, &temp32);
temp16 = BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].selector.value;
access_write_linear(Bit32u(obase32 + 0x48), 2, 0, &temp16);
temp16 = BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value;
access_write_linear(Bit32u(obase32 + 0x4c), 2, 0, &temp16);
temp16 = BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.value;
access_write_linear(Bit32u(obase32 + 0x50), 2, 0, &temp16);
temp16 = BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].selector.value;
access_write_linear(Bit32u(obase32 + 0x54), 2, 0, &temp16);
temp16 = BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].selector.value;
access_write_linear(Bit32u(obase32 + 0x58), 2, 0, &temp16);
temp16 = BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].selector.value;
access_write_linear(Bit32u(obase32 + 0x5c), 2, 0, &temp16);
}
// effect on link field of new task
if (source == BX_TASK_FROM_CALL_OR_INT)
{
// set to selector of old task's TSS
temp16 = BX_CPU_THIS_PTR tr.selector.value;
access_write_linear(nbase32, 2, 0, &temp16);
}
// STEP 4: The new-task state is loaded from the TSS
if (tss_descriptor->type <= 3) {
access_read_linear(Bit32u(nbase32 + 14), 2, 0, BX_READ, &temp16);
newEIP = temp16; // zero out upper word
access_read_linear(Bit32u(nbase32 + 16), 2, 0, BX_READ, &temp16);
newEFLAGS = temp16;
// incoming TSS is 16bit:
// - upper word of general registers is set to 0xFFFF
// - upper word of eflags is zero'd
// - FS, GS are zero'd
// - upper word of eIP is zero'd
access_read_linear(Bit32u(nbase32 + 18), 2, 0, BX_READ, &temp16);
newEAX = 0xffff0000 | temp16;
access_read_linear(Bit32u(nbase32 + 20), 2, 0, BX_READ, &temp16);
newECX = 0xffff0000 | temp16;
access_read_linear(Bit32u(nbase32 + 22), 2, 0, BX_READ, &temp16);
newEDX = 0xffff0000 | temp16;
access_read_linear(Bit32u(nbase32 + 24), 2, 0, BX_READ, &temp16);
newEBX = 0xffff0000 | temp16;
access_read_linear(Bit32u(nbase32 + 26), 2, 0, BX_READ, &temp16);
newESP = 0xffff0000 | temp16;
access_read_linear(Bit32u(nbase32 + 28), 2, 0, BX_READ, &temp16);
newEBP = 0xffff0000 | temp16;
access_read_linear(Bit32u(nbase32 + 30), 2, 0, BX_READ, &temp16);
newESI = 0xffff0000 | temp16;
access_read_linear(Bit32u(nbase32 + 32), 2, 0, BX_READ, &temp16);
newEDI = 0xffff0000 | temp16;
access_read_linear(Bit32u(nbase32 + 34), 2, 0, BX_READ, &raw_es_selector);
access_read_linear(Bit32u(nbase32 + 36), 2, 0, BX_READ, &raw_cs_selector);
access_read_linear(Bit32u(nbase32 + 38), 2, 0, BX_READ, &raw_ss_selector);
access_read_linear(Bit32u(nbase32 + 40), 2, 0, BX_READ, &raw_ds_selector);
access_read_linear(Bit32u(nbase32 + 42), 2, 0, BX_READ, &raw_ldt_selector);
raw_fs_selector = 0; // use a NULL selector
raw_gs_selector = 0; // use a NULL selector
// No CR3 change for 286 task switch
newCR3 = 0; // keep compiler happy (not used)
trap_word = 0; // keep compiler happy (not used)
}
else {
if (BX_CPU_THIS_PTR cr0.get_PG())
access_read_linear(Bit32u(nbase32 + 0x1c), 4, 0, BX_READ, &newCR3);
else
newCR3 = 0; // keep compiler happy (not used)
access_read_linear(Bit32u(nbase32 + 0x20), 4, 0, BX_READ, &newEIP);
access_read_linear(Bit32u(nbase32 + 0x24), 4, 0, BX_READ, &newEFLAGS);
access_read_linear(Bit32u(nbase32 + 0x28), 4, 0, BX_READ, &newEAX);
access_read_linear(Bit32u(nbase32 + 0x2c), 4, 0, BX_READ, &newECX);
access_read_linear(Bit32u(nbase32 + 0x30), 4, 0, BX_READ, &newEDX);
access_read_linear(Bit32u(nbase32 + 0x34), 4, 0, BX_READ, &newEBX);
access_read_linear(Bit32u(nbase32 + 0x38), 4, 0, BX_READ, &newESP);
access_read_linear(Bit32u(nbase32 + 0x3c), 4, 0, BX_READ, &newEBP);
access_read_linear(Bit32u(nbase32 + 0x40), 4, 0, BX_READ, &newESI);
access_read_linear(Bit32u(nbase32 + 0x44), 4, 0, BX_READ, &newEDI);
access_read_linear(Bit32u(nbase32 + 0x48), 2, 0, BX_READ, &raw_es_selector);
access_read_linear(Bit32u(nbase32 + 0x4c), 2, 0, BX_READ, &raw_cs_selector);
access_read_linear(Bit32u(nbase32 + 0x50), 2, 0, BX_READ, &raw_ss_selector);
access_read_linear(Bit32u(nbase32 + 0x54), 2, 0, BX_READ, &raw_ds_selector);
access_read_linear(Bit32u(nbase32 + 0x58), 2, 0, BX_READ, &raw_fs_selector);
access_read_linear(Bit32u(nbase32 + 0x5c), 2, 0, BX_READ, &raw_gs_selector);
access_read_linear(Bit32u(nbase32 + 0x60), 2, 0, BX_READ, &raw_ldt_selector);
access_read_linear(Bit32u(nbase32 + 0x64), 2, 0, BX_READ, &trap_word);
}
// Step 5: If CALL, interrupt, or JMP, set busy flag in new task's
// TSS descriptor. If IRET, leave set.
if (source == BX_TASK_FROM_JUMP || source == BX_TASK_FROM_CALL_OR_INT)
{
// set the new task's busy bit
Bit32u laddr = (Bit32u)(BX_CPU_THIS_PTR gdtr.base) + (tss_selector->index<<3) + 4;
access_read_linear(laddr, 4, 0, BX_READ, &dword2);
dword2 |= 0x200;
access_write_linear(laddr, 4, 0, &dword2);
}
// Step 6: If JMP or IRET, clear busy bit in old task TSS descriptor,
// otherwise leave set.
// effect on Busy bit of old task
if (source == BX_TASK_FROM_JUMP || source == BX_TASK_FROM_IRET) {
// Bit is cleared
Bit32u laddr = (Bit32u) BX_CPU_THIS_PTR gdtr.base + (BX_CPU_THIS_PTR tr.selector.index<<3) + 4;
access_read_linear(laddr, 4, 0, BX_READ, &temp32);
temp32 &= ~0x200;
access_write_linear(laddr, 4, 0, &temp32);
}
//
// Commit point. At this point, we commit to the new
// context. If an unrecoverable error occurs in further
// processing, we complete the task switch without performing
// additional access and segment availablility checks and
// generate the appropriate exception prior to beginning
// execution of the new task.
//
// Step 7: Load the task register with the segment selector and
// descriptor for the new task TSS.
BX_CPU_THIS_PTR tr.selector = *tss_selector;
BX_CPU_THIS_PTR tr.cache = *tss_descriptor;
BX_CPU_THIS_PTR tr.cache.type |= 2; // mark TSS in TR as busy
// Step 8: Set TS flag in the CR0 image stored in the new task TSS.
BX_CPU_THIS_PTR cr0.set_TS(1);
// Task switch clears LE/L3/L2/L1/L0 in DR7
BX_CPU_THIS_PTR dr7 &= ~0x00000155;
// Step 9: If call or interrupt, set the NT flag in the eflags
// image stored in new task's TSS. If IRET or JMP,
// NT is restored from new TSS eflags image. (no change)
// effect on NT flag of new task
if (source == BX_TASK_FROM_CALL_OR_INT) {
newEFLAGS |= EFlagsNTMask; // NT flag is set
}
// Step 10: Load the new task (dynamic) state from new TSS.
// Any errors associated with loading and qualification of
// segment descriptors in this step occur in the new task's
// context. State loaded here includes LDTR, CR3,
// EFLAGS, EIP, general purpose registers, and segment
// descriptor parts of the segment registers.
if ((tss_descriptor->type >= 9) && BX_CPU_THIS_PTR cr0.get_PG()) {
// change CR3 only if it actually modified
if (newCR3 != BX_CPU_THIS_PTR cr3) {
SetCR3(newCR3); // Tell paging unit about new cr3 value
BX_DEBUG (("task_switch changing CR3 to 0x" FMT_PHY_ADDRX, newCR3));
BX_INSTR_TLB_CNTRL(BX_CPU_ID, BX_INSTR_TASKSWITCH, newCR3);
}
}
BX_CPU_THIS_PTR prev_rip = EIP = newEIP;
EAX = newEAX;
ECX = newECX;
EDX = newEDX;
EBX = newEBX;
ESP = newESP;
EBP = newEBP;
ESI = newESI;
EDI = newEDI;
writeEFlags(newEFLAGS, EFlagsValidMask);
// Fill in selectors for all segment registers. If errors
// occur later, the selectors will at least be loaded.
parse_selector(raw_cs_selector, &cs_selector);
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector = cs_selector;
parse_selector(raw_ds_selector, &ds_selector);
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].selector = ds_selector;
parse_selector(raw_es_selector, &es_selector);
BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].selector = es_selector;
parse_selector(raw_ss_selector, &ss_selector);
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector = ss_selector;
parse_selector(raw_fs_selector, &fs_selector);
BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].selector = fs_selector;
parse_selector(raw_gs_selector, &gs_selector);
BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].selector = gs_selector;
parse_selector(raw_ldt_selector, &ldt_selector);
BX_CPU_THIS_PTR ldtr.selector = ldt_selector;
// Start out with invalid descriptor caches, fill in
// with values only as they are validated.
BX_CPU_THIS_PTR ldtr.cache.valid = 0;
BX_CPU_THIS_PTR ldtr.cache.u.system.limit = 0;
BX_CPU_THIS_PTR ldtr.cache.u.system.limit_scaled = 0;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.valid = 0;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.valid = 0;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.valid = 0;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.valid = 0;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].cache.valid = 0;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].cache.valid = 0;
// LDTR
if (ldt_selector.ti) {
// LDT selector must be in GDT
BX_INFO(("task_switch(exception after commit point): bad LDT selector TI=1"));
exception(BX_TS_EXCEPTION, raw_ldt_selector & 0xfffc, 0);
}
if ((raw_ldt_selector & 0xfffc) != 0) {
bx_bool good = fetch_raw_descriptor2(&ldt_selector, &dword1, &dword2);
if (!good) {
BX_ERROR(("task_switch(exception after commit point): bad LDT fetch"));
exception(BX_TS_EXCEPTION, raw_ldt_selector & 0xfffc, 0);
}
parse_descriptor(dword1, dword2, &ldt_descriptor);
// LDT selector of new task is valid, else #TS(new task's LDT)
if (ldt_descriptor.valid==0 ||
ldt_descriptor.type!=BX_SYS_SEGMENT_LDT ||
ldt_descriptor.segment)
{
BX_ERROR(("task_switch(exception after commit point): bad LDT segment"));
exception(BX_TS_EXCEPTION, raw_ldt_selector & 0xfffc, 0);
}
// LDT of new task is present in memory, else #TS(new tasks's LDT)
if (! IS_PRESENT(ldt_descriptor)) {
BX_ERROR(("task_switch(exception after commit point): LDT not present"));
exception(BX_TS_EXCEPTION, raw_ldt_selector & 0xfffc, 0);
}
// All checks pass, fill in LDTR shadow cache
BX_CPU_THIS_PTR ldtr.cache = ldt_descriptor;
}
else {
// NULL LDT selector is OK, leave cache invalid
}
if (v8086_mode()) {
// load seg regs as 8086 registers
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS], raw_cs_selector);
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS], raw_ss_selector);
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS], raw_ds_selector);
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES], raw_es_selector);
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS], raw_fs_selector);
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS], raw_gs_selector);
}
else {
// SS
if ((raw_ss_selector & 0xfffc) != 0)
{
bx_bool good = fetch_raw_descriptor2(&ss_selector, &dword1, &dword2);
if (!good) {
BX_ERROR(("task_switch(exception after commit point): bad SS fetch"));
exception(BX_TS_EXCEPTION, raw_ss_selector & 0xfffc, 0);
}
parse_descriptor(dword1, dword2, &ss_descriptor);
// SS selector must be within its descriptor table limits else #TS(SS)
// SS descriptor AR byte must must indicate writable data segment,
// else #TS(SS)
if (ss_descriptor.valid==0 || ss_descriptor.segment==0 ||
IS_CODE_SEGMENT(ss_descriptor.type) ||
!IS_DATA_SEGMENT_WRITEABLE(ss_descriptor.type))
{
BX_ERROR(("task_switch(exception after commit point): SS not valid or writeable segment"));
exception(BX_TS_EXCEPTION, raw_ss_selector & 0xfffc, 0);
}
//
// Stack segment is present in memory, else #SS(new stack segment)
//
if (! IS_PRESENT(ss_descriptor)) {
BX_ERROR(("task_switch(exception after commit point): SS not present"));
exception(BX_SS_EXCEPTION, raw_ss_selector & 0xfffc, 0);
}
// Stack segment DPL matches CS.RPL, else #TS(new stack segment)
if (ss_descriptor.dpl != cs_selector.rpl) {
BX_ERROR(("task_switch(exception after commit point): SS.rpl != CS.RPL"));
exception(BX_TS_EXCEPTION, raw_ss_selector & 0xfffc, 0);
}
// Stack segment DPL matches selector RPL, else #TS(new stack segment)
if (ss_descriptor.dpl != ss_selector.rpl) {
BX_ERROR(("task_switch(exception after commit point): SS.dpl != SS.rpl"));
exception(BX_TS_EXCEPTION, raw_ss_selector & 0xfffc, 0);
}
// All checks pass, fill in shadow cache
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache = ss_descriptor;
}
else {
// SS selector is valid, else #TS(new stack segment)
BX_ERROR(("task_switch(exception after commit point): SS NULL"));
exception(BX_TS_EXCEPTION, raw_ss_selector & 0xfffc, 0);
}
// if new selector is not null then perform following checks:
// index must be within its descriptor table limits else #TS(selector)
// AR byte must indicate data or readable code else #TS(selector)
// if data or non-conforming code then:
// DPL must be >= CPL else #TS(selector)
// DPL must be >= RPL else #TS(selector)
// AR byte must indicate PRESENT else #NP(selector)
// load cache with new segment descriptor and set valid bit
// CS
if ((raw_cs_selector & 0xfffc) != 0) {
bx_bool good = fetch_raw_descriptor2(&cs_selector, &dword1, &dword2);
if (!good) {
BX_ERROR(("task_switch(exception after commit point): bad CS fetch"));
exception(BX_TS_EXCEPTION, raw_cs_selector & 0xfffc, 0);
}
parse_descriptor(dword1, dword2, &cs_descriptor);
// CS descriptor AR byte must indicate code segment else #TS(CS)
if (cs_descriptor.valid==0 || cs_descriptor.segment==0 ||
IS_DATA_SEGMENT(cs_descriptor.type))
{
BX_ERROR(("task_switch(exception after commit point): CS not valid executable seg"));
exception(BX_TS_EXCEPTION, raw_cs_selector & 0xfffc, 0);
}
// if non-conforming then DPL must equal selector RPL else #TS(CS)
if (IS_CODE_SEGMENT_NON_CONFORMING(cs_descriptor.type) &&
cs_descriptor.dpl != cs_selector.rpl)
{
BX_ERROR(("task_switch(exception after commit point): non-conforming: CS.dpl!=CS.RPL"));
exception(BX_TS_EXCEPTION, raw_cs_selector & 0xfffc, 0);
}
// if conforming then DPL must be <= selector RPL else #TS(CS)
if (IS_CODE_SEGMENT_CONFORMING(cs_descriptor.type) &&
cs_descriptor.dpl > cs_selector.rpl)
{
BX_ERROR(("task_switch(exception after commit point): conforming: CS.dpl>RPL"));
exception(BX_TS_EXCEPTION, raw_cs_selector & 0xfffc, 0);
}
// Code segment is present in memory, else #NP(new code segment)
if (! IS_PRESENT(cs_descriptor)) {
BX_ERROR(("task_switch(exception after commit point): CS.p==0"));
exception(BX_NP_EXCEPTION, raw_cs_selector & 0xfffc, 0);
}
// All checks pass, fill in shadow cache
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache = cs_descriptor;
}
else {
// If new cs selector is null #TS(CS)
BX_ERROR(("task_switch(exception after commit point): CS NULL"));
exception(BX_TS_EXCEPTION, raw_cs_selector & 0xfffc, 0);
}
#if BX_SUPPORT_ICACHE
BX_CPU_THIS_PTR updateFetchModeMask();
#endif
#if BX_CPU_LEVEL >= 4 && BX_SUPPORT_ALIGNMENT_CHECK
handleAlignmentCheck(); // task switch, CPL was modified
#endif
task_switch_load_selector(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS],
&ds_selector, raw_ds_selector, cs_selector.rpl);
task_switch_load_selector(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES],
&es_selector, raw_es_selector, cs_selector.rpl);
task_switch_load_selector(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS],
&fs_selector, raw_fs_selector, cs_selector.rpl);
task_switch_load_selector(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS],
&gs_selector, raw_gs_selector, cs_selector.rpl);
}
if ((tss_descriptor->type>=9) && (trap_word & 0x1)) {
BX_CPU_THIS_PTR debug_trap |= 0x00008000; // BT flag in DR6
BX_CPU_THIS_PTR async_event = 1; // so processor knows to check
BX_INFO(("task_switch: T bit set in new TSS"));
}
//
// Step 14: Begin execution of new task.
//
BX_DEBUG(("TASKING: LEAVE"));
}
BX_CPU_C::call_gate64(bx_selector_t *gate_selector)
{
bx_selector_t cs_selector;
Bit32u dword1, dword2, dword3;
bx_descriptor_t cs_descriptor;
bx_descriptor_t gate_descriptor;
// examine code segment selector in call gate descriptor
BX_DEBUG(("call_gate64: CALL 64bit call gate"));
fetch_raw_descriptor_64(gate_selector, &dword1, &dword2, &dword3, BX_GP_EXCEPTION);
parse_descriptor(dword1, dword2, &gate_descriptor);
Bit16u dest_selector = gate_descriptor.u.gate.dest_selector;
// selector must not be null else #GP(0)
if ((dest_selector & 0xfffc) == 0) {
BX_ERROR(("call_gate64: selector in gate null"));
exception(BX_GP_EXCEPTION, 0, 0);
}
parse_selector(dest_selector, &cs_selector);
// selector must be within its descriptor table limits,
// else #GP(code segment selector)
fetch_raw_descriptor(&cs_selector, &dword1, &dword2, BX_GP_EXCEPTION);
parse_descriptor(dword1, dword2, &cs_descriptor);
// find the RIP in the gate_descriptor
Bit64u new_RIP = gate_descriptor.u.gate.dest_offset;
new_RIP |= ((Bit64u)dword3 << 32);
// AR byte of selected descriptor must indicate code segment,
// else #GP(code segment selector)
// DPL of selected descriptor must be <= CPL,
// else #GP(code segment selector)
if (cs_descriptor.valid==0 || cs_descriptor.segment==0 ||
IS_DATA_SEGMENT(cs_descriptor.type) ||
cs_descriptor.dpl > CPL)
{
BX_ERROR(("call_gate64: selected descriptor is not code"));
exception(BX_GP_EXCEPTION, dest_selector & 0xfffc, 0);
}
// In long mode, only 64-bit call gates are allowed, and they must point
// to 64-bit code segments, else #GP(selector)
if (! IS_LONG64_SEGMENT(cs_descriptor) || cs_descriptor.u.segment.d_b)
{
BX_ERROR(("call_gate64: not 64-bit code segment in call gate 64"));
exception(BX_GP_EXCEPTION, dest_selector & 0xfffc, 0);
}
// code segment must be present else #NP(selector)
if (! IS_PRESENT(cs_descriptor)) {
BX_ERROR(("call_gate64: code segment not present !"));
exception(BX_NP_EXCEPTION, dest_selector & 0xfffc, 0);
}
Bit64u old_CS = BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value;
Bit64u old_RIP = RIP;
// CALL GATE TO MORE PRIVILEGE
// if non-conforming code segment and DPL < CPL then
if (IS_CODE_SEGMENT_NON_CONFORMING(cs_descriptor.type) && (cs_descriptor.dpl < CPL))
{
Bit64u RSP_for_cpl_x;
BX_DEBUG(("CALL GATE TO MORE PRIVILEGE LEVEL"));
// get new RSP for new privilege level from TSS
get_RSP_from_TSS(cs_descriptor.dpl, &RSP_for_cpl_x);
Bit64u old_SS = BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.value;
Bit64u old_RSP = RSP;
if (! IsCanonical(RSP_for_cpl_x)) {
// #SS(selector) when changing priviledge level
BX_ERROR(("call_gate64: canonical address failure %08x%08x",
GET32H(RSP_for_cpl_x), GET32L(RSP_for_cpl_x)));
exception(BX_SS_EXCEPTION, old_SS & 0xfffc, 0);
}
// push old stack long pointer onto new stack
write_new_stack_qword_64(RSP_for_cpl_x - 8, cs_descriptor.dpl, old_SS);
write_new_stack_qword_64(RSP_for_cpl_x - 16, cs_descriptor.dpl, old_RSP);
// push long pointer to return address onto new stack
write_new_stack_qword_64(RSP_for_cpl_x - 24, cs_descriptor.dpl, old_CS);
write_new_stack_qword_64(RSP_for_cpl_x - 32, cs_descriptor.dpl, old_RIP);
RSP_for_cpl_x -= 32;
// prepare new stack null SS selector
bx_selector_t ss_selector;
bx_descriptor_t ss_descriptor;
// set up a null descriptor
parse_selector(0, &ss_selector);
parse_descriptor(0, 0, &ss_descriptor);
// load CS:RIP (guaranteed to be in 64 bit mode)
branch_far64(&cs_selector, &cs_descriptor, new_RIP, cs_descriptor.dpl);
// set up null SS descriptor
load_ss(&ss_selector, &ss_descriptor, cs_descriptor.dpl);
RSP = RSP_for_cpl_x;
}
else
{
BX_DEBUG(("CALL GATE TO SAME PRIVILEGE"));
// push to 64-bit stack, switch to long64 guaranteed
write_new_stack_qword_64(RSP - 8, CPL, old_CS);
write_new_stack_qword_64(RSP - 16, CPL, old_RIP);
RSP -= 16;
// load CS:RIP (guaranteed to be in 64 bit mode)
branch_far64(&cs_selector, &cs_descriptor, new_RIP, CPL);
}
}
BX_CPU_C::call_protected(bxInstruction_c *i, Bit16u cs_raw, bx_address disp)
{
bx_selector_t cs_selector;
Bit32u dword1, dword2;
bx_descriptor_t cs_descriptor;
/* new cs selector must not be null, else #GP(0) */
if ((cs_raw & 0xfffc) == 0) {
BX_ERROR(("call_protected: CS selector null"));
exception(BX_GP_EXCEPTION, 0, 0);
}
parse_selector(cs_raw, &cs_selector);
// check new CS selector index within its descriptor limits,
// else #GP(new CS selector)
fetch_raw_descriptor(&cs_selector, &dword1, &dword2, BX_GP_EXCEPTION);
parse_descriptor(dword1, dword2, &cs_descriptor);
// examine AR byte of selected descriptor for various legal values
if (cs_descriptor.valid==0) {
BX_ERROR(("call_protected: invalid CS descriptor"));
exception(BX_GP_EXCEPTION, cs_raw & 0xfffc, 0);
}
if (cs_descriptor.segment) // normal segment
{
check_cs(&cs_descriptor, cs_raw, BX_SELECTOR_RPL(cs_raw), CPL);
#if BX_SUPPORT_X86_64
if (i->os64L()) {
// push return address onto stack (CS padded to 64bits)
push_64((Bit64u) BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value);
push_64(RIP);
}
else
#endif
if (i->os32L()) {
// push return address onto stack (CS padded to 32bits)
push_32((Bit32u) BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value);
push_32(EIP);
}
else {
// push return address onto stack
push_16(BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value);
push_16(IP);
}
// load code segment descriptor into CS cache
// load CS with new code segment selector
// set RPL of CS to CPL
branch_far64(&cs_selector, &cs_descriptor, disp, CPL);
return;
}
else { // gate & special segment
bx_descriptor_t gate_descriptor = cs_descriptor;
bx_selector_t gate_selector = cs_selector;
Bit32u new_EIP;
Bit16u dest_selector;
Bit16u raw_tss_selector;
bx_selector_t tss_selector;
bx_descriptor_t tss_descriptor;
Bit32u temp_eIP;
// descriptor DPL must be >= CPL else #GP(gate selector)
if (gate_descriptor.dpl < CPL) {
BX_ERROR(("call_protected: descriptor.dpl < CPL"));
exception(BX_GP_EXCEPTION, cs_raw & 0xfffc, 0);
}
// descriptor DPL must be >= gate selector RPL else #GP(gate selector)
if (gate_descriptor.dpl < gate_selector.rpl) {
BX_ERROR(("call_protected: descriptor.dpl < selector.rpl"));
exception(BX_GP_EXCEPTION, cs_raw & 0xfffc, 0);
}
#if BX_SUPPORT_X86_64
if (long_mode()) {
// call gate type is higher priority than non-present bit check
if (gate_descriptor.type != BX_386_CALL_GATE) {
BX_ERROR(("call_protected: gate type %u unsupported in long mode", (unsigned) gate_descriptor.type));
exception(BX_GP_EXCEPTION, cs_raw & 0xfffc, 0);
}
}
else
#endif
{
switch (gate_descriptor.type) {
case BX_SYS_SEGMENT_AVAIL_286_TSS:
case BX_SYS_SEGMENT_AVAIL_386_TSS:
case BX_TASK_GATE:
case BX_286_CALL_GATE:
case BX_386_CALL_GATE:
break;
default:
BX_ERROR(("call_protected(): gate.type(%u) unsupported", (unsigned) gate_descriptor.type));
exception(BX_GP_EXCEPTION, cs_raw & 0xfffc, 0);
}
}
// gate descriptor must be present else #NP(gate selector)
if (! IS_PRESENT(gate_descriptor)) {
BX_ERROR(("call_protected: gate not present"));
exception(BX_NP_EXCEPTION, cs_raw & 0xfffc, 0);
}
#if BX_SUPPORT_X86_64
if (long_mode()) {
call_gate64(&gate_selector);
return;
}
#endif
switch (gate_descriptor.type) {
case BX_SYS_SEGMENT_AVAIL_286_TSS:
case BX_SYS_SEGMENT_AVAIL_386_TSS:
if (gate_descriptor.type==BX_SYS_SEGMENT_AVAIL_286_TSS)
BX_DEBUG(("call_protected: 16bit available TSS"));
else
BX_DEBUG(("call_protected: 32bit available TSS"));
// SWITCH_TASKS _without_ nesting to TSS
task_switch(&gate_selector, &gate_descriptor,
BX_TASK_FROM_CALL_OR_INT, dword1, dword2);
// EIP must be in code seg limit, else #GP(0)
if (EIP > BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled) {
BX_ERROR(("call_protected: EIP not within CS limits"));
exception(BX_GP_EXCEPTION, 0, 0);
}
return;
case BX_TASK_GATE:
// examine selector to TSS, given in Task Gate descriptor
// must specify global in the local/global bit else #TS(TSS selector)
raw_tss_selector = gate_descriptor.u.taskgate.tss_selector;
parse_selector(raw_tss_selector, &tss_selector);
if (tss_selector.ti) {
BX_ERROR(("call_protected: tss_selector.ti=1"));
exception(BX_GP_EXCEPTION, raw_tss_selector & 0xfffc, 0);
}
// index must be within GDT limits else #TS(TSS selector)
fetch_raw_descriptor(&tss_selector, &dword1, &dword2, BX_GP_EXCEPTION);
parse_descriptor(dword1, dword2, &tss_descriptor);
// descriptor AR byte must specify available TSS
// else #GP(TSS selector)
if (tss_descriptor.valid==0 || tss_descriptor.segment) {
BX_ERROR(("call_protected: TSS selector points to bad TSS"));
exception(BX_GP_EXCEPTION, raw_tss_selector & 0xfffc, 0);
}
if (tss_descriptor.type!=BX_SYS_SEGMENT_AVAIL_286_TSS &&
tss_descriptor.type!=BX_SYS_SEGMENT_AVAIL_386_TSS)
{
BX_ERROR(("call_protected: TSS selector points to bad TSS"));
exception(BX_GP_EXCEPTION, raw_tss_selector & 0xfffc, 0);
}
// task state segment must be present, else #NP(tss selector)
if (! IS_PRESENT(tss_descriptor)) {
BX_ERROR(("call_protected: task descriptor.p == 0"));
exception(BX_NP_EXCEPTION, raw_tss_selector & 0xfffc, 0);
}
// SWITCH_TASKS without nesting to TSS
task_switch(&tss_selector, &tss_descriptor,
BX_TASK_FROM_CALL_OR_INT, dword1, dword2);
// EIP must be within code segment limit, else #TS(0)
if (BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.d_b)
temp_eIP = EIP;
else
temp_eIP = IP;
if (temp_eIP > BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled)
{
BX_ERROR(("call_protected: EIP > CS.limit"));
exception(BX_GP_EXCEPTION, 0, 0);
}
return;
case BX_286_CALL_GATE:
case BX_386_CALL_GATE:
// examine code segment selector in call gate descriptor
BX_DEBUG(("call_protected: call gate"));
dest_selector = gate_descriptor.u.gate.dest_selector;
new_EIP = gate_descriptor.u.gate.dest_offset;
// selector must not be null else #GP(0)
if ((dest_selector & 0xfffc) == 0) {
BX_ERROR(("call_protected: selector in gate null"));
exception(BX_GP_EXCEPTION, 0, 0);
}
parse_selector(dest_selector, &cs_selector);
// selector must be within its descriptor table limits,
// else #GP(code segment selector)
fetch_raw_descriptor(&cs_selector, &dword1, &dword2, BX_GP_EXCEPTION);
parse_descriptor(dword1, dword2, &cs_descriptor);
// AR byte of selected descriptor must indicate code segment,
// else #GP(code segment selector)
// DPL of selected descriptor must be <= CPL,
// else #GP(code segment selector)
if (cs_descriptor.valid==0 || cs_descriptor.segment==0 ||
IS_DATA_SEGMENT(cs_descriptor.type) ||
cs_descriptor.dpl > CPL)
{
BX_ERROR(("call_protected: selected descriptor is not code"));
exception(BX_GP_EXCEPTION, dest_selector & 0xfffc, 0);
}
// code segment must be present else #NP(selector)
if (! IS_PRESENT(cs_descriptor)) {
BX_ERROR(("call_protected: code segment not present !"));
exception(BX_NP_EXCEPTION, dest_selector & 0xfffc, 0);
}
// CALL GATE TO MORE PRIVILEGE
// if non-conforming code segment and DPL < CPL then
if (IS_CODE_SEGMENT_NON_CONFORMING(cs_descriptor.type) && (cs_descriptor.dpl < CPL))
{
Bit16u SS_for_cpl_x;
Bit32u ESP_for_cpl_x;
bx_selector_t ss_selector;
bx_descriptor_t ss_descriptor;
Bit16u return_SS, return_CS;
Bit32u return_ESP, return_EIP;
Bit16u parameter_word[32];
Bit32u parameter_dword[32];
BX_DEBUG(("CALL GATE TO MORE PRIVILEGE LEVEL"));
// get new SS selector for new privilege level from TSS
get_SS_ESP_from_TSS(cs_descriptor.dpl, &SS_for_cpl_x, &ESP_for_cpl_x);
// check selector & descriptor for new SS:
// selector must not be null, else #TS(0)
if ((SS_for_cpl_x & 0xfffc) == 0) {
BX_ERROR(("call_protected: new SS null"));
exception(BX_TS_EXCEPTION, 0, 0);
}
// selector index must be within its descriptor table limits,
// else #TS(SS selector)
parse_selector(SS_for_cpl_x, &ss_selector);
fetch_raw_descriptor(&ss_selector, &dword1, &dword2, BX_TS_EXCEPTION);
parse_descriptor(dword1, dword2, &ss_descriptor);
// selector's RPL must equal DPL of code segment,
// else #TS(SS selector)
if (ss_selector.rpl != cs_descriptor.dpl) {
BX_ERROR(("call_protected: SS selector.rpl != CS descr.dpl"));
exception(BX_TS_EXCEPTION, SS_for_cpl_x & 0xfffc, 0);
}
// stack segment DPL must equal DPL of code segment,
// else #TS(SS selector)
if (ss_descriptor.dpl != cs_descriptor.dpl) {
BX_ERROR(("call_protected: SS descr.rpl != CS descr.dpl"));
exception(BX_TS_EXCEPTION, SS_for_cpl_x & 0xfffc, 0);
}
// descriptor must indicate writable data segment,
// else #TS(SS selector)
if (ss_descriptor.valid==0 || ss_descriptor.segment==0 ||
IS_CODE_SEGMENT(ss_descriptor.type) ||
!IS_DATA_SEGMENT_WRITEABLE(ss_descriptor.type))
{
BX_ERROR(("call_protected: ss descriptor is not writable data seg"));
exception(BX_TS_EXCEPTION, SS_for_cpl_x & 0xfffc, 0);
}
// segment must be present, else #SS(SS selector)
if (! IS_PRESENT(ss_descriptor)) {
BX_ERROR(("call_protected: ss descriptor not present"));
exception(BX_SS_EXCEPTION, SS_for_cpl_x & 0xfffc, 0);
}
// get word count from call gate, mask to 5 bits
unsigned param_count = gate_descriptor.u.gate.param_count & 0x1f;
// save return SS:eSP to be pushed on new stack
return_SS = BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.value;
if (BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.d_b)
return_ESP = ESP;
else
return_ESP = SP;
// save return CS:eIP to be pushed on new stack
return_CS = BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value;
if (cs_descriptor.u.segment.d_b)
return_EIP = EIP;
else
return_EIP = IP;
if (gate_descriptor.type==BX_286_CALL_GATE) {
for (unsigned i=0; i<param_count; i++) {
parameter_word[i] = read_virtual_word(BX_SEG_REG_SS, return_ESP + i*2);
}
}
else {
for (unsigned i=0; i<param_count; i++) {
parameter_dword[i] = read_virtual_dword(BX_SEG_REG_SS, return_ESP + i*4);
}
}
// Prepare new stack segment
bx_segment_reg_t new_stack;
new_stack.selector = ss_selector;
new_stack.cache = ss_descriptor;
new_stack.selector.rpl = cs_descriptor.dpl;
// add cpl to the selector value
new_stack.selector.value = (0xfffc & new_stack.selector.value) |
new_stack.selector.rpl;
/* load new SS:SP value from TSS */
if (ss_descriptor.u.segment.d_b) {
Bit32u temp_ESP = ESP_for_cpl_x;
// push pointer of old stack onto new stack
if (gate_descriptor.type==BX_386_CALL_GATE) {
write_new_stack_dword_32(&new_stack, temp_ESP-4, cs_descriptor.dpl, return_SS);
write_new_stack_dword_32(&new_stack, temp_ESP-8, cs_descriptor.dpl, return_ESP);
temp_ESP -= 8;
for (unsigned i=param_count; i>0; i--) {
temp_ESP -= 4;
write_new_stack_dword_32(&new_stack, temp_ESP, cs_descriptor.dpl, parameter_dword[i-1]);
}
// push return address onto new stack
write_new_stack_dword_32(&new_stack, temp_ESP-4, cs_descriptor.dpl, return_CS);
write_new_stack_dword_32(&new_stack, temp_ESP-8, cs_descriptor.dpl, return_EIP);
temp_ESP -= 8;
}
else {
write_new_stack_word_32(&new_stack, temp_ESP-2, cs_descriptor.dpl, return_SS);
write_new_stack_word_32(&new_stack, temp_ESP-4, cs_descriptor.dpl, (Bit16u) return_ESP);
temp_ESP -= 4;
for (unsigned i=param_count; i>0; i--) {
temp_ESP -= 2;
write_new_stack_word_32(&new_stack, temp_ESP, cs_descriptor.dpl, parameter_word[i-1]);
}
// push return address onto new stack
write_new_stack_word_32(&new_stack, temp_ESP-2, cs_descriptor.dpl, return_CS);
write_new_stack_word_32(&new_stack, temp_ESP-4, cs_descriptor.dpl, (Bit16u) return_EIP);
temp_ESP -= 4;
}
ESP = temp_ESP;
}
else {
Bit16u temp_SP = (Bit16u) ESP_for_cpl_x;
// push pointer of old stack onto new stack
if (gate_descriptor.type==BX_386_CALL_GATE) {
write_new_stack_dword_32(&new_stack, (Bit16u)(temp_SP-4), cs_descriptor.dpl, return_SS);
write_new_stack_dword_32(&new_stack, (Bit16u)(temp_SP-8), cs_descriptor.dpl, return_ESP);
temp_SP -= 8;
for (unsigned i=param_count; i>0; i--) {
temp_SP -= 4;
write_new_stack_dword_32(&new_stack, temp_SP, cs_descriptor.dpl, parameter_dword[i-1]);
}
// push return address onto new stack
write_new_stack_dword_32(&new_stack, (Bit16u)(temp_SP-4), cs_descriptor.dpl, return_CS);
write_new_stack_dword_32(&new_stack, (Bit16u)(temp_SP-8), cs_descriptor.dpl, return_EIP);
temp_SP -= 8;
}
else {
write_new_stack_word_32(&new_stack, (Bit16u)(temp_SP-2), cs_descriptor.dpl, return_SS);
write_new_stack_word_32(&new_stack, (Bit16u)(temp_SP-4), cs_descriptor.dpl, (Bit16u) return_ESP);
temp_SP -= 4;
for (unsigned i=param_count; i>0; i--) {
temp_SP -= 2;
write_new_stack_word_32(&new_stack, temp_SP, cs_descriptor.dpl, parameter_word[i-1]);
}
// push return address onto new stack
write_new_stack_word_32(&new_stack, (Bit16u)(temp_SP-2), cs_descriptor.dpl, return_CS);
write_new_stack_word_32(&new_stack, (Bit16u)(temp_SP-4), cs_descriptor.dpl, (Bit16u) return_EIP);
temp_SP -= 4;
}
SP = temp_SP;
}
// new eIP must be in code segment limit else #GP(0)
if (new_EIP > cs_descriptor.u.segment.limit_scaled) {
BX_ERROR(("call_protected: EIP not within CS limits"));
exception(BX_GP_EXCEPTION, 0, 0);
}
/* load SS descriptor */
load_ss(&ss_selector, &ss_descriptor, cs_descriptor.dpl);
/* load new CS:IP value from gate */
/* load CS descriptor */
/* set CPL to stack segment DPL */
/* set RPL of CS to CPL */
load_cs(&cs_selector, &cs_descriptor, cs_descriptor.dpl);
EIP = new_EIP;
}
else // CALL GATE TO SAME PRIVILEGE
{
BX_DEBUG(("CALL GATE TO SAME PRIVILEGE"));
if (gate_descriptor.type == BX_386_CALL_GATE) {
// call gate 32bit, push return address onto stack
push_32(BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value);
push_32(EIP);
}
else {
// call gate 16bit, push return address onto stack
push_16(BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value);
push_16(IP);
}
// load CS:EIP from gate
// load code segment descriptor into CS register
// set RPL of CS to CPL
branch_far32(&cs_selector, &cs_descriptor, new_EIP, CPL);
}
return;
default: // can't get here
BX_PANIC(("call_protected: gate type %u unsupported", (unsigned) cs_descriptor.type));
exception(BX_GP_EXCEPTION, cs_raw & 0xfffc, 0);
}
}
}
void BX_CPP_AttrRegparmN(1) BX_CPU_C::call_gate(bx_descriptor_t *gate_descriptor)
{
bx_selector_t cs_selector;
Bit32u dword1, dword2;
bx_descriptor_t cs_descriptor;
// examine code segment selector in call gate descriptor
BX_DEBUG(("call_protected: call gate"));
Bit16u dest_selector = gate_descriptor->u.gate.dest_selector;
Bit32u new_EIP = gate_descriptor->u.gate.dest_offset;
// selector must not be null else #GP(0)
if ((dest_selector & 0xfffc) == 0) {
BX_ERROR(("call_protected: selector in gate null"));
exception(BX_GP_EXCEPTION, 0);
}
parse_selector(dest_selector, &cs_selector);
// selector must be within its descriptor table limits,
// else #GP(code segment selector)
fetch_raw_descriptor(&cs_selector, &dword1, &dword2, BX_GP_EXCEPTION);
parse_descriptor(dword1, dword2, &cs_descriptor);
// AR byte of selected descriptor must indicate code segment,
// else #GP(code segment selector)
// DPL of selected descriptor must be <= CPL,
// else #GP(code segment selector)
if (cs_descriptor.valid==0 || cs_descriptor.segment==0 ||
IS_DATA_SEGMENT(cs_descriptor.type) || cs_descriptor.dpl > CPL)
{
BX_ERROR(("call_protected: selected descriptor is not code"));
exception(BX_GP_EXCEPTION, dest_selector & 0xfffc);
}
// code segment must be present else #NP(selector)
if (! IS_PRESENT(cs_descriptor)) {
BX_ERROR(("call_protected: code segment not present !"));
exception(BX_NP_EXCEPTION, dest_selector & 0xfffc);
}
// CALL GATE TO MORE PRIVILEGE
// if non-conforming code segment and DPL < CPL then
if (IS_CODE_SEGMENT_NON_CONFORMING(cs_descriptor.type) && (cs_descriptor.dpl < CPL))
{
Bit16u SS_for_cpl_x;
Bit32u ESP_for_cpl_x;
bx_selector_t ss_selector;
bx_descriptor_t ss_descriptor;
Bit16u return_SS, return_CS;
Bit32u return_ESP, return_EIP;
BX_DEBUG(("CALL GATE TO MORE PRIVILEGE LEVEL"));
// get new SS selector for new privilege level from TSS
get_SS_ESP_from_TSS(cs_descriptor.dpl, &SS_for_cpl_x, &ESP_for_cpl_x);
// check selector & descriptor for new SS:
// selector must not be null, else #TS(0)
if ((SS_for_cpl_x & 0xfffc) == 0) {
BX_ERROR(("call_protected: new SS null"));
exception(BX_TS_EXCEPTION, 0);
}
// selector index must be within its descriptor table limits,
// else #TS(SS selector)
parse_selector(SS_for_cpl_x, &ss_selector);
fetch_raw_descriptor(&ss_selector, &dword1, &dword2, BX_TS_EXCEPTION);
parse_descriptor(dword1, dword2, &ss_descriptor);
// selector's RPL must equal DPL of code segment,
// else #TS(SS selector)
if (ss_selector.rpl != cs_descriptor.dpl) {
BX_ERROR(("call_protected: SS selector.rpl != CS descr.dpl"));
exception(BX_TS_EXCEPTION, SS_for_cpl_x & 0xfffc);
}
// stack segment DPL must equal DPL of code segment,
// else #TS(SS selector)
if (ss_descriptor.dpl != cs_descriptor.dpl) {
BX_ERROR(("call_protected: SS descr.rpl != CS descr.dpl"));
exception(BX_TS_EXCEPTION, SS_for_cpl_x & 0xfffc);
}
// descriptor must indicate writable data segment,
// else #TS(SS selector)
if (ss_descriptor.valid==0 || ss_descriptor.segment==0 ||
IS_CODE_SEGMENT(ss_descriptor.type) || !IS_DATA_SEGMENT_WRITEABLE(ss_descriptor.type))
{
BX_ERROR(("call_protected: ss descriptor is not writable data seg"));
exception(BX_TS_EXCEPTION, SS_for_cpl_x & 0xfffc);
}
// segment must be present, else #SS(SS selector)
if (! IS_PRESENT(ss_descriptor)) {
BX_ERROR(("call_protected: ss descriptor not present"));
exception(BX_SS_EXCEPTION, SS_for_cpl_x & 0xfffc);
}
// get word count from call gate, mask to 5 bits
unsigned param_count = gate_descriptor->u.gate.param_count & 0x1f;
// save return SS:eSP to be pushed on new stack
return_SS = BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.value;
if (BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.d_b)
return_ESP = ESP;
else
return_ESP = SP;
// save return CS:eIP to be pushed on new stack
return_CS = BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value;
if (cs_descriptor.u.segment.d_b)
return_EIP = EIP;
else
return_EIP = IP;
// Prepare new stack segment
bx_segment_reg_t new_stack;
new_stack.selector = ss_selector;
new_stack.cache = ss_descriptor;
new_stack.selector.rpl = cs_descriptor.dpl;
// add cpl to the selector value
new_stack.selector.value = (0xfffc & new_stack.selector.value) |
new_stack.selector.rpl;
/* load new SS:SP value from TSS */
if (ss_descriptor.u.segment.d_b) {
Bit32u temp_ESP = ESP_for_cpl_x;
// push pointer of old stack onto new stack
if (gate_descriptor->type==BX_386_CALL_GATE) {
write_new_stack_dword_32(&new_stack, temp_ESP-4, cs_descriptor.dpl, return_SS);
write_new_stack_dword_32(&new_stack, temp_ESP-8, cs_descriptor.dpl, return_ESP);
temp_ESP -= 8;
for (unsigned n=param_count; n>0; n--) {
temp_ESP -= 4;
Bit32u param = read_virtual_dword_32(BX_SEG_REG_SS, return_ESP + (n-1)*4);
write_new_stack_dword_32(&new_stack, temp_ESP, cs_descriptor.dpl, param);
}
// push return address onto new stack
write_new_stack_dword_32(&new_stack, temp_ESP-4, cs_descriptor.dpl, return_CS);
write_new_stack_dword_32(&new_stack, temp_ESP-8, cs_descriptor.dpl, return_EIP);
temp_ESP -= 8;
}
else {
write_new_stack_word_32(&new_stack, temp_ESP-2, cs_descriptor.dpl, return_SS);
write_new_stack_word_32(&new_stack, temp_ESP-4, cs_descriptor.dpl, (Bit16u) return_ESP);
temp_ESP -= 4;
for (unsigned n=param_count; n>0; n--) {
temp_ESP -= 2;
Bit16u param = read_virtual_word_32(BX_SEG_REG_SS, return_ESP + (n-1)*2);
write_new_stack_word_32(&new_stack, temp_ESP, cs_descriptor.dpl, param);
}
// push return address onto new stack
write_new_stack_word_32(&new_stack, temp_ESP-2, cs_descriptor.dpl, return_CS);
write_new_stack_word_32(&new_stack, temp_ESP-4, cs_descriptor.dpl, (Bit16u) return_EIP);
temp_ESP -= 4;
}
ESP = temp_ESP;
}
else {
Bit16u temp_SP = (Bit16u) ESP_for_cpl_x;
// push pointer of old stack onto new stack
if (gate_descriptor->type==BX_386_CALL_GATE) {
write_new_stack_dword_32(&new_stack, (Bit16u)(temp_SP-4), cs_descriptor.dpl, return_SS);
write_new_stack_dword_32(&new_stack, (Bit16u)(temp_SP-8), cs_descriptor.dpl, return_ESP);
temp_SP -= 8;
for (unsigned n=param_count; n>0; n--) {
temp_SP -= 4;
Bit32u param = read_virtual_dword_32(BX_SEG_REG_SS, return_ESP + (n-1)*4);
write_new_stack_dword_32(&new_stack, temp_SP, cs_descriptor.dpl, param);
}
// push return address onto new stack
write_new_stack_dword_32(&new_stack, (Bit16u)(temp_SP-4), cs_descriptor.dpl, return_CS);
write_new_stack_dword_32(&new_stack, (Bit16u)(temp_SP-8), cs_descriptor.dpl, return_EIP);
temp_SP -= 8;
}
else {
write_new_stack_word_32(&new_stack, (Bit16u)(temp_SP-2), cs_descriptor.dpl, return_SS);
write_new_stack_word_32(&new_stack, (Bit16u)(temp_SP-4), cs_descriptor.dpl, (Bit16u) return_ESP);
temp_SP -= 4;
for (unsigned n=param_count; n>0; n--) {
temp_SP -= 2;
Bit16u param = read_virtual_word_32(BX_SEG_REG_SS, return_ESP + (n-1)*2);
write_new_stack_word_32(&new_stack, temp_SP, cs_descriptor.dpl, param);
}
// push return address onto new stack
write_new_stack_word_32(&new_stack, (Bit16u)(temp_SP-2), cs_descriptor.dpl, return_CS);
write_new_stack_word_32(&new_stack, (Bit16u)(temp_SP-4), cs_descriptor.dpl, (Bit16u) return_EIP);
temp_SP -= 4;
}
SP = temp_SP;
}
// new eIP must be in code segment limit else #GP(0)
if (new_EIP > cs_descriptor.u.segment.limit_scaled) {
BX_ERROR(("call_protected: EIP not within CS limits"));
exception(BX_GP_EXCEPTION, 0);
}
/* load SS descriptor */
load_ss(&ss_selector, &ss_descriptor, cs_descriptor.dpl);
/* load new CS:IP value from gate */
/* load CS descriptor */
/* set CPL to stack segment DPL */
/* set RPL of CS to CPL */
load_cs(&cs_selector, &cs_descriptor, cs_descriptor.dpl);
EIP = new_EIP;
}
else // CALL GATE TO SAME PRIVILEGE
{
BX_DEBUG(("CALL GATE TO SAME PRIVILEGE"));
if (gate_descriptor->type == BX_386_CALL_GATE) {
// call gate 32bit, push return address onto stack
push_32(BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value);
push_32(EIP);
}
else {
// call gate 16bit, push return address onto stack
push_16(BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value);
push_16(IP);
}
// load CS:EIP from gate
// load code segment descriptor into CS register
// set RPL of CS to CPL
branch_far32(&cs_selector, &cs_descriptor, new_EIP, CPL);
}
}
