/**
* @brief Initializes the FSMC_PCCARD IO space Timing according to the specified
* parameters in the FSMC_NAND_PCC_TimingTypeDef
* @param Device Pointer to PCCARD device instance
* @param Timing Pointer to PCCARD timing structure
* @retval HAL status
*/
HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing)
{
uint32_t tmpr = 0U;
/* Check the parameters */
assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
/* Get FSMC_PCCARD device timing parameters */
tmpr = Device->PIO4;
/* Clear IOSET4, IOWAIT4, IOHOLD4 and IOHIZ4 bits */
tmpr &= ((uint32_t)~(FSMC_PIO4_IOSET4 | FSMC_PIO4_IOWAIT4 | FSMC_PIO4_IOHOLD4 | \
FSMC_PIO4_IOHIZ4));
/* Set FSMC_PCCARD device timing parameters */
tmpr |= (uint32_t)(Timing->SetupTime |\
((Timing->WaitSetupTime) << 8U) |\
((Timing->HoldSetupTime) << 16U) |\
((Timing->HiZSetupTime) << 24U));
Device->PIO4 = tmpr;
return HAL_OK;
}
/**
* @brief Initializes the FSMC_PCCARD Common space Timing according to the specified
* parameters in the FSMC_NAND_PCC_TimingTypeDef
* @param Device Pointer to PCCARD device instance
* @param Timing Pointer to PCCARD timing structure
* @retval HAL status
*/
HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing)
{
uint32_t tmpr = 0U;
/* Check the parameters */
assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
/* Get PCCARD common space timing register value */
tmpr = Device->PMEM4;
/* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */
tmpr &= ((uint32_t)~(FSMC_PMEM4_MEMSET4 | FSMC_PMEM4_MEMWAIT4 | FSMC_PMEM4_MEMHOLD4 | \
FSMC_PMEM4_MEMHIZ4));
/* Set PCCARD timing parameters */
tmpr |= (uint32_t)((Timing->SetupTime |\
((Timing->WaitSetupTime) << 8U) |\
(Timing->HoldSetupTime) << 16U) |\
((Timing->HiZSetupTime) << 24U));
Device->PMEM4 = tmpr;
return HAL_OK;
}
/**
* @brief Initializes the FSMC_PCCARD Attribute space Timing according to the specified
* parameters in the FSMC_NAND_PCC_TimingTypeDef
* @param Device Pointer to PCCARD device instance
* @param Timing Pointer to PCCARD timing structure
* @retval HAL status
*/
HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing)
{
uint32_t tmpr = 0U;
/* Check the parameters */
assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
/* Get PCCARD timing parameters */
tmpr = Device->PATT4;
/* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */
tmpr &= ((uint32_t)~(FSMC_PATT4_ATTSET4 | FSMC_PATT4_ATTWAIT4 | FSMC_PATT4_ATTHOLD4 | \
FSMC_PATT4_ATTHIZ4));
/* Set PCCARD timing parameters */
tmpr |= (uint32_t)(Timing->SetupTime |\
((Timing->WaitSetupTime) << 8U) |\
((Timing->HoldSetupTime) << 16U) |\
((Timing->HiZSetupTime) << 24U));
Device->PATT4 = tmpr;
return HAL_OK;
}
/**
* @brief Initializes the FSMC_NAND Attribute space Timing according to the specified
* parameters in the FSMC_NAND_PCC_TimingTypeDef
* @param Device: Pointer to NAND device instance
* @param Timing: Pointer to NAND timing structure
* @param Bank: NAND bank number
* @retval HAL status
*/
HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
{
/* Check the parameters */
assert_param(IS_FSMC_NAND_DEVICE(Device));
assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
assert_param(IS_FSMC_NAND_BANK(Bank));
if(Bank == FSMC_NAND_BANK2)
{
/* NAND bank 2 registers configuration */
MODIFY_REG(Device->PATT2, PATT_CLEAR_MASK, (Timing->SetupTime |\
((Timing->WaitSetupTime) << POSITION_VAL(FSMC_PATTx_ATTWAITx)) |\
((Timing->HoldSetupTime) << POSITION_VAL(FSMC_PATTx_ATTHOLDx)) |\
((Timing->HiZSetupTime) << POSITION_VAL(FSMC_PATTx_ATTHIZx))));
}
else
{
/* NAND bank 3 registers configuration */
MODIFY_REG(Device->PATT3, PATT_CLEAR_MASK, (Timing->SetupTime |\
((Timing->WaitSetupTime) << POSITION_VAL(FSMC_PATTx_ATTWAITx)) |\
((Timing->HoldSetupTime) << POSITION_VAL(FSMC_PATTx_ATTHOLDx)) |\
((Timing->HiZSetupTime) << POSITION_VAL(FSMC_PATTx_ATTHIZx))));
}
return HAL_OK;
}
/**
* @brief Initializes the FSMC_NAND Attribute space Timing according to the specified
* parameters in the FSMC_NAND_PCC_TimingTypeDef
* @param Device: Pointer to NAND device instance
* @param Timing: Pointer to NAND timing structure
* @param Bank: NAND bank number
* @retval HAL status
*/
HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
{
uint32_t tmppatt = 0;
/* Check the parameters */
assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
/* Set FSMC_NAND device timing parameters */
tmppatt = (uint32_t)(Timing->SetupTime |\
((Timing->WaitSetupTime) << 8) |\
((Timing->HoldSetupTime) << 16) |\
((Timing->HiZSetupTime) << 24)
);
if(Bank == FSMC_NAND_BANK2)
{
/* NAND bank 2 registers configuration */
Device->PATT2 = tmppatt;
}
else
{
/* NAND bank 3 registers configuration */
Device->PATT3 = tmppatt;
}
return HAL_OK;
}
/**
* @brief Initializes the FSMC_PCCARD IO space Timing according to the specified
* parameters in the FSMC_NAND_PCC_TimingTypeDef
* @param Device: Pointer to PCCARD device instance
* @param Timing: Pointer to PCCARD timing structure
* @retval HAL status
*/
HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing)
{
/* Check the parameters */
assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
/* Set FSMC_PCCARD device timing parameters */
Device->PIO4 = (uint32_t)((Timing->SetupTime |\
((Timing->WaitSetupTime) << 8) |\
(Timing->HoldSetupTime) << 16) |\
((Timing->HiZSetupTime) << 24)
);
return HAL_OK;
}
/**
* @brief Initializes the FSMC_NAND Attribute space Timing according to the specified
* parameters in the FSMC_NAND_PCC_TimingTypeDef
* @param Device Pointer to NAND device instance
* @param Timing Pointer to NAND timing structure
* @param Bank NAND bank number
* @retval HAL status
*/
HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
{
uint32_t tmpr = 0U;
/* Check the parameters */
assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
if(Bank == FSMC_NAND_BANK2)
{
/* Get the NAND bank 2 register value */
tmpr = Device->PATT2;
}
else
{
/* Get the NAND bank 3 register value */
tmpr = Device->PATT3;
}
/* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */
tmpr &= ((uint32_t)~(FSMC_PATT2_ATTSET2 | FSMC_PATT2_ATTWAIT2 | FSMC_PATT2_ATTHOLD2 | \
FSMC_PATT2_ATTHIZ2));
/* Set FSMC_NAND device timing parameters */
tmpr |= (uint32_t)(Timing->SetupTime |\
((Timing->WaitSetupTime) << 8U) |\
((Timing->HoldSetupTime) << 16U) |\
((Timing->HiZSetupTime) << 24U)
);
if(Bank == FSMC_NAND_BANK2)
{
/* NAND bank 2 registers configuration */
Device->PATT2 = tmpr;
}
else
{
/* NAND bank 3 registers configuration */
Device->PATT3 = tmpr;
}
return HAL_OK;
}
/**
* @brief Initializes the FSMC_NAND Common space Timing according to the specified
* parameters in the FSMC_NAND_PCC_TimingTypeDef
* @param Device: Pointer to NAND device instance
* @param Timing: Pointer to NAND timing structure
* @param Bank: NAND bank number
* @retval HAL status
*/
HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
{
uint32_t tmpr = 0;
/* Check the parameters */
assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
if(Bank == FSMC_NAND_BANK2)
{
/* Get the NAND bank 2 register value */
tmpr = Device->PMEM2;
}
else
{
/* Get the NAND bank 3 register value */
tmpr = Device->PMEM3;
}
/* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */
tmpr &= ((uint32_t)~(FSMC_PMEM2_MEMSET2 | FSMC_PMEM2_MEMWAIT2 | FSMC_PMEM2_MEMHOLD2 | \
FSMC_PMEM2_MEMHIZ2));
/* Set FSMC_NAND device timing parameters */
tmpr |= (uint32_t)(Timing->SetupTime |\
((Timing->WaitSetupTime) << 8) |\
((Timing->HoldSetupTime) << 16) |\
((Timing->HiZSetupTime) << 24)
);
if(Bank == FSMC_NAND_BANK2)
{
/* NAND bank 2 registers configuration */
Device->PMEM2 = tmpr;
}
else
{
/* NAND bank 3 registers configuration */
Device->PMEM3 = tmpr;
}
return HAL_OK;
}
/**
* @brief Initializes the FSMC_PCCARD IO space Timing according to the specified
* parameters in the FSMC_NAND_PCC_TimingTypeDef
* @param Device: Pointer to PCCARD device instance
* @param Timing: Pointer to PCCARD timing structure
* @retval HAL status
*/
HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing)
{
/* Check the parameters */
assert_param(IS_FSMC_PCCARD_DEVICE(Device));
assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
/* Set FSMC_PCCARD device timing parameters */
MODIFY_REG(Device->PIO4, PIO4_CLEAR_MASK, \
(Timing->SetupTime | \
(Timing->WaitSetupTime << POSITION_VAL(FSMC_PIO4_IOWAIT4)) | \
(Timing->HoldSetupTime << POSITION_VAL(FSMC_PIO4_IOHOLD4)) | \
(Timing->HiZSetupTime << POSITION_VAL(FSMC_PIO4_IOHIZ4))));
return HAL_OK;
}
/**
* @brief Initializes the FSMC_PCCARD Attribute space Timing according to the specified
* parameters in the FSMC_NAND_PCC_TimingTypeDef
* @param Device: Pointer to PCCARD device instance
* @param Timing: Pointer to PCCARD timing structure
* @retval HAL status
*/
HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing)
{
/* Check the parameters */
assert_param(IS_FSMC_PCCARD_DEVICE(Device));
assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
/* Set PCCARD timing parameters */
MODIFY_REG(Device->PATT4, PATT_CLEAR_MASK, \
(Timing->SetupTime | \
((Timing->WaitSetupTime) << POSITION_VAL(FSMC_PATTx_ATTWAITx)) | \
((Timing->HoldSetupTime) << POSITION_VAL(FSMC_PATTx_ATTHOLDx)) | \
((Timing->HiZSetupTime) << POSITION_VAL(FSMC_PATTx_ATTHIZx))));
return HAL_OK;
}
