void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT)
{
/* Check the parameters */
assert_param(IS_TIM_ALL_PERIPH(TIMx));
/* Clear the IT pending Bit */
TIMx->SR = (uint16_t)~TIM_IT;
}
/**
* @brief Check the specified TIM peripheral.
* @param TIMx: where x can be 1 to 17 to select the TIMx peripheral.
* @retval State: the state of the TIMx peripheral.
* This value can be: ENABLE or DISABLE.
*/
FunctionalState TIM_State(TIM_TypeDef* TIMx)
{
/* Check the parameters */
assert_param(IS_TIM_ALL_PERIPH(TIMx));
if ((TIMx->CR1 && TIM_CR1_CEN) != 0)
{
/* TIM Counter Enabled */
return ENABLE;
}
else
{
/* TIM Counter Disabled */
return DISABLE;
}
}
/*
* @brief set the specified TIM interrupts enable bit and return old state.
* @param TIMx: where x can be 1 to 17 to select the TIMx peripheral.
* @param TIM_IT: specifies the TIM interrupts sources to be enabled or disabled.
* This parameter can be any combination of the following values:
* @arg TIM_IT_Update: TIM update Interrupt source
* @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
* @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
* @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
* @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
* @arg TIM_IT_COM: TIM Commutation Interrupt source
* @arg TIM_IT_Trigger: TIM Trigger Interrupt source
* @arg TIM_IT_Break: TIM Break Interrupt source
* @note
* - TIM6 and TIM7 can only generate an update interrupt.
* - TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1,
* TIM_IT_CC2 or TIM_IT_Trigger.
* - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1.
* - TIM_IT_Break is used only with TIM1, TIM8 and TIM15.
* - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17.
*
* @param NewState: new state of the TIM interrupts.
* This parameter can be: ENABLE or DISABLE.
*
* @retval ENABLE or DISABLE.
* */
FunctionalState set_timx_int_enable_bit(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState new_state)
{
FunctionalState ret;
/* Check the parameters */
assert_param(IS_TIM_ALL_PERIPH(TIMx));
assert_param(IS_TIM_IT(TIM_IT));
assert_param(IS_FUNCTIONAL_STATE(new_state));
if (0 != (TIMx->DIER & TIM_IT))
ret = ENABLE;
else
ret = DISABLE;
if (new_state != DISABLE)
TIMx->DIER |= TIM_IT; /* Enable the Interrupt sources */
else
TIMx->DIER &= (uint16_t)~TIM_IT; /* Disable the Interrupt sources */
return ret;
}