/******************************************************************************* * Function Name : OTGD_FS_CoreInitDev * Description : Initialize the USB_OTG controller registers for device mode * Input : None * Output : None * Return : Status *******************************************************************************/ USB_OTG_Status OTGD_FS_CoreInitDev (void) { USB_OTG_Status status = USB_OTG_OK; USB_OTG_DEPCTLx_TypeDef depctl; USB_OTG_DCFG_TypeDef dcfg; USB_OTG_FIFOSIZ_TypeDef txfifosize0; USB_OTG_FIFOSIZ_TypeDef txfifosize; uint32_t i = 0; depctl.d32 = 0; dcfg.d32 = 0; txfifosize0.d32 = 0; txfifosize.d32 = 0; /* Set device speed */ InitDevSpeed (); /* Restart the Phy Clock */ USB_OTG_WRITE_REG32(USB_OTG_FS_regs.PCGCCTL, 0); /* Device configuration register */ dcfg.d32 = USB_OTG_READ_REG32( &USB_OTG_FS_regs.DEV->DCFG); dcfg.b.perfrint = DCFG_FRAME_INTERVAL_80; USB_OTG_WRITE_REG32( &USB_OTG_FS_regs.DEV->DCFG, dcfg.d32 ); /* set Rx FIFO size */ USB_OTG_WRITE_REG32( &USB_OTG_FS_regs.GREGS->GRXFSIZ, RX_FIFO_SIZE); /* EP0 TX*/ txfifosize0.b.depth = TX0_FIFO_SIZE; txfifosize0.b.startaddr = RX_FIFO_SIZE; USB_OTG_WRITE_REG32( &USB_OTG_FS_regs.GREGS->DIEPTXF0, txfifosize0.d32 ); /* EP1 TX*/ txfifosize.b.startaddr = txfifosize0.b.startaddr + txfifosize0.b.depth; txfifosize.b.depth = TX1_FIFO_SIZE; USB_OTG_WRITE_REG32( &USB_OTG_FS_regs.GREGS->DIEPTXFx[0], txfifosize.d32 ); /* EP2 TX*/ txfifosize.b.startaddr += txfifosize.b.depth; txfifosize.b.depth = TX2_FIFO_SIZE; USB_OTG_WRITE_REG32( &USB_OTG_FS_regs.GREGS->DIEPTXFx[1], txfifosize.d32 ); /* EP3 TX*/ txfifosize.b.startaddr += txfifosize.b.depth; txfifosize.b.depth = TX3_FIFO_SIZE; USB_OTG_WRITE_REG32( &USB_OTG_FS_regs.GREGS->DIEPTXFx[2], txfifosize.d32 ); /* Flush the FIFOs */ OTGD_FS_FlushTxFifo(0x10); /* all Tx FIFOs */ OTGD_FS_FlushRxFifo(); /* Clear all pending Device Interrupts */ USB_OTG_WRITE_REG32( &USB_OTG_FS_regs.DEV->DIEPMSK, 0 ); USB_OTG_WRITE_REG32( &USB_OTG_FS_regs.DEV->DOEPMSK, 0 ); USB_OTG_WRITE_REG32( &USB_OTG_FS_regs.DEV->DAINT, 0xFFFFFFFF ); USB_OTG_WRITE_REG32( &USB_OTG_FS_regs.DEV->DAINTMSK, 0 ); for (i = 0; i < NUM_TX_FIFOS; i++) { depctl.d32 = USB_OTG_READ_REG32(&USB_OTG_FS_regs.DINEPS[i]->DIEPCTLx); if (depctl.b.epena) { depctl.d32 = 0; depctl.b.epdis = 1; depctl.b.snak = 1; } else { depctl.d32 = 0; } USB_OTG_WRITE_REG32( &USB_OTG_FS_regs.DINEPS[i]->DIEPCTLx, depctl.d32); USB_OTG_WRITE_REG32( &USB_OTG_FS_regs.DINEPS[i]->DIEPTSIZx, 0); USB_OTG_WRITE_REG32( &USB_OTG_FS_regs.DINEPS[i]->DIEPINTx, 0xFF); } for (i = 0; i < 1/* NUM_OUT_EPS*/; i++) { depctl.d32 = USB_OTG_READ_REG32(&USB_OTG_FS_regs.DOUTEPS[i]->DOEPCTLx); if (depctl.b.epena) { depctl.d32 = 0; depctl.b.epdis = 1; depctl.b.snak = 1; } else { depctl.d32 = 0; } USB_OTG_WRITE_REG32( &USB_OTG_FS_regs.DOUTEPS[i]->DOEPCTLx, depctl.d32); USB_OTG_WRITE_REG32( &USB_OTG_FS_regs.DOUTEPS[i]->DOEPTSIZx, 0); USB_OTG_WRITE_REG32( &USB_OTG_FS_regs.DOUTEPS[i]->DOEPINTx, 0xFF); } OTGD_FS_EnableDevInt(); return status; }
/******************************************************************************* * Function Name : OTGD_FS_CoreInitDev * Description : Initialize the USB_OTG controller registers for device mode * Input : None * Output : None * Return : Status *******************************************************************************/ USB_OTG_Status OTGD_FS_CoreInitDev (void) { USB_OTG_Status status = USB_OTG_OK; USB_OTG_dev_ep_ctl_data depctl; uint32_t i; USB_OTG_dev_cfg_data dcfg; USB_OTG_fifo_size_data nptxfifosize; USB_OTG_fifo_size_data txfifosize; USB_OTG_dev_in_ep_msk_data msk; dcfg.d32 = 0; /* Set device speed */ InitDevSpeed (); /* Restart the Phy Clock */ WRITE_REG32(core_regs.pcgcctl, 0); /* Device configuration register */ dcfg.d32 = READ_REG32( &core_regs.dev_regs->dev_cfg); dcfg.b.perfrint = DCFG_FRAME_INTERVAL_80; WRITE_REG32( &core_regs.dev_regs->dev_cfg, dcfg.d32 ); /* set Rx FIFO size */ WRITE_REG32( &core_regs.common_regs->rx_fifo_siz, RX_FIFO_SIZE); /* Non-periodic Tx FIFO */ nptxfifosize.b.depth = DEV_NP_TX_FIFO_SIZE; nptxfifosize.b.startaddr = RX_FIFO_SIZE; WRITE_REG32( &core_regs.common_regs->np_tx_fifo_siz, nptxfifosize.d32 ); txfifosize.b.depth = DEV_NP_TX_FIFO_SIZE; WRITE_REG32( &core_regs.common_regs->dev_p_tx_fsiz_dieptxf[0], txfifosize.d32 ); txfifosize.b.startaddr += txfifosize.b.depth; txfifosize.b.startaddr = nptxfifosize.b.startaddr + nptxfifosize.b.depth; /* Flush the FIFOs */ OTGD_FS_FlushTxFifo(0x10); /* all Tx FIFOs */ OTGD_FS_FlushRxFifo(); /* Clear all pending Device Interrupts */ WRITE_REG32( &core_regs.dev_regs->dev_in_ep_msk, 0 ); WRITE_REG32( &core_regs.dev_regs->dev_out_ep_msk, 0 ); WRITE_REG32( &core_regs.dev_regs->dev_all_int, 0xFFFFFFFF ); WRITE_REG32( &core_regs.dev_regs->dev_all_int_msk, 0 ); for (i = 0; i <= MAX_TX_FIFOS; i++) { depctl.d32 = READ_REG32(&core_regs.inep_regs[i]->dev_in_ep_ctl); if (depctl.b.epena) { depctl.d32 = 0; depctl.b.epdis = 1; depctl.b.snak = 1; } else { depctl.d32 = 0; } WRITE_REG32( &core_regs.inep_regs[i]->dev_in_ep_ctl, depctl.d32); WRITE_REG32( &core_regs.inep_regs[i]->dev_in_ep_txfer_siz, 0); WRITE_REG32( &core_regs.inep_regs[i]->dev_in_ep_int, 0xFF); } for (i = 0; i < 1/* NUM_OUT_EPS*/; i++) { depctl.d32 = READ_REG32(&core_regs.outep_regs[i]->dev_out_ep_ctl); if (depctl.b.epena) { depctl.d32 = 0; depctl.b.epdis = 1; depctl.b.snak = 1; } else { depctl.d32 = 0; } WRITE_REG32( &core_regs.outep_regs[i]->dev_out_ep_ctl, depctl.d32); WRITE_REG32( &core_regs.outep_regs[i]->dev_out_ep_txfer_siz, 0); WRITE_REG32( &core_regs.outep_regs[i]->dev_out_ep_int, 0xFF); } msk.d32 = 0; msk.b.txfifoundrn = 1; MODIFY_REG32(&core_regs.dev_regs->dev_in_ep_msk, msk.d32, msk.d32); OTGD_FS_EnableDevInt(); return status; }