void InitSciGpio()
{
InitSciaGpio();
#if DSP28_SCIB
InitScibGpio();
#endif // if DSP28_SCIB
#if DSP28_SCIC
InitScicGpio();
#endif // if DSP28_SCIC
}
main()
{
int16 i;
int16 j;
int16 test[100];
//一、 system initialize: pll clock:150M;hispcp=1 100m/2; lospcp=2 100m/4;eWM,ADC,cpu Timer clock enabled
InitSysCtrl(); //修改了默认时钟到150MHz,关闭了无关外设时钟
// DELAY_US(1000000);
//二、initialize GPIO:set the GPIO to it's default state: 普通GPIO状态,均为输入,输入采样方式为第一种,均为上拉使能.
//epwm disable pull up
InitGpio(); //全部引脚初始化
//用户自定义IO初始化(主要包括:逻辑输入输出引脚)
InitLogicIO();
//串口初始化
InitScicGpio();
InitSci();
//初始化触摸屏变量
initvar();
// MemCopy(&RamfuncsLoadStart, &RamfuncsLoadEnd, &RamfuncsRunStart);
//EPwm初始化
// InitEPwmGpio(); //PWM IO初始化
//InitEPwm1Gpio();
//InitEPwm2Gpio(); //所有PWM模块都需要开启
//InitEPwm3Gpio();
//InitEPwm4Gpio();
//InitEPwm5Gpio();
//InitEPwm6Gpio();
//三、initialize interrupts:disable cpu interrupt; disabel all pie interrupts and clear all pie interrupt flags
DINT;
InitPieCtrl();
IER=0x0000;
IFR=0x0000;
//initialize Pie interrupts and enable pie
InitPieVectTable();
//用户自定义的中断初始化
EALLOW;
PieVectTable.TINT0 = &cpu_timer0_isr; //Cpu timer0 interrupt
PieVectTable.XINT1 = &xint1_isr;
EDIS;
//四、initialize peripherials and setup peripherials
InitFlash();
InitXintf();
//ADC initialize
InitAdc();
//ADC setup
SetupAdc();
// Adc_Inquire();
//Epwm Setup
// SetupEPwm(); //pwm开始产生
//CPU timer0 initialize
InitCpuTimers();
// Configure CPU-Timer 0 to interrupt every msecond:
// 150MHz CPU Freq, 3m second Period (in uSeconds)
ConfigCpuTimer(&CpuTimer0, 150, 3000);
StartCpuTimer0();
//五、User specific code, enable interrupts:
//在开始中断之前先进行测试循环。此时进行单步运行
//1. I/O test
//测试程序，GPIOA的低18位为通用I/O输入
//测试程序，GPIOA的24,25,26,27为通用I/O输入，GPIOB的48-61为通用I/O输入
//由于I/o口均有上拉，所以只要测试输入0时是否正确即可。这样最大限度保护芯片。
for(i=0;i<100;i++)
{
j=i;
}
// EALLOW;
// GpioCtrlRegs.GPADIR.all = 0x0003FFFF; // GPIO functionality GPIO0-GPIO15
// EDIS;
// GpioDataRegs.GPACLEAR.all = 0x0003FFFF;
// GpioDataRegs.GPASET.all = 0x0001AAAA;
// GpioDataRegs.GPATOGGLE.all = 0x0003FFFF;
//2. Communication Test: //具体通讯是否成功还需要更多程序
//测试RS485通讯芯片
GpioDataRegs.GPASET.bit.GPIO21=1;
GpioDataRegs.GPATOGGLE.bit.GPIO22=1;
//测试CAN通讯芯片
GpioDataRegs.GPATOGGLE.bit.GPIO19=1;
for(i=0;i<100;i++)
{
j=i;
}
//测试RS485通讯芯片
GpioDataRegs.GPASET.bit.GPIO21=1;
GpioDataRegs.GPATOGGLE.bit.GPIO22=1;
//测试CAN通讯芯片
GpioDataRegs.GPATOGGLE.bit.GPIO19=1;
for(i=0;i<100;i++)
{
j=i;
}
// 3. A/D Test
//软件启动adc转换
for(i=0;i<100;i++)
{
AdcRegs.ADCTRL2.bit.SOC_SEQ1=1;
Adc_Inquire();
}
// 4. PWM Test //每次测一个单相，这样子发现错误及时下电
for(i=0;i<100;i++)
{
j=i;
}
*FPGA_PWMA_Wait1=1000;
*FPGA_PWMA_Duty1=1000;
*FPGA_PWMA_Wait2=2000;
*FPGA_PWMA_Duty2=2000;
*FPGA_PWMA_Wait3=3000;
*FPGA_PWMA_Duty3=3000;
*FPGA_PWMA_Wait4=4000;
*FPGA_PWMA_Duty4=4000;
*FPGA_PWMA_Wait5=5000;
*FPGA_PWMA_Duty5=5000;
*FPGA_PWMA_Wait6=6000;
*FPGA_PWMA_Duty6=6000;
*FPGA_PWMA_Wait7=1000;
*FPGA_PWMA_Duty7=1000;
*FPGA_PWMA_Wait8=2000;
*FPGA_PWMA_Duty8=2000;
*FPGA_PWMA_Wait9=3000;
*FPGA_PWMA_Duty9=3000;
*FPGA_PWMA_Wait10=4000;
*FPGA_PWMA_Duty10=4000;
*FPGA_PWMA_Wait11=5000;
*FPGA_PWMA_Duty11=5000;
*FPGA_PWMA_Wait12=6000;
*FPGA_PWMA_Duty12=6000;
for(i=0;i<100;i++)
{
j=i;
}
*FPGA_PWMB_Wait1=1000;
*FPGA_PWMB_Duty1=1000;
*FPGA_PWMB_Wait2=2000;
*FPGA_PWMB_Duty2=2000;
*FPGA_PWMB_Wait3=3000;
*FPGA_PWMB_Duty3=3000;
*FPGA_PWMB_Wait4=4000;
*FPGA_PWMB_Duty4=4000;
*FPGA_PWMB_Wait5=5000;
*FPGA_PWMB_Duty5=5000;
*FPGA_PWMB_Wait6=6000;
*FPGA_PWMB_Duty6=6000;
*FPGA_PWMB_Wait7=1000;
*FPGA_PWMB_Duty7=1000;
*FPGA_PWMB_Wait8=2000;
*FPGA_PWMB_Duty8=2000;
*FPGA_PWMB_Wait9=3000;
*FPGA_PWMB_Duty9=3000;
*FPGA_PWMB_Wait10=4000;
*FPGA_PWMB_Duty10=4000;
*FPGA_PWMB_Wait11=5000;
*FPGA_PWMB_Duty11=5000;
*FPGA_PWMB_Wait12=6000;
*FPGA_PWMB_Duty12=6000;
for(i=0;i<100;i++)
{
j=i;
}
*FPGA_PWMC_Wait1=1000;
*FPGA_PWMC_Duty1=1000;
*FPGA_PWMC_Wait2=2000;
*FPGA_PWMC_Duty2=2000;
*FPGA_PWMC_Wait3=3000;
*FPGA_PWMC_Duty3=3000;
*FPGA_PWMC_Wait4=4000;
*FPGA_PWMC_Duty4=4000;
*FPGA_PWMC_Wait5=5000;
*FPGA_PWMC_Duty5=5000;
*FPGA_PWMC_Wait6=6000;
*FPGA_PWMC_Duty6=6000;
*FPGA_PWMC_Wait7=1000;
*FPGA_PWMC_Duty7=1000;
*FPGA_PWMC_Wait8=2000;
*FPGA_PWMC_Duty8=2000;
*FPGA_PWMC_Wait9=3000;
*FPGA_PWMC_Duty9=3000;
*FPGA_PWMC_Wait10=4000;
*FPGA_PWMC_Duty10=4000;
*FPGA_PWMC_Wait11=5000;
*FPGA_PWMC_Duty11=5000;
*FPGA_PWMC_Wait12=6000;
*FPGA_PWMC_Duty12=6000;
for(i=0;i<100;i++)
{
j=i;
}
*FPGA_PWMD_Wait1=1000;
*FPGA_PWMD_Duty1=1000;
*FPGA_PWMD_Wait2=2000;
*FPGA_PWMD_Duty2=2000;
*FPGA_PWMD_Wait3=3000;
*FPGA_PWMD_Duty3=3000;
*FPGA_PWMD_Wait4=4000;
*FPGA_PWMD_Duty4=4000;
*FPGA_PWMD_Wait5=5000;
*FPGA_PWMD_Duty5=5000;
*FPGA_PWMD_Wait6=6000;
*FPGA_PWMD_Duty6=6000;
*FPGA_PWMD_Wait7=1000;
*FPGA_PWMD_Duty7=1000;
*FPGA_PWMD_Wait8=2000;
*FPGA_PWMD_Duty8=2000;
*FPGA_PWMD_Wait9=3000;
*FPGA_PWMD_Duty9=3000;
*FPGA_PWMD_Wait10=4000;
*FPGA_PWMD_Duty10=4000;
*FPGA_PWMD_Wait11=5000;
*FPGA_PWMD_Duty11=5000;
*FPGA_PWMD_Wait12=6000;
*FPGA_PWMD_Duty12=6000;
for(i=0;i<100;i++)
{
j=i;
}
*FPGA_PWME_Wait1=1000;
*FPGA_PWME_Duty1=1000;
*FPGA_PWME_Wait2=2000;
*FPGA_PWME_Duty2=2000;
*FPGA_PWME_Wait3=3000;
*FPGA_PWME_Duty3=3000;
*FPGA_PWME_Wait4=4000;
*FPGA_PWME_Duty4=4000;
*FPGA_PWME_Wait5=5000;
*FPGA_PWME_Duty5=5000;
*FPGA_PWME_Wait6=6000;
*FPGA_PWME_Duty6=6000;
*FPGA_PWME_Wait7=1000;
*FPGA_PWME_Duty7=1000;
*FPGA_PWME_Wait8=2000;
*FPGA_PWME_Duty8=2000;
*FPGA_PWME_Wait9=3000;
*FPGA_PWME_Duty9=3000;
*FPGA_PWME_Wait10=4000;
*FPGA_PWME_Duty10=4000;
*FPGA_PWME_Wait11=5000;
*FPGA_PWME_Duty11=5000;
*FPGA_PWME_Wait12=6000;
*FPGA_PWME_Duty12=6000;
//PWM复位功能演示，复位以后，所有PWM为零。
GpioDataRegs.GPACLEAR.bit.GPIO31=1;
DELAY_US(1);
GpioDataRegs.GPASET.bit.GPIO31=1;
// 5. D/A Test
*DAC1=1024;
*DAC2=2048;
*DAC3=3072;
*DAC4=4095;
// 6.测试FPGA的I/O
// 首先测试是否结果为1
for(j=0;j<10;j++)
{
for(i=0; i<24; i++)
test[i]=*(FPGA_IO1_DATA+i);
i=0;
}
//再测试是否结果为0
for(j=0;j<100;j++)
{
for(i=0; i<24; i++)
test[i]=*(FPGA_IO1_DATA+i);
i=0;
}
//输出功能演示,只有输出使能的IO pin才能输出0
*FPGA_IODIR_LOW=0xFFFF;
*FPGA_IODIR_HIGH=0x00FF;
j=0;
for(i=0; i<24; i++)
{
*(FPGA_IO1_DATA+i)=j;
j=~j;
}
j=0;
for(i=0; i<24; i++)
{
j=~j;
*(FPGA_IO1_DATA+i)=j;
}
//复位功能演示，复位以后，所有IO上拉。且输出不使能
GpioDataRegs.GPACLEAR.bit.GPIO30=1;
DELAY_US(1);
GpioDataRegs.GPASET.bit.GPIO30=1;
j=*FPGA_IODIR_LOW;
j=*FPGA_IODIR_HIGH;
j=0;
for(i=0; i<24; i++)
*(FPGA_IO1_DATA+i)=j;
//开用到的中断，最后开中断。测试SCI 通讯以及DSP 和FPGA的通讯
EnableInterrupts(); //cpu timer0 中断
i=0;
// 六. 主循环IDLE loop. Just sit and loop forever (optional):
for(;;)
{
// ScicRegs.SCITXBUF=i;
DELAY_US(1000);
/*
if(GpioDataRegs.GPADAT.bit.GPIO27==0)
GpioDataRegs.GPBCLEAR.bit.GPIO50=1;
else
GpioDataRegs.GPBSET.bit.GPIO50=1;
if(GpioDataRegs.GPBDAT.bit.GPIO48==0)
GpioDataRegs.GPBCLEAR.bit.GPIO51=1;
else
GpioDataRegs.GPBSET.bit.GPIO51=1;
// ModebusRegsDataBuff[0]=i;
// GpioDataRegs.GPBTOGGLE.bit.GPIO60=1;
// GpioDataRegs.GPBTOGGLE.bit.GPIO61=1;
// GpioDataRegs.GPBTOGGLE.bit.GPIO58=1;
// GpioDataRegs.GPBTOGGLE.bit.GPIO59=1;
GpioDataRegs.GPBCLEAR.bit.GPIO53= 1;
GpioDataRegs.GPBCLEAR.bit.GPIO52= 1;
i++;
// if(i==2000)
if(i==FPGA_DATA_Test_length)
i=0;
// TestState=~TestState;
*/
slavecomm();
}
}