Beispiel #1
0
//////////
// Function Name : PWM_ReadrTCMPB
// Function Description : This function read out rTCMPB value
// Input : nNum [0:timer0   1:timer1   2:timer2   3:timer3]
// Output : rTCMPB value
// Version : v0.1
u32 PWM_ReadrTCMPB(u32 uNum)
{
	u32 RegTmp;

	switch(uNum)
		{
		case 0:
			RegTmp = Inp32(rTCMPB0);
			break;
			
		case 1:
			RegTmp = Inp32(rTCMPB1);
			break;			
			
		case 2:
			RegTmp = Inp32(rTCMPB2);
			break;
			
		case 3:
			RegTmp = Inp32(rTCMPB3);	
			break;			
		}
	return RegTmp;
	
}
Beispiel #2
0
bool otp_cmd_init(void)
{
	u32 ulreg;
	u32 uErrorCnt = 0;
	bool bResult = false;

	Outp32(rOTP_CON_CONRTOL, 0x01);

	while (true) {
		if (Inp32(rOTP_INT_STATUS) & 0x01) {
			bResult = true;
			break;
		}
		uErrorCnt++;
		if (uErrorCnt > 0xffffff) {
			bResult = false;
			break;
		}
	}

	ulreg = Inp32(rOTP_INT_STATUS);
	Outp32(rOTP_INT_STATUS, (ulreg | 0x01));

	return bResult;
}
Beispiel #3
0
bool otp_cmd_standby(void)
{
	u32 ulreg;
	u32 uErrorCnt = 0;
	bool bResult = false;

	/* 1. set standby command */
	ulreg = Inp32(rOTP_CON_CONRTOL);
	Outp32(rOTP_CON_CONRTOL, (ulreg & 0xfffffff7) | 0x08);

	while (true) {
		if (Inp32(rOTP_INT_STATUS) & 0x08) {
			bResult = true;
			break;
		}
		uErrorCnt++;
		if (uErrorCnt > 0xffffff) {
			bResult = false;
			break;
		}
	}

	ulreg = Inp32(rOTP_INT_STATUS);
	Outp32(rOTP_INT_STATUS, (ulreg | 0x08));

	return bResult;
}
Beispiel #4
0
//////////
// Function Name : UART_Putc
// Function Description : This function write character data to uart debugging ch
// Input : NONE
// Output : NONE
// Version :
void UART_Putc(char data)
{
    u32 temp;

    if(data=='\n')
    {
        while(1)
        {
            Delay(10);
            temp = Inp32(&g_pUartDebugRegs->rUtrStat);
            temp&=0x2;
            if(temp)
                break;
        }
//		Delay(10);
        Outp8(&g_pUartDebugRegs->rUtxh,'\r');
    }
    while(1)
    {
        Delay(5);
        temp = Inp32(&g_pUartDebugRegs->rUtrStat);
        temp&=0x02;
        if(temp)
            break;
    }
    //Delay(10);
    Outp8(&g_pUartDebugRegs->rUtxh,data);
    return;
}
/*
	Function for setting measurement period
	Parameter :
		BaseAddr = PPMU IP BASE ADDRESS
		clk_count = for caculation
*/
s32 PPMU_SetCIGCondition(addr_u32 BaseAddr, u32 eventIdx, u32 UpperThreshold, u32 UpperRepeat, u32 LowerThreshold, u32 LowerRepeat)
{
    u32 uRegValue;

    if (PPMU_GetVersion(BaseAddr) == 2) {
        uRegValue = Inp32(BaseAddr+rV2_PMNC);
        uRegValue = Inp32(BaseAddr + rV2_CIG_CFG0);

        uRegValue = uRegValue & ~(0xf<<4);
        uRegValue = uRegValue | ((LowerRepeat & 0xf)<<4);

        uRegValue = uRegValue & ~(0xf<<8);
        uRegValue = uRegValue | ((UpperRepeat & 0xf)<<8);

        uRegValue = uRegValue & ~(0x1<<16); /* Lower bound relationship : Any */
        uRegValue = uRegValue | (0x1<<20); /* Upper bound relationship : All */

        Outp32(BaseAddr + rV2_CIG_CFG0, uRegValue);

        Outp32(BaseAddr + rV2_CIG_CFG1, LowerThreshold);
        Outp32(BaseAddr + rV2_CIG_CFG2, UpperThreshold);
    } else {
        return 1;
    }
    return 0;
}
/*
	Function for stop ppmu counting used in Auto, Manual and CIG mode
	Parameter :
		BaseAddr = PPMU IP BASE ADDRESS
*/
void PPMU_Stop(addr_u32 BaseAddr)
{
    u32 uRegValue;

    if (PPMU_GetVersion(BaseAddr) == 2) {
        uRegValue = Inp32(BaseAddr+rV2_PMNC);
        uRegValue &= ~0x1;	/* stop signal */
        Outp32(BaseAddr+rV2_PMNC, uRegValue);
    } else { /* must be v1.1 */
        uRegValue = Inp32(BaseAddr+rV1_PMNC);
        uRegValue &= ~0x1;
        Outp32(BaseAddr+rV1_PMNC, uRegValue);
    }
}
/*
	Function for changing start method to external trigger(sysreg)
	Parameter :
		BaseAddr = PPMU IP BASE ADDRESS
*/
void PPMU_ControlByExtTrigger(addr_u32 BaseAddr)/* start/stop by external trigger(or SYSCON) */
{
    u32 uRegValue;

    if (PPMU_GetVersion(BaseAddr) == 2) {
        uRegValue = Inp32(BaseAddr+rV2_PMNC);
        uRegValue |= 0x1<<16;
        Outp32(BaseAddr+rV2_PMNC, uRegValue);
    } else { /* must be v1.1 */
        uRegValue = Inp32(BaseAddr+rV1_PMNC);
        uRegValue |= 0x1<<16;
        Outp32(BaseAddr+rV1_PMNC, uRegValue);
    }
}
/*
	Function for setting CIG Interrupt enable
	Parameter :
		BaseAddr = PPMU IP BASE ADDRESS
		PMCNTxen = enable interrupt signal for PMCNTx
*/
s32 PPMU_EnableCIGInterrupt(addr_u32 BaseAddr, u32 PMCNT0en, u32 PMCNT1en, u32 PMCNT2en)
{
    u32 uRegValue;

    if (PPMU_GetVersion(BaseAddr) == 2) {
        uRegValue = Inp32(BaseAddr+rV2_PMNC);
        uRegValue = Inp32(BaseAddr + rV2_CIG_CFG0);
        uRegValue = uRegValue | PMCNT0en | (PMCNT1en<<1) | (PMCNT2en<<2);
        Outp32(BaseAddr + rV2_CIG_CFG0, uRegValue);
    } else {
        return 1;
    }
    return 0;
}
Beispiel #9
0
int board_late_init (void)
{
	unsigned int regs;
	char boot_cmd[100];

	regs = Inp32(INF_REG_BASE + INF_REG3_OFFSET);
	Outp32(0xe02002a0, 0x10000000);
	Outp32(0xe02002c0, 0x1);

	switch(regs) {
	case BOOT_NAND:
		Outp32(0xe02002a4, 0x0);	// LED0 On
		Outp32(0xe02002c4, 0x1);	// LED1 Off

         	printf("checking mode for fastboot ...\n");

         	if((~readl(0xE0200C04)) & 0x6) {
         		run_command("fastboot", 0);
                } else
		if(default_boot_mode) {		// using default environment
			sprintf(boot_cmd, "nand read %08x 600000 400000;nand read %08x B00000 300000; bootm %08x %08x"
					, MEMORY_BASE_ADDRESS + 0x8000
					, MEMORY_BASE_ADDRESS + 0x1000000
					, MEMORY_BASE_ADDRESS + 0x8000
					, MEMORY_BASE_ADDRESS + 0x1000000);
			setenv("bootcmd", boot_cmd);

			sprintf(boot_cmd, "root=ramfs devfs=mount console=ttySAC1,115200");
			setenv("bootargs", boot_cmd);
		}
		break;
	case BOOT_MMCSD:
		Outp32(0xe02002a4, 0x80);	// LED1 On
		Outp32(0xe02002c4, 0x0);	// LED0 Off

		if((~Inp32(0xe0200c04)) & 0x6) { // Linux Recovery Booting Mode
			sprintf(boot_cmd, "nand erase clean;nand scrub;movi read u-boot %08x;nand write %08x 0 70000;movi read kernel %08x;bootm %08x"
					, MEMORY_BASE_ADDRESS + 0x1000000, MEMORY_BASE_ADDRESS + 0x1000000
					, MEMORY_BASE_ADDRESS + 0x8000, MEMORY_BASE_ADDRESS + 0x8000);
			setenv("bootcmd", boot_cmd);
			sprintf(boot_cmd, "root=/dev/mmcblk0p3 rootfstype=ext3 console=ttySAC1,115200 rootdelay=1 recovery");
			setenv("bootargs", boot_cmd);
			sprintf(boot_cmd, "0");
			setenv("bootdelay", boot_cmd);
		} else
		if(default_boot_mode) {	// using default environment
			sprintf(boot_cmd, "movi read kernel %08x; bootm %08x"
					, MEMORY_BASE_ADDRESS + 0x8000
					, MEMORY_BASE_ADDRESS + 0x8000);
			setenv("bootcmd", boot_cmd);
			sprintf(boot_cmd, "root=/dev/mmcblk0p4 rootfstype=ext3 console=ttySAC1,115200 rootdelay=1");	// Android Booting Mode
			setenv("bootargs", boot_cmd);
		}
		break;
	}

	//LCD_turnon();
	return 0;
}
// do not protext this by mutex. It's internally only called by mutex protected functions
int TimePixDAQStatus::_Inp32(short par)
{	static int retval;
	retval = Inp32(par);
	if(retval == 0xFF)
		return AfxMessageBox("Please enter valid Port Address", MB_ICONERROR, 0);//MessageBox(NULL, "Please enter valid Port Address", "I/O Error", MB_ICONERROR);
	else
		return retval;
}
/*
	Function for initiating PPMU defualt setting
	Parameter :
		BaseAddr = PPMU IP BASE ADDRESS
*/
void PPMU_Init(addr_u32 BaseAddr)
{
    u32 uRegValue;
    u32  bIsCounting;

    if (PPMU_GetVersion(BaseAddr) == 2) {
        /* reset to default */
        uRegValue = Inp32(BaseAddr+rV2_PMNC);

        bIsCounting = uRegValue & 0x1;
        if (bIsCounting) {
            uRegValue &= ~(1<<0); /* counting disable */
            Outp32(BaseAddr+rV2_PMNC, uRegValue);
        }
        uRegValue = uRegValue & ~(0x3<<20);

        uRegValue &= ~(0x1<<16);/* 0x0: Configure start mode as APB interface */
        uRegValue &= ~(0x1<<3); /* 0x0: Disable clock dividing */
        uRegValue |= (0x1<<2); /* 0x1: Reset CCNT */
        uRegValue |= (0x1<<1); /* 0x1: Reset PMCNTs */
        Outp32(BaseAddr+rV2_PMNC, uRegValue);

        /* Count Enable CCNT, PMCNTTx */
        Outp32(BaseAddr+rV2_CNTENS, 0x8000000f);

        PPMU_EnableOverflowInterrupt(BaseAddr);
    } else { /* must be v1.1 */
        uRegValue = Inp32(BaseAddr+rV1_PMNC);

        bIsCounting = uRegValue & 0x1;
        if (bIsCounting) {
            uRegValue &= ~(1<<0);
            Outp32(BaseAddr+rV1_PMNC, uRegValue);
        }

        uRegValue &= ~(0x1<<3); /* NO CC Divider */
        uRegValue |= 0x1<<2; /* Reset CCNT */
        uRegValue |= 0x1<<1; /* Reset All PMCNTs */
        Outp32(BaseAddr+rV1_PMNC, uRegValue);

        Outp32(BaseAddr+rV1_CNTENS, 0x8000000f);

        PPMU_EnableOverflowInterrupt(BaseAddr);
    }
}
Beispiel #12
0
u32 StopTimer(u32 uTsel)
{
	u32 uVal;
	
	PWM_stop(uTsel);

	uVal = 0xffffffff - (Inp32(rTCNTO0+(uTsel*12)));

	return uVal;
}
Beispiel #13
0
// Input : 			cMeasure [milli : milli sec,   micro: micro sec]
// 					uDnum [uDnum : 1 = 1msec, 10=10msec, 100 = 100msec when cMeasure = milli]
// Output : NONE
// Version : v0.1
void DelayfrTimer(eDelay_M cMeasure, u32 uDnum)
{
	u32 uCnt;
	
	PWM_stop(2);							// Using PWM timer #2


	if( cMeasure == micro )
		{
			uCnt = g_PCLK/1000000;
			
			PWM_Select(2,uCnt,0,0xffffffff,(u32)(0xffffffff/2),0,0,0,1,0,0); // Timer2,Divider =1/1, Prescaler = g_PCLK/1M

			while(1)
				{	
					if((0xffffffff-Inp32(rTCNTO2)) == uDnum)
						break;
				}	

		}

	else if( cMeasure == milli )
		{

			uCnt = g_PCLK/1000000;
			
			PWM_Select(2,uCnt,0,0xffffffff,(u32)(0xffffffff/2),0,0,0,1,0,0); // Timer2,Divider =1/1, Prescaler = g_PCLK/1M

//			while(!(Inp32(rTCNTO0)==0xffffffff))

			while(1)
				{	
					if((0xffffffff-Inp32(rTCNTO2)) == (uDnum*1000))
						break;
				}	
	

		}

		PWM_Select(2,uCnt,0,0xffffffff,(u32)(0xffffffff/2),0,0,0,1,0,0); // Timer2,Divider =1/1, Prescaler = g_PCLK/1M
//		PWM_stop(2);	
}
void bts_setotf_sysreg(BWL_SYSREG_RT_NRT_SEL path_sel, addr_u32 base, bool enable)
{
	unsigned int tmp_reg;

	tmp_reg = Inp32(base);

	if(enable)
		Outp32(base, tmp_reg | (0x1<<path_sel));
	else
		Outp32(base, tmp_reg & ~(0x1<<path_sel));
}
/*
	Function for reset counter CCNT, PMCNTx
	Parameter :
		BaseAddr = PPMU IP BASE ADDRESS
*/
void PPMU_Reset(addr_u32 BaseAddr)
{
    u32 uRegValue;

    if (PPMU_GetVersion(BaseAddr) == 2) {
        uRegValue = Inp32(BaseAddr+rV2_PMNC);
        uRegValue |= (0x1<<2); /* 0x1: Reset CCNT */
        uRegValue |= (0x1<<1); /* 0x1: Reset PMCNTs */
        Outp32(BaseAddr+rV2_PMNC, uRegValue);

    } else { /* must be v1.1 */
        uRegValue = Inp32(BaseAddr+rV1_PMNC);
        uRegValue |= (0x1<<2); /* 0x1: Reset CCNT */
        uRegValue |= (0x1<<1); /* 0x1: Reset PMCNTs */
        Outp32(BaseAddr+rV1_PMNC, uRegValue);

        uRegValue &= ~(0x00000006);
        Outp32(BaseAddr+rV1_PMNC, uRegValue);
    }
}
Beispiel #16
0
//////////
// Function Name : PWM_stop
// Function Description : This function stops timer individually
// Input : nNum [0:timer0   1:timer1   2:timer2   3:timer3]
// Output : NONE
// Version : v0.1
void PWM_stop(u32 uNum)
{
	u32 uTemp;

	uTemp = Inp32(rTCON);

	if(uNum == 0)
			uTemp &= ~(0x1);
	else
			uTemp &= ~((0x10)<<(uNum*4));
		
	Outp32(rTCON,uTemp);
}
Beispiel #17
0
void ParallelPort::PinLow(const int p)

// set pin p (2:9) low
{
    if (!initSuccess) return;
    if ((p < 2) | (p > 9)) return;

    short x = Inp32(port);
    short b = 1 << (p - 2);
    if (x & b) {
        x -= b;
        Out32(port, x);
    }
}
Beispiel #18
0
//////////
// Function Name : UART_Getc
// Function Description : This function read character data from uart debugging ch
// Input : NONE
// Output : temp8, character data received through uart
// Version :
s8 UART_Getc( void)
{
    u32 temp32;
    char temp8;
    while(1)
    {
        temp32 = Inp32(&g_pUartDebugRegs->rUtrStat);
        temp32&=0x01;
        if(temp32)
            break;
    }
    temp8 = Inp8(&g_pUartDebugRegs->rUrxh);
    return temp8;
}
Beispiel #19
0
//////////
// Function Name : Isr_TIMER3
// Function Description : This function is Interrupt Service Routine of PWM Timer0
// Input : NONE
// Output : NONE (increment of g_uIntCounter0 value)
// Version : v0.1
void Isr_TIMER3(void)
{
	u32 uTmp;
	
	uTmp = Inp32(rTINT_CSTAT);
	uTmp = (uTmp & 0x1f) | (1<<8);
	Outp32(rTINT_CSTAT,uTmp);       //  Timer3 Interrupt Clear register
    
	UART_Printf("Timer3\n");
	g_uIntCounter3++;
	
	INTC_ClearVectAddr();    

}
Beispiel #20
0
void ParallelPort::PinHigh(const int p)

// set pin (2:9) high
{
    if (!initSuccess) return;
    if ((p < 2) | (p > 9)) return;

    short x = Inp32(port);
    short b = 1 << (p - 2);
    if (!(x & b)) {
        x += b;
        Out32(port, x);
    }
}
/*
	Function for start ppmu counting by APB signal used in Auto or Manual mode
	Parameter :
		BaseAddr = PPMU IP BASE ADDRESS
		eMode = Auto, Manual, CIG (Ref. ppmu.h)

*/
void PPMU_Start(addr_u32 BaseAddr, PPMU_MODE eMode)/* for individual control use CNTENS/C Reg */
{
    u32 uRegValue;

    if (PPMU_GetVersion(BaseAddr) == 2) {
        uRegValue = Inp32(BaseAddr+rV2_PMNC);
        uRegValue = uRegValue & ~(0x3<<20);/* clear Start Mode */
        uRegValue =
            (eMode == PPMU_MODE_MANUAL)	? uRegValue | (0x0<<20) :
            (eMode == PPMU_MODE_AUTO)	? uRegValue | (0x1<<20) :
            (eMode == PPMU_MODE_CIG)	? uRegValue | (0x2<<20) : 0;
        uRegValue |= 0x1;/* Start counting throung APB interface */

        if (eMode == PPMU_MODE_CIG)
            PPMU_SetGICMeasurementPeriod(BaseAddr, 400); /* 1000ms interval */

        Outp32(BaseAddr+rV2_PMNC, uRegValue);
    } else { /* must be v1.1 and only 'manual mode' exist. */
        uRegValue = Inp32(BaseAddr+rV1_PMNC);
        uRegValue &= ~0x1;
        uRegValue |= 0x1;
        Outp32(BaseAddr+rV1_PMNC, uRegValue);
    }
}
Beispiel #22
0
unsigned int Fire( void )
{
	unsigned char index;

	index = (unsigned char)Inp32( PPORT_BASE+0 ); // Get the previous address

	Out32( PPORT_BASE+0, index | 0x80 ); // Fire socket (set high-order bit)
	Out32( PPORT_BASE+2, 0x01 ); // Begin strobe of STROBE
	Out32( PPORT_BASE+2, 0x00 ); // Begin strobe of STROBE

	Sleep( FireDelay );

	Out32( PPORT_BASE+0, index & ~0x80 ); // Fire socket
	Out32( PPORT_BASE+2, 0x01 ); // Begin strobe of STROBE
	Out32( PPORT_BASE+2, 0x00 ); // Begin strobe of STROBE

	return( FireDelay );
}
Beispiel #23
0
void CalibrateDelay(void)
{
	u32 i, tmpDelay=100;
	u32 uPCLK_MHz=g_PCLK/1000000;
	
	delayLoopCount = 5000;
	
	Outp32(rWTCON, (uPCLK_MHz-1)<<8);
	Outp32(rWTDAT, 0xffff);						//for first update
	Outp32(rWTCNT, 0xffff);						//resolution=16us @any PCLK 
	Outp32(rWTCON, ((uPCLK_MHz-1)<<8)|(1<<5));	//Watch-dog timer start
	
	for(;tmpDelay>0;tmpDelay--)
		for(i=0;i<delayLoopCount;i++);
	
	Outp32(rWTCON, (uPCLK_MHz-1)<<8);   		//Watch-dog timer stop
	i = 0xffff - Inp32(rWTCNT);                 // 1count->16us, 100*5000 cycle runtime = 
	delayLoopCount = 50000000/(i*16);         	//100*5000:16*i[us]=1*x:100[us] -> x=50000000/(16*i)

}
s32 PPMU_GetVersion(addr_u32 BaseAddr)
{
    u32 uVersion;

#ifdef CONFIG_ARM_EXYNOS5433_BUS_DEVFREQ
    if (ppmu_version != 0)
        return ppmu_version;
#endif

    uVersion = (Inp32(BaseAddr) & 0x000f0000) >> 16;
    if (uVersion == 2)
        uVersion = 2;
    else
        uVersion = 1;

#ifdef CONFIG_ARM_EXYNOS5433_BUS_DEVFREQ
    ppmu_version = uVersion;
#endif

    return uVersion;
}
Beispiel #25
0
void Isr_TIMEROS(void)
{
	u32 uTmp;
	u32 uCnt;
	
	uTmp = Inp32(rTINT_CSTAT);

	for(uCnt = 0 ; uCnt <50 ; uCnt++)
	UART_Printf("#%d : rTINT_CSTAT = %x\n",uCnt,uTmp);

	
//	uTmp = (uTmp & 0x1f)| (1<<5);
	Outp32(rTINT_CSTAT,uTmp);       //  Timer0 Interrupt Clear register
    
	UART_Printf("Timer0\n");
	UART_Printf("IntCounter = %d \n ",g_uIntCounterOS);
	
	g_uIntCounterOS++;

	INTC_ClearVectAddr();

}
/*
	Function for starting with external trigger(sysreg)
	Parameter :
		BaseAddr = PPMU IP BASE ADDRESS
		controlAddr = SYSREG_PERIS ALL_PPMU_CON BaseAddr
		eMode = Auto, Menaul, CIG (Ref. ppmu.h)
*/
s32 PPMU_StartByExtTrigger(addr_u32 BaseAddr, addr_u32 controlAddr, PPMU_MODE eMode)
{

    u32 uRegValue;

    if (PPMU_GetVersion(BaseAddr) == 2) {
        if (eMode != PPMU_MODE_CIG) {
            uRegValue = Inp32(BaseAddr+rV2_PMNC);
            uRegValue = uRegValue & ~(0x3<<20);/* clear Start Mode */
            uRegValue =
                (eMode == PPMU_MODE_MANUAL)	? uRegValue | (0x0<<20) :
                (eMode == PPMU_MODE_AUTO)	? uRegValue | (0x1<<20) : 0;
            Outp32(BaseAddr+rV2_PMNC, uRegValue);

            Outp32(controlAddr, 0xFFFFFFFF); /* SYSREF PPMU External Trigger */
        } else {
            return 1;
        }
    } else { /* must be v1.1 and only 'manual mode' exist. */
        Outp32(controlAddr, 0xFFFFFFFF); /* SYSREF PPMU External Trigger */
    }

    return 0;
}
/*
	Function for getting result count for CIG mode
	Parameter :
		BaseAddr = PPMU IP BASE ADDRESS
		uClockcount = for clock count
		uEventxCount = for PMCNTx count
*/
s32 PPMU_GetCIGResult(addr_u32 BaseAddr, u32 *uClockCount, u32 *uEvent0Count, u32 *uEvent1Count, u32 *uEvent2Count, u64  *uEvent3Count)
{
    u32 uRegValue;

    if (PPMU_GetVersion(BaseAddr) == 2) {
        if (PPMU_GetVersion(BaseAddr) == 2) {
            /* Clear Interrupt */
            uRegValue = Inp32(BaseAddr + rV2_CIG_RESULT);

            uRegValue = uRegValue | (1<<4) | (1<<0);
            Outp32(BaseAddr + rV2_CIG_RESULT, uRegValue);

            *uClockCount = Inp32(BaseAddr+rV2_CCNT);
            *uEvent0Count = Inp32(BaseAddr+rV2_PMCNT0);
            *uEvent1Count = Inp32(BaseAddr+rV2_PMCNT1);
            *uEvent2Count = Inp32(BaseAddr+rV2_PMCNT2);
            *uEvent3Count = (u64)(Inp32(BaseAddr+rV2_PMCNT3_LOW)) + (((u64)(Inp32(BaseAddr+rV2_PMCNT3_HIGH)&0xff))<<32);
        }
    } else {
        return 1;
    }
    return 0;
}
/*
	Function for getting result count
	Parameter :
		BaseAddr = PPMU IP BASE ADDRESS
		uClockcount = for clock count
		uEventxCount = for PMCNTx count
*/
void PPMU_GetResult(addr_u32 BaseAddr, u32 *uClockCount, u32 *uEvent0Count, u32 *uEvent1Count, u32 *uEvent2Count, u64  *uEvent3Count)
{
    if (PPMU_GetVersion(BaseAddr) == 2) {
        *uClockCount = Inp32(BaseAddr+rV2_CCNT);
        *uEvent0Count = Inp32(BaseAddr+rV2_PMCNT0);
        *uEvent1Count = Inp32(BaseAddr+rV2_PMCNT1);
        *uEvent2Count = Inp32(BaseAddr+rV2_PMCNT2);
        *uEvent3Count = (u64)(Inp32(BaseAddr+rV2_PMCNT3_LOW)) + (((u64)(Inp32(BaseAddr+rV2_PMCNT3_HIGH)&0xff))<<32);
    } else { /* must be v1.1 */
        *uClockCount = Inp32(BaseAddr+rV1_CCNT);
        *uEvent0Count = Inp32(BaseAddr+rV1_PMCNT0);
        *uEvent1Count = Inp32(BaseAddr+rV1_PMCNT1);
        *uEvent2Count = Inp32(BaseAddr+rV1_PMCNT2);
        *uEvent3Count = (u64)(Inp32(BaseAddr+rV1_PMCNT3_HIGH)<<8) + (Inp32(BaseAddr+rV1_PMCNT3_LOW) & 0xf);
    }
}
void bts_setqos_sysreg(BWL_QOS_SYSREG_IP qos_id, addr_u32 base, unsigned int ar_qos,
			unsigned int aw_qos)
{
	unsigned int tmp_val;
	aw_qos = aw_qos&0xF;
	ar_qos = ar_qos&0xF;

	switch (qos_id) {
		case BTS_SYSREG_AUD:
			Outp32(base + DISPAUD_XIU_DISPAUD_QOS_CON, (aw_qos<<16)|(ar_qos<<12)|\
				(Inp32(base + DISPAUD_XIU_DISPAUD_QOS_CON)&0xFFF00FFF));
			break;
		case BTS_SYSREG_DISP:
			Outp32(base + DISPAUD_QOS_SEL, 0x0); /* DISP Qos select : 0x0(SYSREG QOS), 0x1(DECON QOS) */
			Outp32(base + DISPAUD_XIU_DISPAUD_QOS_CON, (ar_qos<<8)|(ar_qos<<4)|(ar_qos)|\
				(Inp32(base + DISPAUD_XIU_DISPAUD_QOS_CON)&0xFFFFF000));
			break;
		case BTS_SYSREG_FSYS0:
			Outp32(base + FSYS_QOS_CON0, (aw_qos<<28)|(ar_qos<<24)| \
				(aw_qos<<12)|(ar_qos<<8)|(aw_qos<<4)|(ar_qos));
			break;
		case BTS_SYSREG_FSYS1:
			Outp32(base + FSYS_QOS_CON1, (aw_qos<<20)|(ar_qos<<16)| \
				(aw_qos<<12)|(ar_qos<<8)|(aw_qos<<4)| \
				(ar_qos));
			break;
		case BTS_SYSREG_IMEM:
			Outp32(base + IMEM_QOS_CON, (ar_qos<<16)|(aw_qos<<12)| \
				(ar_qos<<8)|(aw_qos<<4)|(ar_qos));
			break;
		case BTS_SYSREG_FIMC_SCL:
			Outp32(base + ISP_QOS_CON0, (aw_qos<<28)| \
				(Inp32(base + ISP_QOS_CON0)&0x0FFFFFFF));
			break;
		case BTS_SYSREG_FIMC_FD:
			Outp32(base + ISP_QOS_CON0, (aw_qos<<20)|(ar_qos<<16)| \
				(Inp32(base + ISP_QOS_CON0)&0xFF00FFFF));
			break;
		case BTS_SYSREG_FIMC_ISP:
			Outp32(base + ISP_QOS_CON0, (aw_qos<<12)|(ar_qos<<8)| \
				(Inp32(base + ISP_QOS_CON0)&0xFFFF00FF));
			break;
		case BTS_SYSREG_FIMC_BNS_L:
			Outp32(base + ISP_QOS_CON0, (aw_qos<<4)| \
				(Inp32(base + ISP_QOS_CON0)&0xFFFFFF0F));
			break;
		case BTS_SYSREG_MIF_MODAPIF:
			tmp_val = 0x1;/* MODEM Qos select : 0x0(SYSREG QOS), 0x1(MODEM QOS) */
			Outp32(base + MIF_MODAPIF_QOS_CON, (aw_qos<<8)|(ar_qos<<4)|tmp_val);
			break;
		case BTS_SYSREG_MIF_CPU:
			Outp32(base + MIF_CPU_QOS_CON, (aw_qos<<4)|ar_qos);
			break;
		case BTS_SYSREG_MFC:
			Outp32(base + MFCMSCL_QOS_CON, (aw_qos<<28)|(ar_qos<<24)| \
				(Inp32(base + MFCMSCL_QOS_CON)&0x00FFFFFF));
			break;
		case BTS_SYSREG_JPEG:
			Outp32(base + MFCMSCL_QOS_CON, (aw_qos<<20)|(ar_qos<<16)| \
				(Inp32(base + MFCMSCL_QOS_CON)&0xFF00FFFF));
			break;
		case BTS_SYSREG_MSCL:
			Outp32(base + MFCMSCL_QOS_CON, (aw_qos<<12)|(ar_qos<<8)| \
				(aw_qos<<4)|(ar_qos)| \
				(Inp32(base + MFCMSCL_QOS_CON)&0xFFFF0000));
			break;
		default:
			break;
	}
}
void bts_setmo_sysreg(BWL_MO_SYSREG_IP mo_id, addr_u32 base, unsigned int ar_mo,
			unsigned int aw_mo)
{
	unsigned int tmp_reg;

	switch (mo_id) {
		case BTS_SYSREG_ISP1_M0:
			tmp_reg = Inp32(base + ISP_XIU_ISP1_AR_AC_TARGET_CON) & ~(0x3F<<16);
			/* reset value(0xC), [19:16] for AR */
			Outp32(base + ISP_XIU_ISP1_AR_AC_TARGET_CON, tmp_reg | ((ar_mo&0x3F)<<16));
			tmp_reg = Inp32(base + ISP_XIU_ISP1_AW_AC_TARGET_CON) & ~(0x3F<<16);
			/* reset value(0xC), [21:16] for AW */
			Outp32(base + ISP_XIU_ISP1_AW_AC_TARGET_CON, tmp_reg | ((aw_mo&0x3F)<<16));
			break;
		case BTS_SYSREG_ISP1_S1:
			tmp_reg = Inp32(base + ISP_XIU_ISP1_AR_AC_TARGET_CON) & ~(0x3F<<8);
			/* reset value(0x4), [10:8] for AR */
			Outp32(base + ISP_XIU_ISP1_AR_AC_TARGET_CON, tmp_reg | ((ar_mo&0x3F)<<8));
			tmp_reg = Inp32(base + ISP_XIU_ISP1_AW_AC_TARGET_CON) & ~(0x3F<<8);
			/* reset value(0x8), [11:8] for AW */
			Outp32(base + ISP_XIU_ISP1_AW_AC_TARGET_CON, tmp_reg | ((aw_mo&0x3F)<<8));
			break;
		case BTS_SYSREG_ISP1_S0:
			tmp_reg = Inp32(base + ISP_XIU_ISP1_AR_AC_TARGET_CON) & ~(0x3F);
			/* reset value(0x8), [3:0] for AR */
			Outp32(base + ISP_XIU_ISP1_AR_AC_TARGET_CON, tmp_reg | (ar_mo&0x3F));
			tmp_reg = Inp32(base + ISP_XIU_ISP1_AW_AC_TARGET_CON) & ~(0x3F);
			/* reset value(0x18), [4:0] for AW */
			Outp32(base + ISP_XIU_ISP1_AW_AC_TARGET_CON, tmp_reg | (aw_mo&0x3F));
			break;
		case BTS_SYSREG_ISP0_M0:
			tmp_reg = Inp32(base + ISP_XIU_ISP0_AR_AC_TARGET_CON) & ~(0x3F<<24);
			/* reset value(0x8), [27:24] for AR */
			Outp32(base + ISP_XIU_ISP0_AR_AC_TARGET_CON, tmp_reg | ((ar_mo&0x3F)<<24));
			tmp_reg = Inp32(base + ISP_XIU_ISP0_AW_AC_TARGET_CON) & ~(0x3F<<24);
			/* reset value(0x8), [28:24] for AW */
			Outp32(base + ISP_XIU_ISP0_AW_AC_TARGET_CON, tmp_reg | ((aw_mo&0x3F)<<24));
			break;
		case BTS_SYSREG_ISP0_S2:
			tmp_reg = Inp32(base + ISP_XIU_ISP0_AR_AC_TARGET_CON) & ~(0x3F<<16);
			/* reset value(0x1), [16:16] for AR */
			Outp32(base + ISP_XIU_ISP0_AR_AC_TARGET_CON, tmp_reg | ((ar_mo&0x3F)<<16));
			tmp_reg = Inp32(base + ISP_XIU_ISP0_AW_AC_TARGET_CON) & ~(0x3F<<16);
			/* reset value(0x1), [19:16] for AW */
			Outp32(base + ISP_XIU_ISP0_AW_AC_TARGET_CON, tmp_reg | ((aw_mo&0x3F)<<16));
			break;
		case BTS_SYSREG_ISP0_S1:
			tmp_reg = Inp32(base + ISP_XIU_ISP0_AR_AC_TARGET_CON) & ~(0x3F<<8);
			/* reset value(0x8), [11:8] for AR */
			Outp32(base + ISP_XIU_ISP0_AR_AC_TARGET_CON, tmp_reg | ((ar_mo&0x3F)<<8));
			tmp_reg = Inp32(base + ISP_XIU_ISP0_AW_AC_TARGET_CON) & ~(0x3F<<8);
			/* reset value(0x8), [11:8] for AW */
			Outp32(base + ISP_XIU_ISP0_AW_AC_TARGET_CON, tmp_reg | ((aw_mo&0x3F)<<8));
			break;
		case BTS_SYSREG_ISP0_S0:
			tmp_reg = Inp32(base + ISP_XIU_ISP0_AR_AC_TARGET_CON) & ~(0x3F);
			/* reset value(0x1), [0:0] for AR */
			Outp32(base + ISP_XIU_ISP0_AR_AC_TARGET_CON, tmp_reg | (ar_mo&0x3F));
			tmp_reg = Inp32(base + ISP_XIU_ISP0_AW_AC_TARGET_CON) & ~(0x3F);
			/* reset value(0x8), [3:0] for AW */
			Outp32(base + ISP_XIU_ISP0_AW_AC_TARGET_CON, tmp_reg | (aw_mo&0x3F));
			break;
		default:
			break;
	}
}