bool Item::is_magic() const
{
return IsMagic();
}
void Exc::Dispatch(TAny* aPtr, NThread*)
{
#ifdef __CPU_ARM_ABORT_MODEL_UPDATED
#error Processors implementing the 'Base Register Updated' Abort Model are no longer supported
#endif
TArmExcInfo* pR=(TArmExcInfo*)aPtr;
TInt mode=pR->iCpsr & EMaskMode;
TBool faultHandled = EFalse;
#ifdef __DEMAND_PAGING__
faultHandled |= M::DemandPagingFault(aPtr) == KErrNone;
#endif
if(!faultHandled)
faultHandled |= M::RamDefragFault(aPtr) == KErrNone;
if(faultHandled)
{
#ifdef __ATOMIC64_USE_SLOW_EXEC__
if (mode==ESvcMode && pR->iExcCode==EArmExceptionDataAbort && IsMagicAtomic64(pR->iR15))
{
// Magic atomic instruction so return to next instruction to stop any
// writes to memory being executed and ensure interrupts are enabled.
pR->iR15 += 4;
pR->iCpsr &= ~KAllInterruptsMask;
}
#endif
return;
}
if (mode==ESvcMode && pR->iExcCode==EArmExceptionDataAbort && IsMagic(pR->iR15))
{
// skip instruction that caused the exception, set the zero flag and place faulted address in r12
__KTRACE_OPT(KPANIC,DumpExcInfoX(*pR));
pR->iR15 += 4;
pR->iCpsr |= ECpuZf;
pR->iR12 = pR->iFaultAddress;
return;
}
DThread* pT=TheCurrentThread;
TExcTrap* xt=pT->iExcTrap;
if (xt)
{
__KTRACE_OPT(KPANIC,DumpExcInfoX(*pR));
// current thread wishes to handle exceptions
(*xt->iHandler)(xt,pT,aPtr);
}
if (NKern::HeldFastMutex()) // thread held fast mutex when exception occurred
Exc::Fault(aPtr);
#ifdef __CPU_HAS_VFP
if (pR->iExcCode==EArmExceptionUndefinedOpcode)
{
// Get the undefined instruction
GetUndefinedInstruction(pR);
const TUint32 opcode = pR->iFaultAddress;
TInt cpnum = -1;
#ifdef __SUPPORT_THUMB_INTERWORKING
if (!(pR->iCpsr & ECpuThumb)) {
#endif
// check for coprocessor instructions
// 10987654321098765432109876543210
// CDP: cond1110op1 CRn CRd cp_#op20CRm
// LDC: cond110PUNW1Rn CRd cp_#offset
// STC: cond110PUNW0Rn CRd cp_#offset
// MRC: cond1110op11CRn Rd cp_#op21CRm
// MCR: cond1110op10CRn Rd cp_#op21CRm
// ext: cond11000x0xRn CRd cp_#offset
//CDP2: 11111110xxxxxxxxxxxxxxxxxxx0xxxx
//LDC2: 1111110xxxx1xxxxxxxxxxxxxxxxxxxx
//STC2: 1111110xxxx0xxxxxxxxxxxxxxxxxxxx
//MRC2: 11111110xxx1xxxxxxxxxxxxxxx1xxxx
//MCR2: 11111110xxx0xxxxxxxxxxxxxxx1xxxx
//MRRC: cond11100101Rn Rd cp_#opc CRm
//MCRR: cond11100100Rn Rd cp_#opc CRm
//
//NEON data processing:
// 1111001xxxxxxxxxxxxxxxxxxxxxxxxx
//NEON element/structure load/store:
// 11110100xxx0xxxxxxxxxxxxxxxxxxxx
//
// Coprocessor instructions have 2nd hex digit (bits 24-27) C,D,E.
// The coprocessor number is in bits 8-11.
// NEON instructions have 1st hex digits F2, F3, or F4x where x is even
// No coprocessor number, route to cp 10
TUint32 hex2 = (opcode>>24) & 0x0f;
if (hex2==0xc || hex2==0xd || hex2==0xe)
cpnum=(opcode>>8)&0x0f;
#ifdef __CPU_ARMV7
else if ((opcode>>28)==0xf && (hex2==2 || hex2==3 || (hex2==4 && ((opcode>>20)&1)==0)))
