/*
* init_dma: Initialize DMA control register
*/
static void init_dma(bcm6352enet_softc *softc)
{
volatile DmaChannel *txDma = softc->txDma;
volatile DmaChannel *rxDma = softc->rxDma;
// transmit
txDma->cfg = 0; /* initialize first (will enable later) */
txDma->maxBurst = DMA_MAX_BURST_LENGTH;
txDma->intMask = 0; /* mask all ints */
txDma->intStat = DMA_DONE|DMA_NO_DESC|DMA_BUFF_DONE;
txDma->startAddr = (uint32_t) K1_TO_PHYS((uint32_t)softc->txBufPtr);
// receive
rxDma->cfg = 0; // initialize first (will enable later)
rxDma->maxBurst = DMA_MAX_BURST_LENGTH;
rxDma->startAddr = (uint32_t)K1_TO_PHYS((uint32_t)softc->rxFirstBdPtr);
rxDma->length = softc->nrRxBds;
rxDma->fcThreshold = 0;
rxDma->numAlloc = 0;
rxDma->intMask = 0; /* mask all ints */
/* clr any pending interrupts on channel */
rxDma->intStat = DMA_DONE|DMA_NO_DESC|DMA_BUFF_DONE;
/* set to interrupt on packet complete and no descriptor available */
rxDma->intMask = 0;
/* configure DMA channels and enable Rx */
rxDma->cfg = DMA_CHAINING|DMA_WRAP_EN;
}
/*
* init_dma: Initialize DMA control register
*/
static void init_dma(bcmenet_softc *softc)
{
uint32 *StateRam;
int i;
/*
* clear State RAM
*/
StateRam = (UINT32 *)&softc->dmaCtrl->stram.s[0];
for (i = 0; i < sizeof(DmaStateRam) / sizeof(UINT32) * NUM_CHANS_PER_EMAC * NUM_EMAC; i++)
StateRam[i] = 0;
/*
* initialize IUDMA controller register
*/
softc->dmaCtrl->controller_cfg = DMA_FLOWC_CH1_EN;
softc->dmaCtrl->flowctl_ch1_thresh_lo = DMA_FC_THRESH_LO;
softc->dmaCtrl->flowctl_ch1_thresh_hi = DMA_FC_THRESH_HI;
softc->dmaCtrl->flowctl_ch1_alloc = 0;
// transmit
softc->txDma->cfg = 0; /* initialize first (will enable later) */
softc->txDma->maxBurst = DMA_MAX_BURST_LENGTH;
softc->txDma->intMask = 0; /* mask all ints */
/* clr any pending interrupts on channel */
softc->txDma->intStat = DMA_DONE|DMA_NO_DESC|DMA_BUFF_DONE;
softc->txDma->intMask = DMA_DONE;
softc->dmaCtrl->stram.s[EMAC_TX_CHAN].baseDescPtr = (uint32)K1_TO_PHYS((uint32_t)(softc->txFirstBdPtr));
// receive
softc->rxDma->cfg = 0; // initialize first (will enable later)
softc->rxDma->maxBurst = DMA_MAX_BURST_LENGTH;
softc->rxDma->intMask = 0; /* mask all ints */
/* clr any pending interrupts on channel */
softc->rxDma->intStat = DMA_DONE|DMA_NO_DESC|DMA_BUFF_DONE;
softc->rxDma->intMask = DMA_DONE;
softc->dmaCtrl->stram.s[EMAC_RX_CHAN].baseDescPtr = (uint32)K1_TO_PHYS((uint32_t)(softc->rxFirstBdPtr));
}
void cfe_bootarea_init(void)
{
unsigned char *pte;
int64_t pte_int;
unsigned int addr = 16*MEG;
unsigned int topmem;
unsigned int topcfe;
unsigned int botcfe;
unsigned int beforecfe;
unsigned int aftercfe;
/*
* Calculate the location where the boot area will
* live. It lives either above or below the
* firmware, depending on where there's more space.
*/
/*
* The firmware will always be loaded in the first
* 256M. Calculate the top of that region. The bottom
* of that region is always the beginning of our
* data segment.
*/
if (mem_totalsize > (uint64_t)256) {
topmem = 256*MEG;
}
else {
topmem = (unsigned int) (mem_totalsize << 20);
}
botcfe = (unsigned int) K1_TO_PHYS(mem_bottomofmem);
topcfe = (unsigned int) K1_TO_PHYS(mem_topofmem);
beforecfe = botcfe;
aftercfe = topmem-topcfe;
if (beforecfe > aftercfe) {
botcfe -= (PAGESIZE-1);
botcfe &= ~(PAGESIZE-1); /* round down to page boundary */
addr = botcfe - CFE_BOOTAREA_SIZE; /* this is the address */
}
else {
topcfe += (PAGESIZE-1); /* round *up* to a page address */
topcfe &= ~(PAGESIZE-1);
addr = topcfe;
}
mem_bootarea_start = addr;
mem_bootarea_size = CFE_BOOTAREA_SIZE;
/*
* Allocate the page table
*/
pte = KMALLOC(1024,1024);
#ifdef __long64
pte_int = (int64_t) pte;
#else
pte_int = (int64_t) ((int) pte);
#endif
/*
* Set the CP0 CONTEXT register to point at the page table
*/
pte_int <<= 13;
cfe_pagetable = (uint64_t *) pte;
_setcontext(pte_int);
/*
* Initialize page table entries
*/
CPUCFG_PAGETBLINIT(cfe_pagetable,addr);
}
static int internal_open(bcmenet_softc * softc)
{
int i;
void *p;
/* make sure emac clock is on */
PERF->blkEnables |= EMAC_CLK_EN;
/* init rx/tx dma channels */
softc->dmaCtrl = (DmaRegs *)(EMAC_DMA_BASE);
softc->rxDma = &softc->dmaCtrl->chcfg[EMAC_RX_CHAN];
softc->txDma = &softc->dmaCtrl->chcfg[EMAC_TX_CHAN];
p = KMALLOC( NR_TX_BDS * sizeof(DmaDesc), CACHE_ALIGN );
if( p == NULL ) {
xprintf( "BCM6348 : Failed to allocate txBds memory.\n" );
return -1;
}
INVAL_RANGE(p, NR_TX_BDS * sizeof(DmaDesc));
softc->txBds = (DmaDesc *)K0_TO_K1((uint32) p);
p = KMALLOC( NR_RX_BDS * sizeof(DmaDesc), CACHE_ALIGN );
if( p== NULL ) {
xprintf( "BCM6348 : Failed to allocate rxBds memory.\n" );
KFREE( (void *)(softc->txBds) );
softc->txBds = NULL;
return -1;
}
INVAL_RANGE(p, NR_RX_BDS * sizeof(DmaDesc));
softc->rxBds = (DmaDesc *)K0_TO_K1((uint32) p);
softc->rxBuffers = (uint32_t)KMALLOC( NR_RX_BDS * ENET_BUF_SIZE, CACHE_ALIGN );
if( softc->rxBuffers == NULL ) {
xprintf( "BCM6348 : Failed to allocate RxBuffer memory.\n" );
KFREE( (void *)(softc->txBds) );
softc->txBds = NULL;
KFREE( (void *)(softc->rxBds) );
softc->rxBds = NULL;
return -1;
}
INVAL_RANGE(softc->rxBuffers, NR_RX_BDS * ENET_BUF_SIZE);
softc->txBuffers = (uint32_t)KMALLOC( NR_TX_BDS * ENET_BUF_SIZE, CACHE_ALIGN );
if( softc->txBuffers == NULL ) {
xprintf( "BCM6348 : Failed to allocate txBuffer memory.\n" );
KFREE( (void *)(softc->rxBuffers) );
softc->rxBuffers = NULL;
KFREE( (void *)(softc->txBds) );
softc->txBds = NULL;
KFREE( (void *)(softc->rxBds) );
softc->rxBds = NULL;
return -1;
}
INVAL_RANGE(softc->txBuffers, NR_TX_BDS * ENET_BUF_SIZE);
/* Init the Receive Buffer Descriptor Ring. */
softc->rxFirstBdPtr = softc->rxBdReadPtr = softc->rxBds;
softc->rxLastBdPtr = softc->rxBds + NR_RX_BDS - 1;
for(i = 0; i < NR_RX_BDS; i++) {
(softc->rxBds + i)->status = DMA_OWN;
(softc->rxBds + i)->length = ENET_BUF_SIZE;
(softc->rxBds + i)->address = softc->rxBuffers + i * ENET_BUF_SIZE;
(softc->rxBds + i)->address = K1_TO_PHYS( (softc->rxBds + i)->address );
softc->dmaCtrl->flowctl_ch1_alloc = 1;
}
softc->rxLastBdPtr->status |= DMA_WRAP;
/* Init Transmit Buffer Descriptor Ring. */
softc->txFirstBdPtr = softc->txNextBdPtr = softc->txBds;
softc->txLastBdPtr = softc->txBds + NR_TX_BDS - 1;
for(i = 0; i < NR_TX_BDS; i++) {
(softc->txBds + i)->status = 0;
(softc->txBds + i)->length = 0;
(softc->txBds + i)->address = softc->txBuffers + i * ENET_BUF_SIZE;
(softc->txBds + i)->address = K1_TO_PHYS( (softc->txBds + i)->address );
}
softc->txLastBdPtr->status = DMA_WRAP;
/* init dma registers */
init_dma(softc);
/* init enet control registers */
if (init_emac(softc))
return -1;
getMacAddress(softc->hwaddr);
bcm6348_write_mac_address( softc, softc->hwaddr);
softc->rxDma->cfg |= DMA_ENABLE;
return 0;
}
