/*****************************************
@brief process mipi sequence table
@param table: lcd init code, count: sizeof(table), lcd_panel: lcd type
mfd:mipi need ,tp: process mipi buffer.
@return none
******************************************/
void process_mipi_table(struct msm_fb_data_type *mfd,struct dsi_buf *tp,
struct sequence *table, size_t count, lcd_panel_type lcd_panel)
{
unsigned int i = 0;
uint32 reg = 0;
uint32 value = 0;
uint32 time = 0;
for (i = 0; i < count; i++)
{
reg = table[i].reg;
value = table[i].value;
time = table[i].time;
switch(lcd_panel)
{
case MIPI_RSP61408_CHIMEI_WVGA:
case MIPI_RSP61408_BYD_WVGA:
case MIPI_RSP61408_TRULY_WVGA:
case MIPI_HX8357C_TIANMA_IPS_HVGA:
case MIPI_HX8357C_CHIMEI_HVGA:
case MIPI_HX8357C_TIANMA_HVGA:
case MIPI_HX8369A_TIANMA_WVGA:
case MIPI_HX8357C_CHIMEI_IPS_HVGA:
mipi_lcd_register_write(mfd,tp,reg,value,0);
break;
default:
break;
}
if (time != 0)
{
LCD_MDELAY(time);
}
}
}
/*****************************************
@brief process mipi sequence table
@param table: lcd init code, count: sizeof(table), lcd_panel: lcd type
mfd:mipi need ,tp: process mipi buffer.
@return none
******************************************/
void process_mipi_table(struct msm_fb_data_type *mfd,struct dsi_buf *tp,
const struct sequence *table, size_t count, lcd_panel_type lcd_panel)
{
unsigned int i = 0;
uint32 reg = 0;
uint32 value = 0;
uint32 time = 0;
for (i = 0; i < count; i++)
{
reg = table[i].reg;
value = table[i].value;
time = table[i].time;
mipi_lcd_register_write(mfd,tp,reg,value,0);
if (time != 0)
{
LCD_MDELAY(time);
}
}
}
int process_mddi_table(struct sequence *table, size_t count, lcd_panel_type lcd_panel)
{
unsigned int i;
uint32 reg = 0;
uint32 value = 0;
uint32 time = 0;
int ret = 0;
int clk_on = 0;
for (i = 0; i < count; i++)
{
reg = table[i].reg;
value = table[i].value;
time = table[i].time;
switch(lcd_panel)
{
case LCD_NT35582_BYD_WVGA:
case LCD_NT35582_TRULY_WVGA:
case LCD_NT35510_ALPHA_SI_WVGA:
case LCD_NT35560_TOSHIBA_FWVGA:
case LCD_NT35510_ALPHA_SI_WVGA_TYPE2:
down(&mdp_pipe_ctrl_mutex);
clk_on = pmdh_clk_func(2);
pmdh_clk_func(1);
/* MDDI port to write the reg and value */
ret = mddi_queue_register_write(reg,value,TRUE,0);
if (clk_on == 0)
{
pmdh_clk_func(0);
}
up(&mdp_pipe_ctrl_mutex);
break;
case MDDI_RSP61408_CHIMEI_WVGA:
case MDDI_RSP61408_BYD_WVGA:
case MDDI_HX8369A_TIANMA_WVGA:
case MDDI_HX8357C_CHIMEI_HVGA:
case MDDI_HX8357C_TIANMA_HVGA:
case MDDI_HX8357C_CHIMEI_IPS_HVGA:
down(&mdp_pipe_ctrl_mutex);
clk_on = pmdh_clk_func(2);
pmdh_clk_func(1);
ret = mddi_multi_register_write(reg,value);
if (clk_on == 0)
{
pmdh_clk_func(0);
}
up(&mdp_pipe_ctrl_mutex);
break;
default:
break;
}
if (time != 0)
{
LCD_MDELAY(time);
}
}
return ret;
}
int process_lcdc_table(struct sequence *table, size_t count, lcd_panel_type lcd_panel)
{
unsigned int i;
uint32 reg = 0;
uint32 value = 0;
uint32 time = 0;
uint8 start_byte = 0;
int ret = 0;
for (i = 0; i < count; i++)
{
reg = table[i].reg;
value = table[i].value;
time = table[i].time;
switch(lcd_panel)
{
case LCD_S6D74A0_SAMSUNG_HVGA:
seriout_ext((uint16)reg, (uint16)value, (uint16)time);
break;
case LCD_HX8368A_SEIKO_QVGA:
case LCD_HX8368A_TRULY_QVGA:
if (value & TYPE_COMMAND)
{
start_byte = START_BYTE_COMMAND;
}
else if (value & TYPE_PARAMETER)
{
start_byte = START_BYTE_PARAMETER;
}
/* 16 bit SPI to write the command and data */
seriout_transfer_byte((uint8)reg, start_byte);
break;
case LCD_HX8357B_TIANMA_HVGA:
case LCD_S6D05A0_INNOLUX_HVGA:
case LCD_R61529_TRULY_HVGA:
case LCD_ILI9481D_INNOLUX_HVGA:
case LCD_ILI9481DS_TIANMA_HVGA:
/*add an new lcd for U8510*/
case LCD_NT35410_CHIMEI_HVGA:
if (value & TYPE_COMMAND)
{
start_byte = START_BYTE_COMMAND;
}
else if (value & TYPE_PARAMETER)
{
start_byte = START_BYTE_PARAMETER;
}
/* 9 bit SPI to write the command and data */
seriout_byte_9bit(start_byte, (uint8)reg);
break;
// Ignore MDDI displays
case LCD_MDDI_NT35582_BYD_WVGA:
case LCD_MDDI_NT35582_TRULY_WVGA:
case LCD_MDDI_NT35510_ALPHA_SI_WVGA:
default:
break;
}
if (time != 0)
{
LCD_MDELAY(time);
}
}
return ret;
}
