static void radeonQueryGetResult(struct gl_context *ctx, struct gl_query_object *q)
{
struct radeon_query_object *query = (struct radeon_query_object *)q;
uint32_t *result;
int i;
radeon_print(RADEON_STATE, RADEON_VERBOSE,
"%s: query id %d, result %d\n",
__FUNCTION__, query->Base.Id, (int) query->Base.Result);
radeon_bo_map(query->bo, GL_FALSE);
result = query->bo->ptr;
query->Base.Result = 0;
for (i = 0; i < query->curr_offset/sizeof(uint32_t); ++i) {
query->Base.Result += LE32_TO_CPU(result[i]);
radeon_print(RADEON_STATE, RADEON_TRACE, "result[%d] = %d\n", i, LE32_TO_CPU(result[i]));
}
radeon_bo_unmap(query->bo);
}
static void emit_ubyte_rgba4( GLcontext *ctx,
struct r200_dma_region *rvb,
char *data,
int stride,
int count )
{
int i;
int *out = (int *)(rvb->address + rvb->start);
if (R200_DEBUG & DEBUG_VERTS)
fprintf(stderr, "%s count %d stride %d\n",
__FUNCTION__, count, stride);
if (stride == 4) {
for (i = 0; i < count; i++)
((int *)out)[i] = LE32_TO_CPU(((int *)data)[i]);
} else {
for (i = 0; i < count; i++) {
*(int *)out++ = LE32_TO_CPU(*(int *)data);
data += stride;
}
}
}
/**
* i40e_read_dword - read HMC context dword into struct
* @hmc_bits: pointer to the HMC memory
* @ce_info: a description of the struct to be filled
* @dest: the struct to be filled
**/
static void i40e_read_dword(u8 *hmc_bits,
struct i40e_context_ele *ce_info,
u8 *dest)
{
u32 dest_dword, mask;
u8 *src, *target;
u16 shift_width;
__le32 src_dword;
/* prepare the bits and mask */
shift_width = ce_info->lsb % 8;
/* if the field width is exactly 32 on an x86 machine, then the shift
* operation will not work because the SHL instructions count is masked
* to 5 bits so the shift will do nothing
*/
if (ce_info->width < 32)
mask = ((u32)1 << ce_info->width) - 1;
else
mask = ~(u32)0;
/* shift to correct alignment */
mask <<= shift_width;
/* get the current bits from the src bit string */
src = hmc_bits + (ce_info->lsb / 8);
i40e_memcpy(&src_dword, src, sizeof(src_dword), I40E_DMA_TO_NONDMA);
/* the data in the memory is stored as little endian so mask it
* correctly
*/
src_dword &= ~(CPU_TO_LE32(mask));
/* get the data back into host order before shifting */
dest_dword = LE32_TO_CPU(src_dword);
dest_dword >>= shift_width;
/* get the address from the struct field */
target = dest + ce_info->offset;
/* put it back in the struct */
i40e_memcpy(target, &dest_dword, sizeof(dest_dword),
I40E_NONDMA_TO_DMA);
}
static void emit_ubyte_rgba4( GLcontext *ctx,
struct radeon_dma_region *rvb,
char *data,
int stride,
int count )
{
int i;
int *out = (int *)(rvb->address + rvb->start);
if (RADEON_DEBUG & DEBUG_VERTS)
fprintf(stderr, "%s count %d stride %d\n",
__FUNCTION__, count, stride);
if (stride == 4)
COPY_DWORDS( out, data, count );
else
for (i = 0; i < count; i++) {
*out++ = LE32_TO_CPU(*(int *)data);
data += stride;
}
}
static void radeonQueryGetResult(struct gl_context *ctx, struct gl_query_object *q)
{
radeonContextPtr radeon = RADEON_CONTEXT(ctx);
struct radeon_query_object *query = (struct radeon_query_object *)q;
uint32_t *result;
int i;
radeon_print(RADEON_STATE, RADEON_VERBOSE,
"%s: query id %d, result %d\n",
__FUNCTION__, query->Base.Id, (int) query->Base.Result);
radeon_bo_map(query->bo, GL_FALSE);
result = query->bo->ptr;
query->Base.Result = 0;
if (IS_R600_CLASS(radeon->radeonScreen)) {
/* ZPASS EVENT writes alternating qwords
* At query start we set the start offset to 0 and
* hw writes zpass start counts to qwords 0, 2, 4, 6.
* At query end we set the start offset to 8 and
* hw writes zpass end counts to qwords 1, 3, 5, 7.
* then we substract. MSB is the valid bit.
*/
for (i = 0; i < 32; i += 4) {
uint64_t start = (uint64_t)LE32_TO_CPU(result[i]) |
(uint64_t)LE32_TO_CPU(result[i + 1]) << 32;
uint64_t end = (uint64_t)LE32_TO_CPU(result[i + 2]) |
(uint64_t)LE32_TO_CPU(result[i + 3]) << 32;
if ((start & 0x8000000000000000) && (end & 0x8000000000000000)) {
uint64_t query_count = end - start;
query->Base.Result += query_count;
}
radeon_print(RADEON_STATE, RADEON_TRACE,
"%d start: %" PRIu64 ", end: %" PRIu64 " %" PRIu64 "\n", i, start, end, end - start);
}
} else {
for (i = 0; i < query->curr_offset/sizeof(uint32_t); ++i) {
query->Base.Result += LE32_TO_CPU(result[i]);
radeon_print(RADEON_STATE, RADEON_TRACE, "result[%d] = %d\n", i, LE32_TO_CPU(result[i]));
}
}
radeon_bo_unmap(query->bo);
}
int32_t
rs22_ssp_bus_request_synch
(
struct bus_cmd_s *cmd
)
{
struct cmd_fmt_s tx_cmd;
int32_t status = RSI_STATUS_FAIL;
int32_t tknStatus = RSI_STATUS_SUCCESS;
uint8_t rx_buf[8];
uint16_t busy_retry = 0;
/* Enter the Critical section */
rs22_memset((uint8_t *)&tx_cmd, 0, sizeof(struct cmd_fmt_s));
rs22_memset((void *)rx_buf, 0, 8);
switch(cmd->type)
{
case SPI_INITIALIZATION:
{
/* Form C1 here */
tx_cmd.buf[0] = CMD_INITIALIZATION;
/* Form C2 here */
tx_cmd.buf[1] = 0x00;//Dummy data to send
#if USE_NO_DMA
rs22_ssp_send_and_receive((uint8_t *)(&tx_cmd.buf[0]), rx_buf, 2);
#else
rs22_ssp_send_and_receive_with_dma((uint8_t *)(&tx_cmd.buf[0]), rx_buf, 2);
#endif
/* Check the status */
if (rx_buf[1] == SPI_STATUS_SUCCESS)
{
status = RSI_STATUS_SUCCESS;
}
else if (rx_buf[1] == SPI_STATUS_FAILURE)
{
status = RSI_STATUS_FAIL;
}
else
{
status = RSI_STATUS_FAIL;
} /* End if <condition> */
}
break;
case SPI_INTERNAL_READ:
{
/* Prepare the cmd */
/* Form C1 here */
tx_cmd.buf[0] = CMD_READ_WRITE;
tx_cmd.buf[0] |= (uint8_t)(cmd->length & 0x0003);
/* Only LSB 5 bits of the address are valid */
/* Form C2 here */
tx_cmd.buf[1] |= (uint8_t)(cmd->address & 0x3F);
#if USE_NO_DMA
/* Send the cmd and receive the status */
rs22_ssp_send_and_receive((uint8_t *)&tx_cmd.buf[0], rx_buf, 2);
#else
rs22_ssp_send_and_receive_with_dma((uint8_t *)&tx_cmd.buf[0], rx_buf, 2);
#endif
/* Check the status */
if ((rx_buf[1] == SPI_STATUS_SUCCESS))
{
tknStatus = rs22_ssp_receive_start_token();
if (tknStatus == RSI_STATUS_BUSY)
{
status = RSI_STATUS_BUSY;
break;
}
else if (tknStatus == RSI_STATUS_FAIL)
{
status = RSI_STATUS_FAIL;
break;
}
else
{
while(0);
} /* End if <condition> */
/* Send C3 and C4 (length in 2bytes) here */
#if USE_NO_DMA
glbl_glbl_count = 1;
/* Send the junk data and receive the required data */
rs22_ssp_send_and_receive(junk, cmd->data, cmd->length);
glbl_glbl_count = 2;
#else
rs22_ssp_send_and_receive_with_dma(junk, cmd->data, cmd->length);
#endif
status = RSI_STATUS_SUCCESS;
}
else if (rx_buf[1] == SPI_STATUS_BUSY)
{
status = RSI_STATUS_BUSY;
}
else if (rx_buf[1] == SPI_STATUS_FAILURE)
{
status = RSI_STATUS_FAIL;
}
else
{
if(rx_buf[1] == 0xa4)
status = RSI_STATUS_FAIL;
}
}
break;
case SPI_INTERNAL_WRITE:
{
/* Prepare the cmd */
/* Form C1 here */
tx_cmd.buf[0] = CMD_READ_WRITE;
tx_cmd.buf[0] |= CMD_WRITE;
tx_cmd.buf[0] |= (uint8_t)(cmd->length & 0x0003);
/* Only LSB 5 bits of the address are valid */
//tx_cmd.buf[1] |= (uint8_t)(cmd->address & 0x3F);
/* Form C2 here */
tx_cmd.buf[1] |= (uint8_t)LE32_TO_CPU((cmd->address & 0xFF000000));
/* Send C1 & C2 here */
#if USE_NO_DMA
/* Send the cmd and receive the status */
rs22_ssp_send_and_receive((uint8_t *)&tx_cmd.buf[0],rx_buf, 2);
#else
rs22_ssp_send_and_receive_with_dma((uint8_t *)&tx_cmd.buf[0],rx_buf, 2);
#endif
/* Check the status */
if (rx_buf[1] == SPI_STATUS_SUCCESS)
{
/* Send C3 & C4 here */
#if USE_NO_DMA
/* Send the data the junk data */
/* Here there are no issues while receiving junk data as cmd->length equals 2 only */
rs22_ssp_send_and_receive(cmd->data, rx_buf, cmd->length);
#else
rs22_ssp_send_and_receive_with_dma(cmd->data, rx_buf, cmd->length);
#endif
status = RSI_STATUS_SUCCESS;
}
else if (rx_buf[1] == SPI_STATUS_BUSY)
{
status = RSI_STATUS_BUSY;
}
else if (rx_buf[1] == SPI_STATUS_FAILURE)
{
status = RSI_STATUS_FAIL;
break;
}
else
{
status = RSI_STATUS_FAIL;
} /* End if <condition> */
}
break;
case AHB_MASTER_READ:
{
/* Prepare the cmd */
/* Form C1, C2, C3 and C4 here */
tx_cmd.buf[0] = CMD_READ_WRITE;
tx_cmd.buf[0] |= AHB_BUS_ACCESS;
tx_cmd.buf[0] |= TRANSFER_LEN_16_BITS;
*(uint16_t *)&tx_cmd.buf[2] = cmd->length;
#if USE_NO_DMA
/* Send the cmd and receive the response */
/* Send C1, C2, C3 and C4 here */
rs22_ssp_send_and_receive((uint8_t *)&tx_cmd.buf[0], &rx_buf[0], 4);
/* Send the address and receive the response */
/* Send A1, A2, A3 and A4 here */
rs22_ssp_send_and_receive((uint8_t *)(&(cmd->address)), &rx_buf[4], 4);
#else
rs22_ssp_send_and_receive_with_dma((uint8_t *)&tx_cmd.buf[0], &rx_buf[0], 4);
rs22_ssp_send_and_receive_with_dma((uint8_t *)(&(cmd->address)), &rx_buf[4], 4);
#endif
/* Check the status */
if (rx_buf[1] == SPI_STATUS_SUCCESS)
{
tknStatus = rs22_ssp_receive_start_token();
if (tknStatus == RSI_STATUS_BUSY)
{
status = RSI_STATUS_BUSY;
}
else if (tknStatus == RSI_STATUS_FAIL)
{
status = RSI_STATUS_FAIL;
}
else
{
/* Here we can read the data using DMA */
//rs22_ssp_send_and_receive_with_dma(junk, cmd->data, cmd->length);
rs22_ssp_send_and_receive(junk, cmd->data, cmd->length);
status = RSI_STATUS_SUCCESS;
} /* End if <condition> */
}
else if (rx_buf[1] == SPI_STATUS_BUSY)
{
status = RSI_STATUS_BUSY;
}
else if (rx_buf[1] == SPI_STATUS_FAILURE)
{
status = RSI_STATUS_FAIL;
}
else
{
status = RSI_STATUS_FAIL;
} /* End if <condition> */
}
break;
case AHB_MASTER_WRITE:
{
/* Prepare the cmd */
/* Form C1 and C2 here */
tx_cmd.buf[0] = CMD_READ_WRITE;
tx_cmd.buf[0] |= CMD_WRITE;
tx_cmd.buf[0] |= AHB_BUS_ACCESS;
tx_cmd.buf[0] |= TRANSFER_LEN_16_BITS;
tx_cmd.buf[1] = 0x00;
//Here cmd->length need a big endian to little endian converstion
/* Form C3 and C4 here */
tx_cmd.buf[2] = LOBYTE(cmd->length);
tx_cmd.buf[3] = HIBYTE(cmd->length);
// Lets try the following code for the same
do
{
/* Send C1 and C2 here */
#if USE_NO_DMA
rs22_ssp_send_and_receive((uint8_t *)&tx_cmd.buf[0], rx_buf, 2);
#else
rs22_ssp_send_and_receive_with_dma((uint8_t *)&tx_cmd.buf[0], rx_buf, 2);
#endif
if(rx_buf[1] == SPI_STATUS_SUCCESS)
{
/* Send C3 and C4 here first and A1, A2, A3 and A4 here */
#if USE_NO_DMA
rs22_ssp_send_and_receive((uint8_t *)&(tx_cmd.buf[2]), &rx_buf[2], 2);
rs22_ssp_send_and_receive((uint8_t *)&(cmd->address), &rx_buf[4], 4);
#else
rs22_ssp_send_and_receive_with_dma((uint8_t *)&(tx_cmd.buf[2]), &rx_buf[2], 2);
rs22_ssp_send_and_receive_with_dma((uint8_t *)&(cmd->address), &rx_buf[4], 4);
#endif
break;
}
else if ((rx_buf[1]== SPI_STATUS_BUSY) && busy_retry < 5)
{
busy_retry++;//Added by srinivas
continue;
}
else
{
break;
}
}while(1);
/* Check the status */
if (rx_buf[1] == SPI_STATUS_SUCCESS)
{
/* Send the data */
//Here if it doesn't work then try to use rs22_ssp_send_and_receive,
//by increasing the rx_buf size. Take care of the increased length,
//which is not the feasible solution. Otherwise uncomment above for loop code
/* Send the data here, we can also use DMA */
//rs22_ssp_send_and_receive_junk_with_dma((uint8_t*)(cmd->data), cmd->length);
rs22_ssp_send_and_receive_junk((uint8_t*)(cmd->data), cmd->length);
status = RSI_STATUS_SUCCESS;
}
else if (rx_buf[1] == SPI_STATUS_BUSY)
{
status = RSI_STATUS_BUSY;
}
else if (rx_buf[1] == SPI_STATUS_FAILURE)
{
status = RSI_STATUS_FAIL;
}
else
{
status = RSI_STATUS_FAIL;
} /* End if <condition> */
}
break;
case AHB_SLAVE_READ:
{
/* Prepare the cmd */
/* Form C1 here */
tx_cmd.buf[0] = CMD_READ_WRITE;
tx_cmd.buf[0] |= AHB_BUS_ACCESS;
tx_cmd.buf[0] |= AHB_SLAVE;
tx_cmd.buf[0] |= TRANSFER_LEN_16_BITS;
//Since we are using only 8-bit granularity, commented the above statement
//Following supports only for 8-bit granularity
/* Form C2 here */
tx_cmd.buf[1] = 0x00;//(uint8_t)cmd->address;
/* Form C3 and C4 here */
tx_cmd.buf[2] = LOBYTE(cmd->length);
tx_cmd.buf[3] = HIBYTE(cmd->length);
/* Send C1, C2, C3 and C4 here */
#if USE_NO_DMA
/* Send the cmd and receive the response */
rs22_ssp_send_and_receive((uint8_t *)&tx_cmd.buf[0], rx_buf, 2);
#else
rs22_ssp_send_and_receive_with_dma((uint8_t *)&tx_cmd.buf[0], rx_buf, 4);
#endif
/* Check the status */
//if (rx_buf[1] == SPI_STATUS_SUCCESS)
if ((rx_buf[1] != SPI_STATUS_BUSY) && (rx_buf[1] != SPI_STATUS_FAILURE))
{
rs22_ssp_send_and_receive((uint8_t *)(&(tx_cmd.buf[2])), rx_buf, 2);
/* Get the Start token first */
tknStatus = rs22_ssp_receive_start_token();
if (tknStatus == RSI_STATUS_BUSY)
{
status = RSI_STATUS_BUSY;
}
else if (tknStatus == RSI_STATUS_FAIL)
{
status = RSI_STATUS_FAIL;
}
else
{
/* Reading data using DMA */
//rs22_ssp_send_junk_and_receive_with_dma(&((uint8_t *)cmd->data)[0],cmd->length);
rs22_ssp_send_junk_and_receive(&((uint8_t *)cmd->data)[0],cmd->length); status = RSI_STATUS_SUCCESS;
status = RSI_STATUS_SUCCESS;
}
}
else if (rx_buf[1] == SPI_STATUS_BUSY)
{
status = RSI_STATUS_BUSY;
}
else if( rx_buf[1] == SPI_STATUS_FAILURE)
{
status = RSI_STATUS_FAIL;
}
else
{
status = RSI_STATUS_FAIL;
} /* End if <condition> */
}
break;
case AHB_SLAVE_WRITE:
{
/* Prepare the cmd */
/* Form C1 here */
tx_cmd.buf[0] = CMD_READ_WRITE;
tx_cmd.buf[0] |= CMD_WRITE;
tx_cmd.buf[0] |= AHB_BUS_ACCESS;
tx_cmd.buf[0] |= AHB_SLAVE;
tx_cmd.buf[0] |= TRANSFER_LEN_16_BITS;
/* Form C2 here */
tx_cmd.buf[1] = (cmd->address);
tx_cmd.buf[2] = LOBYTE(cmd->length);
tx_cmd.buf[3] = HIBYTE(cmd->length);
/* Send C1 and C2 here */
#if USE_NO_DMA
/* Send the cmd and receive the status */
rs22_ssp_send_and_receive((uint8_t *)&tx_cmd.buf[0], rx_buf, 2);
#else
rs22_ssp_send_and_receive_with_dma((uint8_t *)&tx_cmd.buf[0], rx_buf, 2);
#endif
/* Check the status */
// if ((rx_buf[1] == SPI_STATUS_SUCCESS) || (rx_buf[1] == 0xa4))
if ((rx_buf[1] != SPI_STATUS_BUSY) && (rx_buf[1] != SPI_STATUS_FAILURE))
{
/* Send C3 and C4 here */
#if USE_NO_DMA
/* Send the remaining cmd and receive the status */
rs22_ssp_send_and_receive((uint8_t *)(&(tx_cmd.buf[2])), rx_buf, 2);
#else
rs22_ssp_send_and_receive_with_dma((uint8_t *)(&(tx_cmd.buf[2])), &rx_buf[2], 2);
#endif
/* Send data using DMA here */
/* Above two can be combined -- FIXME: Srinivas */
//rs22_ssp_send_and_receive_junk_with_dma(cmd->data, cmd->length);
rs22_ssp_send_and_receive_junk(cmd->data, cmd->length);
status = RSI_STATUS_SUCCESS;
}
else if (rx_buf[1] == SPI_STATUS_BUSY)
{
status = RSI_STATUS_BUSY;
}
else if (rx_buf[1] == SPI_STATUS_FAILURE)
{
status = RSI_STATUS_FAIL;
}
else
{
status = RSI_STATUS_FAIL;
} /* End if <condition> */
}
break;
default:
{
status = RSI_STATUS_FAIL;
}
break;
}
return(status);
}
static void radeon_Color4ubv_ub( const GLubyte *v )
{
*(GLuint *)vb.colorptr = LE32_TO_CPU(*(GLuint *)v);
}
static void r200_Color4ubv_ub( const GLubyte *v )
{
GET_CURRENT_CONTEXT(ctx);
r200ContextPtr rmesa = R200_CONTEXT(ctx);
*(GLuint *)rmesa->vb.colorptr = LE32_TO_CPU(*(GLuint *)v);
}
void uart_config(uint8_t port, usb_cdc_line_coding_t * cfg)
{
Usart* usart = get_usart(port);
uint32_t stopbits, parity, databits;
uint32_t imr;
switch (cfg->bCharFormat) {
case CDC_STOP_BITS_2:
stopbits = US_MR_NBSTOP_2_BIT;
break;
case CDC_STOP_BITS_1_5:
stopbits = US_MR_NBSTOP_1_5_BIT;
break;
case CDC_STOP_BITS_1:
default:
// Default stop bit = 1 stop bit
stopbits = US_MR_NBSTOP_1_BIT;
break;
}
switch (cfg->bParityType) {
case CDC_PAR_EVEN:
parity = US_MR_PAR_EVEN;
break;
case CDC_PAR_ODD:
parity = US_MR_PAR_ODD;
break;
case CDC_PAR_MARK:
parity = US_MR_PAR_MARK;
break;
case CDC_PAR_SPACE:
parity = US_MR_PAR_SPACE;
break;
default:
case CDC_PAR_NONE:
parity = US_MR_PAR_NO;
break;
}
switch(cfg->bDataBits) {
case 5: case 6: case 7:
databits = cfg->bDataBits - 5;
break;
default:
case 8:
databits = US_MR_CHRL_8_BIT;
break;
}
// Options for USART.
usart_options.baudrate = LE32_TO_CPU(cfg->dwDTERate);
usart_options.char_length = databits;
usart_options.parity_type = parity;
usart_options.stop_bits = stopbits;
usart_options.channel_mode = US_MR_CHMODE_NORMAL;
imr = usart_get_interrupt_mask(usart);
usart_disable_interrupt(usart, 0xFFFFFFFF);
usart_init_rs232(usart, &usart_options,
sysclk_get_peripheral_hz());
// Restore both RX and TX
usart_enable_tx(usart);
usart_enable_rx(usart);
usart_enable_interrupt(usart, imr);
}
static void write_BOOT_PARAM(void)
{
uint32_t spi_API = 0;
uint16_t spi_API16 = 0;
AJ_AlwaysPrintf(("\n\n**************\nTEST: %s\n\n", __FUNCTION__));
// read the clock speed value
spi_API = 0x88888888;
AJ_WSL_SPI_HostControlRegisterWrite(AJ_WSL_SPI_TARGET_ADDR_READ + 1, FALSE, 4, (uint8_t*)&spi_API);
spi_API = 0x42424242;
AJ_WSL_SPI_HostControlRegisterWrite(AJ_WSL_SPI_TARGET_ADDR_READ + 2, FALSE, 4, (uint8_t*)&spi_API);
spi_API = 0x00000000;
AJ_WSL_SPI_HostControlRegisterWrite(AJ_WSL_SPI_TARGET_ADDR_READ + 3, FALSE, 4, (uint8_t*)&spi_API);
spi_API = AJ_WSL_SPI_TARGET_CLOCK_SPEED_ADDR; //0x00428878;
spi_API = CPU_TO_LE32(spi_API);
AJ_WSL_SPI_HostControlRegisterWrite(AJ_WSL_SPI_TARGET_ADDR_READ, TRUE, 4, (uint8_t*)&spi_API);
// now read back the value from the data port.
AJ_WSL_SPI_HostControlRegisterRead(AJ_WSL_SPI_TARGET_VALUE, TRUE, 4, (uint8_t*)&spi_API);
spi_API = LE32_TO_CPU(spi_API);
//AJ_InfoPrintf(("cycles read back was %ld \n", spi_API));
// read the flash is present value
{
// let's try this dance of writing multiple times...
spi_API = 0x88888888;
AJ_WSL_SPI_HostControlRegisterWrite(AJ_WSL_SPI_TARGET_ADDR_READ + 1, FALSE, 4, (uint8_t*)&spi_API);
spi_API = 0x42424242;
AJ_WSL_SPI_HostControlRegisterWrite(AJ_WSL_SPI_TARGET_ADDR_READ + 2, FALSE, 4, (uint8_t*)&spi_API);
spi_API = 0x00000000;
AJ_WSL_SPI_HostControlRegisterWrite(AJ_WSL_SPI_TARGET_ADDR_READ + 3, FALSE, 4, (uint8_t*)&spi_API);
spi_API = AJ_WSL_SPI_TARGET_FLASH_PRESENT_ADDR; //0x0042880C;
spi_API = CPU_TO_LE32(spi_API);
AJ_WSL_SPI_HostControlRegisterWrite(AJ_WSL_SPI_TARGET_ADDR_READ, TRUE, 4, (uint8_t*)&spi_API);
// now read back the value from the data port.
AJ_WSL_SPI_HostControlRegisterRead(AJ_WSL_SPI_TARGET_VALUE, TRUE, 4, (uint8_t*)&spi_API);
spi_API = LE32_TO_CPU(spi_API);
//AJ_InfoPrintf(("host if flash is present read back was %ld \n", spi_API));
}
// now write out the flash_is_present value
spi_API = 0x00000002;
spi_API = CPU_TO_LE32(spi_API);
AJ_WSL_SPI_HostControlRegisterWrite(AJ_WSL_SPI_TARGET_VALUE, TRUE, 4, (uint8_t*)&spi_API);
spi_API = 0x88888888;
AJ_WSL_SPI_HostControlRegisterWrite(AJ_WSL_SPI_TARGET_ADDR_WRITE + 1, FALSE, 4, (uint8_t*)&spi_API);
spi_API = 0x42424242;
AJ_WSL_SPI_HostControlRegisterWrite(AJ_WSL_SPI_TARGET_ADDR_WRITE + 2, FALSE, 4, (uint8_t*)&spi_API);
spi_API = 0x00000000;
AJ_WSL_SPI_HostControlRegisterWrite(AJ_WSL_SPI_TARGET_ADDR_WRITE + 3, FALSE, 4, (uint8_t*)&spi_API);
spi_API = AJ_WSL_SPI_TARGET_FLASH_PRESENT_ADDR; //0x0042880C;
spi_API = CPU_TO_LE32(spi_API);
AJ_WSL_SPI_HostControlRegisterWrite(AJ_WSL_SPI_TARGET_ADDR_WRITE, TRUE, 4, (uint8_t*)&spi_API);
// read the mbox block size
spi_API = 0x88888888;
AJ_WSL_SPI_HostControlRegisterWrite(AJ_WSL_SPI_TARGET_ADDR_READ + 1, FALSE, 4, (uint8_t*)&spi_API);
spi_API = 0x42424242;
AJ_WSL_SPI_HostControlRegisterWrite(AJ_WSL_SPI_TARGET_ADDR_READ + 2, FALSE, 4, (uint8_t*)&spi_API);
spi_API = 0x00000000;
AJ_WSL_SPI_HostControlRegisterWrite(AJ_WSL_SPI_TARGET_ADDR_READ + 3, FALSE, 4, (uint8_t*)&spi_API);
spi_API = AJ_WSL_SPI_TARGET_MBOX_BLOCKSZ_ADDR; //0x0042886C;
spi_API = CPU_TO_LE32(spi_API);
AJ_WSL_SPI_HostControlRegisterWrite(AJ_WSL_SPI_TARGET_ADDR_READ, TRUE, 4, (uint8_t*)&spi_API);
// now read back the value from the data port.
AJ_WSL_SPI_HostControlRegisterRead(AJ_WSL_SPI_TARGET_VALUE, TRUE, 4, (uint8_t*)&spi_API);
spi_API = LE32_TO_CPU(spi_API);
AJ_WSL_MBOX_BLOCK_SIZE = spi_API;
//AJ_InfoPrintf(("block size was %ld \n", spi_API));
spi_API16 = 0x001f;
spi_API16 = CPU_TO_LE16(spi_API16);
AJ_WSL_SPI_RegisterWrite(AJ_WSL_SPI_REG_INTR_ENABLE, spi_API16);
// wait until the write has been processed.
spi_API16 = 0;
while (!(spi_API16 & 1)) {
AJ_WSL_SPI_RegisterRead(AJ_WSL_SPI_REG_SPI_STATUS, (uint8_t*)&spi_API16);
spi_API16 = LE16_TO_CPU(spi_API16);
uint16_t space = 0;
AJ_WSL_SPI_RegisterRead(AJ_WSL_SPI_REG_WRBUF_SPC_AVA, (uint8_t*)&space);
}
// clear the read and write interrupt cause register
spi_API = (1 << 9) | (1 << 8);
spi_API = CPU_TO_LE16(spi_API);
AJ_WSL_SPI_RegisterWrite(AJ_WSL_SPI_REG_INTR_CAUSE, spi_API);
{
spi_API16 = 0x1;
spi_API16 = CPU_TO_LE16(spi_API16);
AJ_WSL_SPI_RegisterWrite(AJ_WSL_SPI_REG_HOST_CTRL_BYTE_SIZE, spi_API16);
// waiting seems to allow the following write to succeed and thus enable interrupts.
// we need something more deterministic.
AJ_Sleep(1000);
spi_API16 = 0x00FF;
spi_API = CPU_TO_LE16(spi_API);
AJ_WSL_SPI_HostControlRegisterWrite(AJ_WSL_SPI_CPU_INT_STATUS, FALSE, 1, (uint8_t*)&spi_API16);
}
}
void uart_config(uint8_t port,usb_cdc_line_coding_t *cfg)
{
UNUSED(port);
/* Configure USART for unit test output */
usart_get_config_defaults(&usart_conf);
switch (cfg->bCharFormat) {
case CDC_STOP_BITS_2:
usart_conf.stopbits = USART_STOPBITS_2;
break;
case CDC_STOP_BITS_1_5:
usart_conf.stopbits = USART_STOPBITS_1;
break;
case CDC_STOP_BITS_1:
default:
/* Default stop bit = 1 stop bit */
usart_conf.stopbits = USART_STOPBITS_1;
break;
}
switch (cfg->bParityType) {
case CDC_PAR_EVEN:
usart_conf.parity = USART_PARITY_EVEN;
break;
case CDC_PAR_ODD:
usart_conf.parity = USART_PARITY_ODD;
break;
case CDC_PAR_MARK:
usart_conf.parity = USART_PARITY_NONE;
break;
case CDC_PAR_SPACE:
usart_conf.parity = USART_PARITY_NONE;
break;
case CDC_PAR_NONE:
default:
usart_conf.parity = USART_PARITY_NONE;
break;
}
switch(cfg->bDataBits) {
case 5:
usart_conf.character_size = USART_CHARACTER_SIZE_5BIT;
break;
case 6:
usart_conf.character_size = USART_CHARACTER_SIZE_6BIT;
break;
case 7:
usart_conf.character_size = USART_CHARACTER_SIZE_7BIT;
break;
case 8:
default:
usart_conf.character_size = USART_CHARACTER_SIZE_8BIT;
break;
}
/* Options for USART. */
usart_conf.baudrate = LE32_TO_CPU(cfg->dwDTERate);
usart_conf.mux_setting = CONF_USART_MUX_SETTING;
usart_conf.pinmux_pad0 = CONF_USART_PINMUX_PAD0;
usart_conf.pinmux_pad1 = CONF_USART_PINMUX_PAD1;
usart_conf.pinmux_pad2 = CONF_USART_PINMUX_PAD2;
usart_conf.pinmux_pad3 = CONF_USART_PINMUX_PAD3;
usart_disable(&usart_module_edbg);
usart_init(&usart_module_edbg, CONF_USART_BASE, &usart_conf);
usart_enable(&usart_module_edbg);
/* Enable interrupts */
usart_register_callback(&usart_module_edbg, usart_tx_callback,
USART_CALLBACK_BUFFER_TRANSMITTED);
usart_enable_callback(&usart_module_edbg, USART_CALLBACK_BUFFER_TRANSMITTED);
usart_register_callback(&usart_module_edbg, usart_rx_callback,
USART_CALLBACK_BUFFER_RECEIVED);
usart_enable_callback(&usart_module_edbg, USART_CALLBACK_BUFFER_RECEIVED);
usart_read_buffer_job(&usart_module_edbg, &rx_data, 1);
}
/* This is the test introduced for SHA-3, which checks for 33-bit overflow:
"abcdefghbcdefghicdefghijdefghijkefghijklfghijklmghijklmnhijklmno"
16777216 times.
*/
static uint32_t expected[] = {
CPU_TO_BE32(0x50e72a0e), CPU_TO_BE32(0x26442fe2),
CPU_TO_BE32(0x552dc393), CPU_TO_BE32(0x8ac58658),
CPU_TO_BE32(0x228c0cbf), CPU_TO_BE32(0xb1d2ca87),
CPU_TO_BE32(0x2ae43526), CPU_TO_BE32(0x6fcd055e)
};
/* Produced by actually running the code on x86. */
static const struct sha256_ctx after_16M_by_64 = {
#ifdef CCAN_CRYPTO_SHA256_USE_OPENSSL
{ { LE32_TO_CPU(0x515e3215), LE32_TO_CPU(0x592f4ae0),
LE32_TO_CPU(0xd407a8fc), LE32_TO_CPU(0x1fad409b),
LE32_TO_CPU(0x51fa46cc), LE32_TO_CPU(0xea528ae5),
LE32_TO_CPU(0x5fa58ebb), LE32_TO_CPU(0x8be97931) },
0x0, 0x2,
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
0x0, 0x20 }
#else
{ LE32_TO_CPU(0x515e3215), LE32_TO_CPU(0x592f4ae0),
LE32_TO_CPU(0xd407a8fc), LE32_TO_CPU(0x1fad409b),
LE32_TO_CPU(0x51fa46cc), LE32_TO_CPU(0xea528ae5),
LE32_TO_CPU(0x5fa58ebb), LE32_TO_CPU(0x8be97931) },
1073741824,
{ .u32 = { 0x64636261, 0x68676665, 0x65646362, 0x69686766,
0x66656463, 0x6a696867, 0x67666564, 0x6b6a6968 } }
#endif
