/**
* @brief Set LPTIMx registers to their reset values.
* @param LPTIMx LP Timer instance
* @retval An ErrorStatus enumeration value:
* - SUCCESS: LPTIMx registers are de-initialized
* - ERROR: invalid LPTIMx instance
*/
ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef* LPTIMx)
{
ErrorStatus result = SUCCESS;
/* Check the parameters */
assert_param(IS_LPTIM_INSTANCE(LPTIMx));
if (LPTIMx == LPTIM1)
{
LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_LPTIM1);
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_LPTIM1);
}
#if defined(LPTIM2)
else if (LPTIMx == LPTIM2)
{
LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_LPTIM2);
LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_LPTIM2);
}
#endif
else
{
result = ERROR;
}
return result;
}
/**
* @brief De-initialize the SWPMI peripheral registers to their default reset values.
* @param SWPMIx SWPMI Instance
* @retval An ErrorStatus enumeration value
* - SUCCESS: SWPMI registers are de-initialized
* - ERROR: Not applicable
*/
ErrorStatus LL_SWPMI_DeInit(SWPMI_TypeDef *SWPMIx)
{
/* Check the parameter */
assert_param(IS_SWPMI_INSTANCE(SWPMIx));
LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_SWPMI1);
LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_SWPMI1);
return SUCCESS;
}
/**
* @brief De-initialize registers of all ADC instances belonging to
* the same ADC common instance to their default reset values.
* @note This function is performing a hard reset, using high level
* clock source RCC ADC reset.
* @param ADCxy_COMMON ADC common instance
* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
* @retval An ErrorStatus enumeration value:
* - SUCCESS: ADC common registers are de-initialized
* - ERROR: not applicable
*/
ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON)
{
/* Check the parameters */
assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
/* Force reset of ADC clock (core clock) */
LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_ADC1);
/* Release reset of ADC clock (core clock) */
LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_ADC1);
return SUCCESS;
}
/**
* @brief De-initialize the I2C registers to their default reset values.
* @param I2Cx I2C Instance.
* @retval An ErrorStatus enumeration value:
* - SUCCESS: I2C registers are de-initialized
* - ERROR: I2C registers are not de-initialized
*/
uint32_t LL_I2C_DeInit(I2C_TypeDef *I2Cx)
{
ErrorStatus status = SUCCESS;
/* Check the I2C Instance I2Cx */
assert_param(IS_I2C_ALL_INSTANCE(I2Cx));
if (I2Cx == I2C1)
{
/* Force reset of I2C clock */
LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C1);
/* Release reset of I2C clock */
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C1);
}
#if defined(I2C2)
else if (I2Cx == I2C2)
{
/* Force reset of I2C clock */
LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C2);
/* Release reset of I2C clock */
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C2);
}
#endif
else if (I2Cx == I2C3)
{
/* Force reset of I2C clock */
LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C3);
/* Release reset of I2C clock */
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C3);
}
#if defined(I2C4)
else if (I2Cx == I2C4)
{
/* Force reset of I2C clock */
LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_I2C4);
/* Release reset of I2C clock */
LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_I2C4);
}
#endif
else
{
status = ERROR;
}
return status;
}
/**
* @brief De-initialize LPUART registers (Registers restored to their default values).
* @param LPUARTx LPUART Instance
* @retval An ErrorStatus enumeration value:
* - SUCCESS: LPUART registers are de-initialized
* - ERROR: not applicable
*/
ErrorStatus LL_LPUART_DeInit(USART_TypeDef *LPUARTx)
{
ErrorStatus status = SUCCESS;
/* Check the parameters */
assert_param(IS_LPUART_INSTANCE(LPUARTx));
if (LPUARTx == LPUART1)
{
/* Force reset of LPUART peripheral */
LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_LPUART1);
/* Release reset of LPUART peripheral */
LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_LPUART1);
}
else
{
status = ERROR;
}
return (status);
}