//------------------------------------------------------------------------------
/// This is the code that gets called on processor reset. To initialize the
/// device. And call the main() routine.
//------------------------------------------------------------------------------
void ResetException(void)
{
unsigned int *pSrc, *pDest;
LowLevelInit();
// Initialize data
pSrc = &_efixed;
pDest = &_srelocate;
if (pSrc != pDest) {
for(; pDest < &_erelocate;) {
*pDest++ = *pSrc++;
}
}
// Zero fill bss
for(pDest = &_szero; pDest < &_ezero;) {
*pDest++ = 0;
}
pSrc = (unsigned int *)&_sfixed;
AT91C_BASE_NVIC->NVIC_VTOFFR = ((unsigned int)(pSrc)) | (0x0 << 7);
main();
}
//-----------------------------------------------------------------------------
//
// InitDevice
//! \brief Description: This function will init the device
//
// Entry:
//! \param
//! This routine does not have any input parameters.
///
// Exit:
//! \return NONE ( Does not return any values )
//-----------------------------------------------------------------------------
void InitDevice( void ){
//Stop watchdog
LowLevelInit();
//Setup LEDs
InitLEDs();
//Configure clocks at 16MHz
ConfigureClocks();
//Initialize the button interupt for forcing last/saved roast curve
InitBtnInterrupt();
//Initialize PWM for fan
InitPWM();
//Initialize thermocouple for sampleing temp
InitTherm();
//Set ACLK to use internal VLO (12 kHz clock)
BCSCTL3 |= LFXT1S_2;
//Set TimerA to use auxiliary clock in UP mode
TACTL = TASSEL_1 | MC_1;
//Enable the interrupt for TACCR0 match
TACCTL0 = CCIE;
// Set TACCR0 which also starts the timer. At 12 kHz, counting to 12000
// should output an LED change every 1 second. Try this out and see how
// inaccurate the VLO can be
TACCR0 = 3000;
} //InitDevice
//------------------------------------------------------------------------------
/// This is the code that gets called on processor reset. To initialize the
/// device.
//------------------------------------------------------------------------------
int __low_level_init( void )
{
unsigned int * src = __section_begin(".vectors");
LowLevelInit();
AT91C_BASE_NVIC->NVIC_VTOFFR = ((unsigned int)(src)) | (0x0 << 7);
return 1; // if return 0, the data sections will not be initialized.
}
//------------------------------------------------------------------------------
/// This is the code that gets called on processor reset. To initialize the
/// device.
//------------------------------------------------------------------------------
void resetHandler( void )
{
unsigned int *pSrc = (unsigned int *)&Image$$Vector_region$$Base;
// Low level Initialize
LowLevelInit();
AT91C_BASE_NVIC->NVIC_VTOFFR = ((unsigned int)(pSrc)) | (0x0 << 7);
// Enter C library entry point
__main();
}
//------------------------------------------------------------------------------
/// This is the code that gets called on processor reset. To initialize the
/// device.
//------------------------------------------------------------------------------
void resetHandler( void )
{
unsigned int *pSrc = (unsigned int *)&Image$$Vector_region$$Base;
// Low level Initialize
LowLevelInit();
SCB->VTOR = ((uint32_t)(pSrc)) & SCB_VTOR_MASK;
// Enter C library entry point
__main();
/* Infinite loop */
while(1);
}
/**
* \brief This is the code that gets called on processor reset.
* To initialize the device, and call the main() routine.
*/
void Reset_Handler( void )
{
uint32_t *pSrc, *pDest ;
/* Low level Initialize */
LowLevelInit() ;
/* Initialize the relocate segment */
pSrc = &_etext ;
pDest = &_srelocate ;
if ( pSrc != pDest )
{
for ( ; pDest < &_erelocate ; )
{
*pDest++ = *pSrc++ ;
}
}
/* Clear the zero segment */
for ( pDest = &_szero ; pDest < &_ezero ; )
{
*pDest++ = 0;
}
/* Set the vector table base address */
pSrc = (uint32_t *)&_sfixed;
SCB->VTOR = ( (uint32_t)pSrc & SCB_VTOR_TBLOFF_Msk ) ;
if ( ((uint32_t)pSrc >= IRAM_ADDR) && ((uint32_t)pSrc < IRAM_ADDR+IRAM_SIZE) )
{
SCB->VTOR |= 1 << SCB_VTOR_TBLBASE_Pos ;
}
/* Initialize the C library */
__libc_init_array() ;
/* Branch to main function */
main() ;
/* Infinite loop */
while ( 1 ) ;
}
//------------------------------------------------------------------------------
/// This is the code that gets called on processor reset. To initialize the
/// device.
//------------------------------------------------------------------------------
void __low_level_init( void )
{
LowLevelInit();
// Setup the Vector table
// Copy the vector table to SRAM (0x20000000)
{
/*
unsigned int * src = __section_begin(".intvec");
unsigned int * src_end = __section_end(".intvec");
unsigned int * des = &__ICFEDIT_region_RAM_VECT_start__;
if (src != des) {
for (; src < src_end; ) {
*des ++ = *src ++;
}
}
*/
// Table base is in RAM
AT91C_BASE_NVIC->NVIC_VTOFFR |= AT91C_NVIC_TBLBASE_RAM;
}
}
//------------------------------------------------------------------------------
/// This is the code that gets called on processor reset. To initialize the
/// device. And call the main() routine.
//------------------------------------------------------------------------------
void ResetException(void)
{
unsigned int *pSrc, *pDest;
LowLevelInit();
#if defined(psram)
pDest = &_vect_start;
pSrc = &_svectorrelocate;
for(; pSrc < &_evectorrelocate;) {
*pDest++ = *pSrc++;
}
#endif
// Initialize data
pSrc = &_efixed;
pDest = &_srelocate;
if (pSrc != pDest) {
for(; pDest < &_erelocate;) {
*pDest++ = *pSrc++;
}
}
// Zero fill bss
for(pDest = &_szero; pDest < &_ezero;) {
*pDest++ = 0;
}
#if defined(psram)
pSrc = (unsigned int *)&_vect_start;
#else
pSrc = (unsigned int *)&_sfixed;
#endif
AT91C_BASE_NVIC->NVIC_VTOFFR = ((unsigned int)(pSrc)) | (0x0 << 7);
main();
}
//------------------------------------------------------------------------------
/// This is the code that gets called on processor reset. To initialize the
/// device. And call the main() routine.
//------------------------------------------------------------------------------
void ResetException(void)
{
unsigned int *pSrc, *pDest;
// Initialize data
// Zero fill bss
if (isInitialized == 0) {
pSrc = &_sidata;
for(pDest = &_sdata; pDest < &_edata;) {
*(pDest ++) = *(pSrc ++);
}
for (pDest = &_szero; pDest < &_ezero;) {
*(pDest ++) = 0;
}
isInitialized = 1;
}
LowLevelInit();
main(1, mailbox);
}
//------------------------------------------------------------------------------
/// Applet code for initializing the external RAM.
//------------------------------------------------------------------------------
int main(int argc, char **argv)
{
struct _Mailbox *pMailbox = (struct _Mailbox *) argv;
unsigned int ramType = 0;
unsigned int bufferSize, bufferAddr, memoryOffset;
unsigned int bytesToWrite;
unsigned int tempBufferAddr;
unsigned int dataBusWidth = 0;
unsigned int ddrModel = 0;
LowLevelInit();
TRACE_CONFIGURE_ISP(DBGU_STANDARD, 115200, BOARD_MCK);
/* *AT91C_PMC_PCER = AT91C_ID_PIOA;
*AT91C_PIOA_PDR = (1<<31);
*AT91C_PIOA_OER = (1<<31);
*AT91C_PIOA_BSR = (1<<31);
*AT91C_PIOA_PER = (1<<0);
*AT91C_PIOA_OER = (1<<0);
*AT91C_PMC_PCKR = (1<<8); // select master clock
*AT91C_PMC_SCER = (1<<8); // ENABLE PCK0*/
TRACE_INFO("Statup: PMC_MCKR %x MCK = %d command = %d\n\r", *AT91C_PMC_MCKR, BOARD_MCK, pMailbox->command);
// ----------------------------------------------------------
// INIT:
// ----------------------------------------------------------
if (pMailbox->command == APPLET_CMD_INIT) {
// Initialize PMC
// BOARD_RemapRam();
// Enable User Reset
AT91C_BASE_RSTC->RSTC_RMR |= AT91C_RSTC_URSTEN | (0xA5<<24);
ramType = pMailbox->argument.inputInit.ramType;
dataBusWidth = pMailbox->argument.inputInit.dataBusWidth;
ddrModel = pMailbox->argument.inputInit.ddrModel;
//#if (DYN_TRACES == 1)
// traceLevel = pMailbox->argument.inputInit.traceLevel;
//#endif
TRACE_INFO("-- EXTRAM ISP Applet %s --\n\r", SAM_BA_APPLETS_VERSION);
TRACE_INFO("-- %s\n\r", BOARD_NAME);
TRACE_INFO("-- Compiled: %s %s %s --\n\r", __DATE__, __TIME__, __GIT__);
TRACE_INFO("INIT command:\n\r");
TRACE_INFO("\tCommunication link type : %d\n\r", pMailbox->argument.inputInit.comType);
TRACE_INFO("\tData bus width : %d bits\n\r", dataBusWidth);
if (ramType == TYPE_SDRAM) {
TRACE_INFO("\tExternal RAM type : %s\n\r", "SDRAM");
}
else {
if (ramType == TYPE_DDRAM) {
TRACE_INFO("\tExternal RAM type : %s\n\r", "DDRAM");
}
else {
TRACE_INFO("\tExternal RAM type : %s\n\r", "PSRAM");
}
}
#if defined(at91cap9) || defined(at91sam9m10) || defined(at91sam9g45)
TRACE_INFO("\tInit EBI Vdd : %s\n\r", (pMailbox->argument.inputInit.VddMemSel)?"3.3V":"1.8V");
BOARD_ConfigureVddMemSel(pMailbox->argument.inputInit.VddMemSel);
#endif //defined(at91cap9)
if (pMailbox->argument.inputInit.ramType == TYPE_SDRAM) {
// Configure SDRAM controller
TRACE_INFO("\tInit SDRAM...\n\r");
#if defined(PINS_SDRAM)
BOARD_ConfigureSdram(dataBusWidth);
#endif
}
else if (pMailbox->argument.inputInit.ramType == TYPE_PSRAM) {
TRACE_INFO("\tInit PSRAM...\n\r");
#if defined(at91sam3u4)
BOARD_ConfigurePsram();
#endif
}
else {
// Configure DDRAM controller
#if defined(at91cap9dk) || defined(at91sam9m10) || defined(at91sam9g45)
TRACE_INFO("\tInit DDRAM ... (model : %d)\n\r", ddrModel);
BOARD_ConfigureVddMemSel(VDDMEMSEL_1V8);
BOARD_ConfigureDdram(0, dataBusWidth);
// ddramc_hw_init();
#endif
}
TRACE_INFO("\tInit successful.\n\r");
}
// ----------------------------------------------------------
// LIST_BAD_BLOCK: (Check DDR)
// ----------------------------------------------------------
else if (pMailbox->command == APPLET_CMD_LIST_BAD_BLOCKS)
{
// Test external RAM access
if (ExtRAM_TestOk()) {
pMailbox->status = APPLET_SUCCESS;
}
else {
pMailbox->status = APPLET_FAIL;
}
pMailbox->argument.outputInit.bufferAddress = ((unsigned int) &end);
pMailbox->argument.outputInit.bufferSize = 0;
pMailbox->argument.outputInit.memorySize = EXTRAM_SIZE;
}
// ----------------------------------------------------------
// WRITE:
// ----------------------------------------------------------
else if (pMailbox->command == APPLET_CMD_WRITE)
{
memoryOffset = pMailbox->argument.inputWrite.memoryOffset;
bufferAddr = pMailbox->argument.inputWrite.bufferAddr;
bytesToWrite = pMailbox->argument.inputWrite.bufferSize;
tempBufferAddr = bufferAddr+memoryOffset;
TRACE_INFO("WRITE arguments : offset 0x%x, run 0x%x, of 0x%x Bytes\n\r",
memoryOffset, tempBufferAddr, bytesToWrite);
pMailbox->argument.outputWrite.bytesWritten = 0;
/*
* We must define the following
* - MACH_TYPE_xxx
* - Setup the kernel tagged list (http://www.arm.linux.org.uk/developer/booting.php#4)
* first 16KiB of RAM.
*
* we recommend to load at 32KiB into RAM
*/
//Fake the end of the applet because we will not be able to do anything after this step
if (bytesToWrite < EXTRAM_SIZE)
{
pMailbox->status = APPLET_SUCCESS;
}
else
{
pMailbox->status = APPLET_FAIL;
}
pMailbox->command = ~(pMailbox->command);
//Going to
((VFptr *)(EXTRAM_ADDR+memoryOffset))();
}
exit :
// Acknowledge the end of command
TRACE_INFO("\tEnd of applet (command : %x --- status : %x)\n\r", pMailbox->command, pMailbox->status);
// Notify the host application of the end of the command processing
pMailbox->command = ~(pMailbox->command);
return 0;
}
/**
* \brief Configure the PMC as EK setting
*/
static void EK_LowLevelInit (void)
{
LowLevelInit();
}
//------------------------------------------------------------------------------
/// Applet code for initializing the external RAM.
//------------------------------------------------------------------------------
int main(int argc, char **argv)
{
struct _Mailbox *pMailbox = (struct _Mailbox *) argv;
unsigned int ramType = 0;
unsigned int dataBusWidth = 0;
unsigned int ddrModel = 0;
TRACE_CONFIGURE_ISP(DBGU_STANDARD, 115200, BOARD_MCK);
// ----------------------------------------------------------
// INIT:
// ----------------------------------------------------------
if (pMailbox->command == APPLET_CMD_INIT) {
// Initialize PMC
LowLevelInit();
// Enable User Reset
AT91C_BASE_RSTC->RSTC_RMR |= AT91C_RSTC_URSTEN | (0xA5<<24);
ramType = pMailbox->argument.inputInit.ramType;
dataBusWidth = pMailbox->argument.inputInit.dataBusWidth;
ddrModel = pMailbox->argument.inputInit.ddrModel;
#if (DYN_TRACES == 1)
traceLevel = pMailbox->argument.inputInit.traceLevel;
#endif
TRACE_INFO("-- EXTRAM ISP Applet %s --\n\r", SAM_BA_APPLETS_VERSION);
TRACE_INFO("-- %s\n\r", BOARD_NAME);
TRACE_INFO("-- Compiled: %s %s --\n\r", __DATE__, __TIME__);
TRACE_INFO("INIT command:\n\r");
TRACE_INFO("\tCommunication link type : %d\n\r", pMailbox->argument.inputInit.comType);
TRACE_INFO("\tData bus width : %d bits\n\r", dataBusWidth);
if (ramType == TYPE_SDRAM) {
TRACE_INFO("\tExternal RAM type : %s\n\r", "SDRAM");
}
else {
if (ramType == TYPE_DDRAM) {
TRACE_INFO("\tExternal RAM type : %s\n\r", "DDRAM");
}
else {
TRACE_INFO("\tExternal RAM type : %s\n\r", "PSRAM");
}
}
#if defined(at91cap9) || defined(at91sam9m10) || defined(at91sam9g45)
TRACE_INFO("\tInit EBI Vdd : %s\n\r", (pMailbox->argument.inputInit.VddMemSel)?"3.3V":"1.8V");
BOARD_ConfigureVddMemSel(pMailbox->argument.inputInit.VddMemSel);
#endif //defined(at91cap9)
if (pMailbox->argument.inputInit.ramType == TYPE_SDRAM) {
// Configure SDRAM controller
TRACE_INFO("\tInit SDRAM...\n\r");
BOARD_ConfigureSdram(dataBusWidth);
}
else if (pMailbox->argument.inputInit.ramType == TYPE_PSRAM) {
TRACE_INFO("\tInit PSRAM...\n\r");
#if defined(at91sam3u4)
BOARD_ConfigurePsram();
#endif
}
else {
// Configure DDRAM controller
#if defined(at91cap9dk) || defined(at91sam9m10) || defined(at91sam9g45)
TRACE_INFO("\tInit DDRAM ... (model : %d)\n\r", ddrModel);
BOARD_ConfigureDdram(ddrModel, dataBusWidth);
#endif
}
// Test external RAM access
if (ExtRAM_TestOk()) {
pMailbox->status = APPLET_SUCCESS;
}
else {
pMailbox->status = APPLET_FAIL;
}
pMailbox->argument.outputInit.bufferAddress = ((unsigned int) &end);
pMailbox->argument.outputInit.bufferSize = 0;
pMailbox->argument.outputInit.memorySize = EXTRAM_SIZE;
TRACE_INFO("\tInit successful.\n\r");
}
// Acknowledge the end of command
TRACE_INFO("\tEnd of applet (command : %x --- status : %x)\n\r", pMailbox->command, pMailbox->status);
// Notify the host application of the end of the command processing
pMailbox->command = ~(pMailbox->command);
return 0;
}
