int GGI_m2164w_drawline(ggi_visual *vis, int x, int y, int x2, int y2)
{
struct m2164w_priv *priv = M2164W_PRIV(vis);
volatile uint8_t *mmioaddr = FBDEV_PRIV(vis)->mmioaddr;
int yadd = vis->w_frame_num * LIBGGI_VIRTY(vis);
uint32_t dwgctl;
if (yadd) {
y += yadd;
y2 += yadd;
}
dwgctl = OP_AUTOLINE_CLOSE | SOLID | SHFTZERO | BOP_COPY |
BLTMOD_BFCOL;
mga_gcupdate(mmioaddr, priv, LIBGGI_MODE(vis), LIBGGI_GC(vis),
LIBGGI_VIRTX(vis), yadd);
if (priv->dwgctl != dwgctl) {
mga_waitfifo(mmioaddr, 3);
mga_setdwgctl(mmioaddr, priv, dwgctl);
} else {
mga_waitfifo(mmioaddr, 2);
}
mga_out32(mmioaddr, (unsigned)RS16(x) | (RS16(y) << 16), XYSTRT);
mga_out32(mmioaddr, (unsigned)RS16(x2) | (RS16(y2) << 16),
XYEND | EXECUTE);
vis->accelactive = 1;
return 0;
}
int GGI_m2164w_fillscreen(struct ggi_visual *vis)
{
struct m2164w_priv *priv = M2164W_PRIV(vis);
volatile uint8_t *mmioaddr = FBDEV_PRIV(vis)->mmioaddr;
int virtx = LIBGGI_VIRTX(vis);
int virty = LIBGGI_VIRTY(vis);
int yadd = vis->w_frame_num * LIBGGI_VIRTY(vis);
mga_gcupdate(mmioaddr, priv, LIBGGI_MODE(vis),
LIBGGI_GC(vis), LIBGGI_VIRTX(vis), yadd);
if (priv->dwgctl != priv->drawboxcmd) {
mga_waitfifo(mmioaddr, 3);
mga_setdwgctl(mmioaddr, priv, priv->drawboxcmd);
} else {
mga_waitfifo(mmioaddr, 2);
}
mga_out32(mmioaddr, (unsigned)RS16(virtx) << 16, FXBNDRY);
mga_out32(mmioaddr, (unsigned)(RS16(yadd) << 16) | RS16(virty + yadd),
YDSTLEN | EXECUTE);
vis->accelactive = 1;
return 0;
}
int GGI_m2164w_drawbox(struct ggi_visual *vis, int x, int y, int w, int h)
{
if (w > 0 && h > 0) { /* 0 width is not OK! */
struct m2164w_priv *priv = M2164W_PRIV(vis);
volatile uint8_t *mmioaddr = FBDEV_PRIV(vis)->mmioaddr;
int yadd = vis->w_frame_num * LIBGGI_VIRTY(vis);
y += yadd;
mga_gcupdate(mmioaddr, priv, LIBGGI_MODE(vis), LIBGGI_GC(vis),
LIBGGI_VIRTX(vis), yadd);
if (priv->dwgctl != priv->drawboxcmd) {
mga_waitfifo(mmioaddr, 3);
mga_setdwgctl(mmioaddr, priv, priv->drawboxcmd);
} else {
mga_waitfifo(mmioaddr, 2);
}
mga_out32(mmioaddr, (unsigned)(RS16(x + w) << 16) | RS16(x),
FXBNDRY);
mga_out32(mmioaddr, (unsigned)(RS16(y) << 16) | RS16(h),
YDSTLEN | EXECUTE);
vis->accelactive = 1;
}
return 0;
}
static int do_cleanup(ggi_visual *vis)
{
ggi_fbdev_priv *fbdevpriv = FBDEV_PRIV(vis);
struct m2164w_priv *priv = NULL;
int i;
DPRINT_MISC("mga-2164w: Starting cleanup\n");
if (fbdevpriv != NULL) {
priv = M2164W_PRIV(vis);
}
/* We may be called more than once due to the LibGG cleanup stuff */
if (priv == NULL) return 0;
/* Restore OPMODE and terminate any pending DMA operations
Manual says we should write to byte 0 to terminate DMA sequence,
but it doesn't say whether a 8 bit access is required, or if any
access will do. We play it safe here... */
mga_out8(fbdevpriv->mmioaddr, priv->origopmode & 0xff, OPMODE);
mga_out16(fbdevpriv->mmioaddr, priv->origopmode, OPMODE);
mga_waitidle(fbdevpriv->mmioaddr);
munmap((void*)fbdevpriv->mmioaddr, fbdevpriv->orig_fix.mmio_len);
DPRINT_MISC("mga-2164w: Unmapped MMIO\n");
/* Free DB resource structures */
for (i = LIBGGI_APPLIST(vis)->num-1; i >= 0; i--) {
if (LIBGGI_APPBUFS(vis)[i]->resource) {
free(LIBGGI_APPBUFS(vis)[i]->resource);
LIBGGI_APPBUFS(vis)[i]->resource = NULL;
}
}
free(priv);
FBDEV_PRIV(vis)->accelpriv = NULL;
ggUnregisterCleanup((ggcleanup_func *)do_cleanup, vis);
return 0;
}
int GGI_m2164w_crossblit(ggi_visual *src, int sx, int sy, int w, int h,
ggi_visual *dst, int dx, int dy)
{
/* Software clip so we don't read/write unused data. */
LIBGGICLIP_COPYBOX(dst, sx, sy, w, h, dx, dy);
if (src->r_frame && src->r_frame->layout == dst->w_frame->layout) {
uint32_t srcformat
= src->r_frame->buffer.plb.pixelformat->stdformat;
PREPARE_FB(src);
switch (srcformat) {
case GGI_DB_STD_24a32p8r8g8b8:
case GGI_DB_STD_24a32p8b8g8r8:
dbblit_32bpp(src, sx, sy, w, h, dst, dx, dy, srcformat);
return 0;
}
}
return M2164W_PRIV(dst)->crossblit(src, sx, sy, w, h, dst, dx, dy);
}
static inline void
dbblit_32bpp(ggi_visual *src, int sx, int sy, int w, int h,
ggi_visual *dst, int dx, int dy, uint32_t srcfmt)
{
struct m2164w_priv *priv = M2164W_PRIV(dst);
volatile uint8_t *mmioaddr = FBDEV_PRIV(dst)->mmioaddr;
int yadd = dst->w_frame_num * LIBGGI_VIRTY(dst);
volatile uint32_t *dstptr;
uint32_t dwgctl, bltmod = BLTMOD_BU32RGB;
uint16_t opmode;
uint8_t *srcptr;
uint32_t *srcptr32;
int srcinc;
int maxpix;
dstptr = priv->dmaaddr;
srcinc = LIBGGI_FB_R_STRIDE(src);
srcptr = (uint8_t*) LIBGGI_CURWRITE(src) + sy*srcinc + sx*4;
srcinc -= w*4;
maxpix = priv->dma_len/4;
dy += yadd;
switch (srcfmt) {
#if 0 /* This case is the default. */
case GGI_DB_STD_24a32p8r8g8b8:
bltmod = BLTMOD_BU32RGB;
break;
#endif
case GGI_DB_STD_24a32p8b8g8r8:
bltmod = BLTMOD_BU32BGR;
break;
}
dwgctl = bltmod | BOP_COPY | SHFTZERO | OP_ILOAD | SGNZERO;
#ifdef GGI_BIG_ENDIAN
opmode = OPMODE_DMA_BLIT_WRITE | OPMODE_DMA_BE_32BPP;
#else
opmode = OPMODE_DMA_BLIT_WRITE | OPMODE_DMA_LE;
#endif
mga_gcupdate(mmioaddr, priv, LIBGGI_MODE(dst), LIBGGI_GC(dst),
LIBGGI_VIRTX(dst), yadd);
if (priv->curopmode != opmode) {
priv->curopmode = opmode;
mga_waitidle(mmioaddr);
mga_out16(mmioaddr, opmode, OPMODE);
}
if (priv->dwgctl != dwgctl) {
mga_waitfifo(mmioaddr, 6);
mga_setdwgctl(mmioaddr, priv, dwgctl);
} else {
mga_waitfifo(mmioaddr, 5);
}
mga_out32(mmioaddr, RS18(w-1), AR0);
mga_out32(mmioaddr, 0, AR3);
mga_out32(mmioaddr, 0, AR5);
mga_out32(mmioaddr, (unsigned)(RS16(dx + w - 1) << 16) | RS16(dx),
FXBNDRY);
mga_out32(mmioaddr, (unsigned)(RS16(dy) << 16) | RS16(h),
YDSTLEN | EXECUTE);
dst->accelactive = 1;
if (w > maxpix) {
while (h--) {
int tmpw = w;
while (tmpw) {
int tmpw2 = (tmpw > maxpix ? maxpix : tmpw);
tmpw -= tmpw2;
while (tmpw2--) {
srcptr32 = (uint32_t *)srcptr;
*(dstptr++) = *(srcptr32++);
srcptr = (uint8_t *)srcptr32;
}
dstptr = priv->dmaaddr;
}
srcptr += srcinc;
}
} else {
while (h--) {
int tmpw = w;
while (tmpw--) {
srcptr32 = (uint32_t *)srcptr;
*(dstptr++) = *(srcptr32++);
srcptr = (uint8_t *)srcptr32;
}
srcptr += srcinc;
dstptr = priv->dmaaddr;
}
}
}
