/*****************************************************************************
* FUNCTION
* mau_dump_status
* DESCRIPTION
* 1. Dump register in MAU related register.
* 2. Show MAU status
* PARAMETERS
* param1 : [IN] MTK_MAU_CONFIG* pMauConf
* MAU setting configuration.
* RETURNS
* None.
****************************************************************************/
void mau_dump_status(const int larb)
{
unsigned int larb_base;
unsigned int regval;
int i;
larb_clock_on(larb, "MAU");
larb_base = gLarbBaseAddr[larb];
//dump interrupt debug infomation
for(i=0; i<MAU_ENTRY_NR; i++)
{
regval = M4U_ReadReg32(larb_base, SMI_MAU_ENTR_GID(i));
if(regval!=0)
{
SMIMSG("larb(%d), entry(%d)=========>\n", larb, i);
SMIMSG("port mask = 0x%x\n", regval);
regval = M4U_ReadReg32(larb_base, SMI_MAU_ENTR_START(i));
SMIMSG("start_addr=0x%x, read_en=%d, write_en=%d\n",
F_MAU_START_ADDR_VAL(regval),
F_MAU_START_IS_RD(regval), F_MAU_START_IS_WR(regval));
regval = M4U_ReadReg32(larb_base, SMI_MAU_ENTR_END(i));
SMIMSG("end_addr=0x%x, virtual=%d\n", F_MAU_END_ADDR_VAL(regval),
F_MAU_END_IS_VIR(regval));
}
else
{
SMIMSG("larb(%d), entry(%d) is free\n", larb, i);
}
//dump interrupt debug infomation
regval = M4U_ReadReg32(larb_base, SMI_MAU_ENTR_STAT(i));
if(F_MAU_STAT_ASSERT(regval))
{
//violation happens in this entry
int port = F_MAU_STAT_ID(regval);
SMIMSG("[MAU] larb=%d, entry=%d, port=%d\n",larb,i,port);
SMIMSG("violation by %s\n",smi_port_name[port]);
}
else
{
SMIMSG("no violation of entry %d\n", i);
}
#if 0
//clear interrupt status
regval = M4U_ReadReg32(larb_base, SMI_MAU_ENTR_STAT(i));
M4U_WriteReg32(larb_base, SMI_MAU_ENTR_STAT(i), regval);
#endif
}
larb_clock_off(larb, "MAU");
}
int larb_reg_restore(int larb)
{
unsigned int regval,regval1,regval2;
unsigned int larb_base = gLarbBaseAddr[larb];
/*
unsigned int* pReg = pLarbRegBackUp[larb];
int i;
//warning: larb_con is controlled by set/clr
regval = *(pReg++);
M4U_WriteReg32(larb_base, SMI_LARB_CON_CLR, ~(regval));
M4U_WriteReg32(larb_base, SMI_LARB_CON_SET, (regval));
M4U_WriteReg32(larb_base, SMI_SHARE_EN, *(pReg++) );
M4U_WriteReg32(larb_base, SMI_ROUTE_SEL, *(pReg++) );
for(i=0; i<3; i++)
{
M4U_WriteReg32(larb_base, SMI_MAU_ENTR_START(i), *(pReg++));
M4U_WriteReg32(larb_base, SMI_MAU_ENTR_END(i), *(pReg++));
M4U_WriteReg32(larb_base, SMI_MAU_ENTR_GID(i), *(pReg++));
}
*/
//Clock manager enable LARB clock before call back restore already, it will be disabled after restore call back returns
//Got to enable OSTD before engine starts
regval = M4U_ReadReg32(larb_base , SMI_LARB_STAT);
regval1 = M4U_ReadReg32(larb_base , SMI_LARB_MON_BUS_REQ0);
regval2 = M4U_ReadReg32(larb_base , SMI_LARB_MON_BUS_REQ1);
if(0 == regval)
{
M4U_WriteReg32(larb_base , SMI_LARB_OSTD_CTRL_EN , 0xffffffff);
}
else
{
SMIMSG("Larb%d is busy : 0x%x , port:0x%x,0x%x ,fail to set OSTD\n" , larb , regval , regval1 , regval2);
smi_dumpDebugMsg();
SMIERR("DISP_MDP LARB%d OSTD cannot be set:0x%x,port:0x%x,0x%x\n" , larb , regval , regval1 , regval2);
}
if(0 == g_bInited)
{
initSetting();
g_bInited = 1;
SMIMSG("SMI init\n");
}
return 0;
}
/*****************************************************************************
* FUNCTION
* mau_isr
* DESCRIPTION
* 1. Print MAU status, such as port ID.
* 2. Clear interrupt status.
* PARAMETERS
* param1 : [IN] int irq
* irq number.
* param2 : [IN] void *dev_id
* No use in this function.
* RETURNS
* Type: irqreturn_t. IRQ_HANDLED mean success.
****************************************************************************/
static irqreturn_t mau_isr(int irq, void *dev_id)
{
int larb,i;
unsigned int larb_base;
unsigned int regval;
switch(irq)
{
case MT_SMI_LARB0_IRQ_ID:
larb = 0;
break;
default :
larb=0;
SMIERR("unkown irq(%d)\n",irq);
}
larb_clock_on(larb, "MAU");
larb_base = gLarbBaseAddr[larb];
//dump interrupt debug infomation
for(i=0; i<MAU_ENTRY_NR; i++)
{
regval = M4U_ReadReg32(larb_base, SMI_MAU_ENTR_STAT(i));
if(F_MAU_STAT_ASSERT(regval))
{
//violation happens in this entry
int port = F_MAU_STAT_ID(regval);
SMIMSG("[MAU] larb=%d, entry=%d, port=%d\n",larb,i,port);
regval = M4U_ReadReg32(larb_base, SMI_MAU_ENTR_START(i));
SMIMSG("start_addr=0x%x, read_en=%d, write_en=%d\n", F_MAU_START_ADDR_VAL(regval),
F_MAU_START_IS_RD(regval), F_MAU_START_IS_WR(regval));
regval = M4U_ReadReg32(larb_base, SMI_MAU_ENTR_END(i));
SMIMSG("end_addr=0x%x, virtual=%d\n", F_MAU_END_ADDR_VAL(regval),
F_MAU_END_IS_VIR(regval));
smi_aee_print("violation by %s\n",smi_port_name[port]);
}
//clear interrupt status
regval = M4U_ReadReg32(larb_base, SMI_MAU_ENTR_STAT(i));
M4U_WriteReg32(larb_base, SMI_MAU_ENTR_STAT(i), regval);
}
larb_clock_off(larb, "MAU");
return IRQ_HANDLED;
}
/*****************************************************************************
* FUNCTION
* larb_reg_backup
* DESCRIPTION
* Backup register for system suspend.
* PARAMETERS
* param1 : [IN] const int larb
* larb index.
* RETURNS
* None.
****************************************************************************/
static void larb_reg_backup(const int larb)
{
unsigned int* pReg = pLarbRegBackUp[larb];
int i;
unsigned int larb_base = gLarbBaseAddr[larb];
//SMI registers
for(i=0; i<2; i++)
*(pReg++) = COM_ReadReg32(REG_SMI_SECUR_CON(i));
*(pReg++) = M4U_ReadReg32(larb_base, SMI_LARB_CON);
for(i=0; i<MAU_ENTRY_NR; i++)
{
*(pReg++) = M4U_ReadReg32(larb_base, SMI_MAU_ENTR_START(i));
*(pReg++) = M4U_ReadReg32(larb_base, SMI_MAU_ENTR_END(i));
*(pReg++) = M4U_ReadReg32(larb_base, SMI_MAU_ENTR_GID(i));
}
}
// Check if specified MMSYS LARB is busy
// Return value:
// 1: MMSYS larb is busy
// 0: Bus is not busy
int is_smi_larb_busy(unsigned int u4Index){
unsigned int reg_value_0= 0;
unsigned int reg_value_1= 0;
unsigned int u4Base;
if(u4Index <0 || u4Index > 2){
SMIMSG("Doesn't support reg dump for Larb%d\n", u4Index);
return 0;
}
u4Base = gLarbBaseAddr[u4Index];
// 1. 0x0 == 1
reg_value_0 = M4U_ReadReg32(u4Base, 0x0);
if( 0x0!=1 ){
return 0;
}
// 2. (0x450 | 0x454) == 1
reg_value_0 = M4U_ReadReg32(u4Base, 0x450);
reg_value_1 = M4U_ReadReg32(u4Base, 0x454);
if( (reg_value_0 | reg_value_1) != 1){
return 0;
}
// 3. 0x600 == 0xaaaa
reg_value_0 = M4U_ReadReg32(u4Base, 0x600);
if( reg_value_0 != 0xaaaa){
return 0;
}
// 4. 0x604 == 0x2a8
reg_value_0 = M4U_ReadReg32(u4Base, 0x604);
if( reg_value_0 != 0x2a8){
return 0;
}
// 5. 0x610 == 0x3e0
reg_value_0 = M4U_ReadReg32(u4Base, 0x610);
if( reg_value_0 != 0x3e0){
return 0;
}
// 6. 0x614 == 0x3e0
reg_value_0 = M4U_ReadReg32(u4Base, 0x614);
if( reg_value_0 != 0x3e0){
return 0;
}
return 1;
}
/*****************************************************************************
* FUNCTION
* mau_start_monitor
* DESCRIPTION
* Configure register to set MAU assert
* a) Assert range
* b) Write and/or read transaction
* c) Physical or virtual address
* d) port mask
* PARAMETERS
* param1 : [IN] const int larb
* larb index.
* param2 : [IN] const int entry
* Index of MAU in assigned larb.
* param3 : [IN] const int rd
* 0 mean no check read transaction, and others mean check read transaction.
* param4 : [IN] const int wr
* 0 mean no check write transaction, and others mean check write transaction.
* param5 : [IN] const int vir
* 0 mean physical address, and others mean virtual address.
* param6 : [IN] const int wr
* 0 mean no check write transaction, and others mean check write transaction.
* param7 : [IN] const unsigned int start
* assert start address. (word align)
* param8 : [IN] const unsigned int end
* assert end address. (word align)
* param9 : [IN] const unsigned int port_msk
* port mask (bitwise)
* RETURNS
* None.
****************************************************************************/
static void mau_start_monitor(const int larb, const int entry, const int rd, const int wr, const int vir,
const unsigned int start, const unsigned int end, const unsigned int port_msk)
{
unsigned int regval;
unsigned int larb_base = gLarbBaseAddr[larb];
//mau entry i start address
regval = F_MAU_START_WR(wr)|F_MAU_START_RD(rd)|F_MAU_START_ADD(start);
M4U_WriteReg32(larb_base, SMI_MAU_ENTR_START(entry), regval);
regval = F_MAU_END_VIR(vir)|F_MAU_END_ADD(end);
M4U_WriteReg32(larb_base, SMI_MAU_ENTR_END(entry), regval);
//start monitor
regval = M4U_ReadReg32(larb_base, SMI_MAU_ENTR_GID(entry));
M4U_WriteReg32(larb_base, SMI_MAU_ENTR_GID(entry), regval|port_msk);
}
void smi_dumpDebugMsg(void)
{
unsigned int u4Index;
unsigned int u4Base;
unsigned int u4Offset;
//SMI COMMON dump
SMIMSG("===SMI common reg dump===\n");
u4Base = SMI_COMMON_EXT_BASE;
u4Offset = 0x400;
SMIMSG("+0x%x=0x%x \n" , u4Offset , M4U_ReadReg32(u4Base , u4Offset));
u4Offset = 0x404;
SMIMSG("+0x%x=0x%x \n" , u4Offset , M4U_ReadReg32(u4Base , u4Offset));
u4Offset = 0x234;
SMIMSG("+0x%x=0x%x \n" , u4Offset , M4U_ReadReg32(u4Base , u4Offset));
u4Offset = 0x200;
SMIMSG("+0x%x=0x%x \n" , u4Offset , M4U_ReadReg32(u4Base , u4Offset));
u4Offset = 0x204;
SMIMSG("+0x%x=0x%x \n" , u4Offset , M4U_ReadReg32(u4Base , u4Offset));
u4Offset = 0x208;
SMIMSG("+0x%x=0x%x \n" , u4Offset , M4U_ReadReg32(u4Base , u4Offset));
u4Offset = 0x20C;
SMIMSG("+0x%x=0x%x \n" , u4Offset , M4U_ReadReg32(u4Base , u4Offset));
u4Offset = 0x210;
SMIMSG("+0x%x=0x%x \n" , u4Offset , M4U_ReadReg32(u4Base , u4Offset));
u4Offset = 0x230;
SMIMSG("+0x%x=0x%x \n" , u4Offset , M4U_ReadReg32(u4Base , u4Offset));
//SMI LARB dump
for( u4Index=0 ; u4Index < SMI_LARB_NR ; u4Index++)
{
if(0 == u4Index)
{
// if((0 == clock_is_on(MT_CG_DISP0_SMI_LARB0)) || (0 == clock_is_on(MT_CG_DISP0_SMI_COMMON)))
if(0x3 & M4U_ReadReg32(0xF4000000 , 0x100))
{
SMIMSG("===SMI%d is off===\n" , u4Index);
continue;
}
}
else if(1 == u4Index)
{
// if(0 == clock_is_on(MT_CG_VDEC1_LARB))
if(0x1 & M4U_ReadReg32(0xF6000000 , 0x4))
{
SMIMSG("===SMI%d is off===\n" , u4Index);
continue;
}
}
else if(2 == u4Index)
{
// if(0 == clock_is_on(MT_CG_IMAGE_LARB2_SMI))
if(0x1 & M4U_ReadReg32(0xF5000000 , 0))
{
SMIMSG("===SMI%d is off===\n" , u4Index);
continue;
}
}
else
{
continue;
}
SMIMSG("===SMI%d reg dump===\n" , u4Index);
u4Base = gLarbBaseAddr[u4Index];
u4Offset = 0;
SMIMSG("+0x%x=0x%x \n" , u4Offset , M4U_ReadReg32(u4Base , u4Offset));
u4Offset = 0x10;
SMIMSG("+0x%x=0x%x \n" , u4Offset , M4U_ReadReg32(u4Base , u4Offset));
u4Offset = 0x450;
SMIMSG("+0x%x=0x%x \n" , u4Offset , M4U_ReadReg32(u4Base , u4Offset));
u4Offset = 0x454;
SMIMSG("+0x%x=0x%x \n" , u4Offset , M4U_ReadReg32(u4Base , u4Offset));
u4Offset = 0x600;
SMIMSG("+0x%x=0x%x \n" , u4Offset , M4U_ReadReg32(u4Base , u4Offset));
u4Offset = 0x604;
SMIMSG("+0x%x=0x%x \n" , u4Offset , M4U_ReadReg32(u4Base , u4Offset));
u4Offset = 0x610;
SMIMSG("+0x%x=0x%x \n" , u4Offset , M4U_ReadReg32(u4Base , u4Offset));
u4Offset = 0x614;
SMIMSG("+0x%x=0x%x \n" , u4Offset , M4U_ReadReg32(u4Base , u4Offset));
for(u4Offset = 0x200; u4Offset < 0x244 ; u4Offset += 4)
{
SMIMSG("+0x%x=0x%x \n" , u4Offset , M4U_ReadReg32(u4Base , u4Offset));
}
}
}
void smi_dumpLarbDebugMsg(unsigned int u4Index){
unsigned int u4Base;
if(0 == u4Index)
{
// if((0 == clock_is_on(MT_CG_DISP0_SMI_LARB0)) || (0 == clock_is_on(MT_CG_DISP0_SMI_COMMON)))
if(0x3 & M4U_ReadReg32(0xF4000000 , 0x100))
{
SMIMSG("===SMI%d is off===\n" , u4Index);
return;
}
}
else if(1 == u4Index)
{
// if(0 == clock_is_on(MT_CG_VDEC1_LARB))
if(0x1 & M4U_ReadReg32(0xF6000000 , 0xC))
{
SMIMSG("===SMI%d is off===\n" , u4Index);
return;
}
}
else if(2 == u4Index)
{
// if(0 == clock_is_on(MT_CG_IMAGE_LARB2_SMI))
if(0x1 & M4U_ReadReg32(0xF5000000 , 0))
{
SMIMSG("===SMI%d is off===\n" , u4Index);
return;
}
}
if(u4Index <0 || u4Index > 2)
{
SMIMSG("Doesn't support reg dump for Larb%d\n", u4Index);
return;
}else{
u4Base = gLarbBaseAddr[u4Index];
SMIMSG("===SMI%d reg dump===\n" , u4Index);
SMIMSG("[0x0,0x10,0x60]=[0x%x,0x%x,0x%x]\n" ,M4U_ReadReg32(u4Base , 0x0),M4U_ReadReg32(u4Base , 0x10),M4U_ReadReg32(u4Base , 0x60));
SMIMSG("[0x64,0x8c,0x450]=[0x%x,0x%x,0x%x]\n" ,M4U_ReadReg32(u4Base , 0x64),M4U_ReadReg32(u4Base , 0x8c),M4U_ReadReg32(u4Base , 0x450));
SMIMSG("[0x454,0x600,0x604]=[0x%x,0x%x,0x%x]\n" ,M4U_ReadReg32(u4Base , 0x454),M4U_ReadReg32(u4Base , 0x600),M4U_ReadReg32(u4Base , 0x604));
SMIMSG("[0x610,0x614]=[0x%x,0x%x]\n" ,M4U_ReadReg32(u4Base , 0x610),M4U_ReadReg32(u4Base , 0x614));
SMIMSG("[0x200,0x204,0x208]=[0x%x,0x%x,0x%x]\n" ,M4U_ReadReg32(u4Base , 0x200),M4U_ReadReg32(u4Base , 0x204),M4U_ReadReg32(u4Base , 0x208));
SMIMSG("[0x20c,0x210,0x214]=[0x%x,0x%x,0x%x]\n" ,M4U_ReadReg32(u4Base , 0x20c),M4U_ReadReg32(u4Base , 0x210),M4U_ReadReg32(u4Base , 0x214));
SMIMSG("[0x218,0x21c,0x220]=[0x%x,0x%x,0x%x]\n" ,M4U_ReadReg32(u4Base , 0x218),M4U_ReadReg32(u4Base , 0x21c),M4U_ReadReg32(u4Base , 0x220));
SMIMSG("[0x224,0x228,0x22c]=[0x%x,0x%x,0x%x]\n" ,M4U_ReadReg32(u4Base , 0x224),M4U_ReadReg32(u4Base , 0x228),M4U_ReadReg32(u4Base , 0x22c));
SMIMSG("[0x230,0x234,0x238]=[0x%x,0x%x,0x%x]\n" ,M4U_ReadReg32(u4Base , 0x230),M4U_ReadReg32(u4Base , 0x234),M4U_ReadReg32(u4Base , 0x238));
SMIMSG("[0x23c,0x240]=[0x%x,0x%x]\n" ,M4U_ReadReg32(u4Base , 0x23c),M4U_ReadReg32(u4Base , 0x240));
}
}
void smi_dumpCommonDebugMsg(void)
{
unsigned int u4Base;
//SMI COMMON dump
SMIMSG("===SMI common reg dump===\n");
u4Base = SMI_COMMON_EXT_BASE;
SMIMSG("[0x200,0x204,0x208]=[0x%x,0x%x,0x%x]\n" ,M4U_ReadReg32(u4Base , 0x200),M4U_ReadReg32(u4Base , 0x204),M4U_ReadReg32(u4Base , 0x208));
SMIMSG("[0x20C,0x210,0x214]=[0x%x,0x%x,0x%x]\n" ,M4U_ReadReg32(u4Base , 0x20C),M4U_ReadReg32(u4Base , 0x210),M4U_ReadReg32(u4Base , 0x214));
SMIMSG("[0x218,0x230,0x234]=[0x%x,0x%x,0x%x]\n" ,M4U_ReadReg32(u4Base , 0x218),M4U_ReadReg32(u4Base , 0x230),M4U_ReadReg32(u4Base , 0x234));
SMIMSG("[0x400,0x404]=[0x%x,0x%x]\n" ,M4U_ReadReg32(u4Base , 0x400),M4U_ReadReg32(u4Base , 0x404));
// For VA and PA check:
// 0x1000C5C0 , 0x1000C5C4, 0x1000C5C8, 0x1000C5CC, 0x1000C5D0
u4Base = SMI_COMMON_AO_BASE;
SMIMSG("===SMI always on reg dump===\n");
SMIMSG("[0x5C0,0x5C4,0x5C8]=[0x%x,0x%x,0x%x]\n" ,M4U_ReadReg32(u4Base , 0x5C0),M4U_ReadReg32(u4Base , 0x5C4),M4U_ReadReg32(u4Base , 0x5C8));
SMIMSG("[0x5CC,0x5D0]=[0x%x,0x%x]\n" ,M4U_ReadReg32(u4Base , 0x5CC),M4U_ReadReg32(u4Base , 0x5D0));
}
int larb_reg_restore(int larb)
{
unsigned int regval,regval1,regval2;
unsigned int larb_base = gLarbBaseAddr[larb];
/*
unsigned int* pReg = pLarbRegBackUp[larb];
int i;
//warning: larb_con is controlled by set/clr
regval = *(pReg++);
M4U_WriteReg32(larb_base, SMI_LARB_CON_CLR, ~(regval));
M4U_WriteReg32(larb_base, SMI_LARB_CON_SET, (regval));
M4U_WriteReg32(larb_base, SMI_SHARE_EN, *(pReg++) );
M4U_WriteReg32(larb_base, SMI_ROUTE_SEL, *(pReg++) );
for(i=0; i<3; i++)
{
M4U_WriteReg32(larb_base, SMI_MAU_ENTR_START(i), *(pReg++));
M4U_WriteReg32(larb_base, SMI_MAU_ENTR_END(i), *(pReg++));
M4U_WriteReg32(larb_base, SMI_MAU_ENTR_GID(i), *(pReg++));
}
*/
//Clock manager enable LARB clock before call back restore already, it will be disabled after restore call back returns
//Got to enable OSTD before engine starts
regval = M4U_ReadReg32(larb_base , SMI_LARB_STAT);
regval1 = M4U_ReadReg32(larb_base , SMI_LARB_MON_BUS_REQ0);
regval2 = M4U_ReadReg32(larb_base , SMI_LARB_MON_BUS_REQ1);
if(0 == regval)
{
int retry_count = 0;
SMIMSG("Init OSTD for larb_base: 0x%x\n" , larb_base);
// Write 0x60 = 0xFFFF_FFFF, enable BW limiter
M4U_WriteReg32(larb_base , 0x60 , 0xffffffff);
// Polling 0x600 = 0xaaaa
for(retry_count= 0; retry_count<64; retry_count++)
{
if(M4U_ReadReg32(larb_base , 0x600) == 0xaaaa)
{
//Step3. Once it is found 0x600 == 0xaaaa, we can start to enable outstanding limiter and set outstanding limit
break;
}
SMIMSG("Larb: 0x%x busy : waiting for idle\n" , larb_base);
udelay(500);
}
// Write 0x60 = 0x0, disable BW limiter
M4U_WriteReg32(larb_base , 0x60 , 0x0);
// enable ISTD
M4U_WriteReg32(larb_base , SMI_LARB_OSTD_CTRL_EN , 0xffffffff);
}
else
{
SMIMSG("Larb%d is busy : 0x%x , port:0x%x,0x%x ,fail to set OSTD\n" , larb , regval , regval1 , regval2);
smi_dumpDebugMsg();
SMIERR("DISP_MDP LARB%d OSTD cannot be set:0x%x,port:0x%x,0x%x\n" , larb , regval , regval1 , regval2);
}
if(0 == g_bInited)
{
initSetting();
g_bInited = 1;
SMIMSG("SMI init\n");
}
// Show SMI always on register when larb 0 is enable
if(larb == 0){
SMIMSG("===SMI always on reg dump===\n");
SMIMSG("[0x5C0,0x5C4,0x5C8]=[0x%x,0x%x,0x%x]\n" ,M4U_ReadReg32(SMI_COMMON_AO_BASE , 0x5C0),M4U_ReadReg32(SMI_COMMON_AO_BASE , 0x5C4),M4U_ReadReg32(SMI_COMMON_AO_BASE , 0x5C8));
SMIMSG("[0x5CC,0x5D0]=[0x%x,0x%x]\n" ,M4U_ReadReg32(SMI_COMMON_AO_BASE , 0x5CC),M4U_ReadReg32(SMI_COMMON_AO_BASE , 0x5D0));
}
return 0;
}
void dump_smi_register(void)
{
int i;
SMIMSG(" SMI COMMON Register Start ======= \n");
for(i=0;i<4096/8;i+=4)
{
SMIMSG("+0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x \n", 8*i,
M4U_ReadReg32(SMI_COMMON_EXT_BASE, 8*i + 4*0), M4U_ReadReg32(SMI_COMMON_EXT_BASE, 8*i + 4*1),
M4U_ReadReg32(SMI_COMMON_EXT_BASE, 8*i + 4*2), M4U_ReadReg32(SMI_COMMON_EXT_BASE, 8*i + 4*3),
M4U_ReadReg32(SMI_COMMON_EXT_BASE, 8*i + 4*4), M4U_ReadReg32(SMI_COMMON_EXT_BASE, 8*i + 4*5),
M4U_ReadReg32(SMI_COMMON_EXT_BASE, 8*i + 4*6), M4U_ReadReg32(SMI_COMMON_EXT_BASE, 8*i + 4*7));
}
SMIMSG(" SMI COMMONR egister End ========== \n");
SMIMSG(" SMI LARB Register Start ======= \n");
for(i=0;i<4096/8;i+=4)
{
SMIMSG("+0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x \n", 8*i,
M4U_ReadReg32(LARB0_BASE, 8*i + 4*0), M4U_ReadReg32(LARB0_BASE, 8*i + 4*1),
M4U_ReadReg32(LARB0_BASE, 8*i + 4*2), M4U_ReadReg32(LARB0_BASE, 8*i + 4*3),
M4U_ReadReg32(LARB0_BASE, 8*i + 4*4), M4U_ReadReg32(LARB0_BASE, 8*i + 4*5),
M4U_ReadReg32(LARB0_BASE, 8*i + 4*6), M4U_ReadReg32(LARB0_BASE, 8*i + 4*7));
}
SMIMSG(" SMI LARB egister End ========== \n");
}
