int main() {
#ifndef USE_TIRTOS
MAP_IntVTableBaseSet((unsigned long) &g_pfnVectors[0]);
#endif
MAP_IntEnable(FAULT_SYSTICK);
MAP_IntMasterEnable();
PRCMCC3200MCUInit();
/* Console UART init. */
MAP_PRCMPeripheralClkEnable(CONSOLE_UART_PERIPH, PRCM_RUN_MODE_CLK);
MAP_PinTypeUART(PIN_55, PIN_MODE_3); /* PIN_55 -> UART0_TX */
MAP_PinTypeUART(PIN_57, PIN_MODE_3); /* PIN_57 -> UART0_RX */
MAP_UARTConfigSetExpClk(
CONSOLE_UART, MAP_PRCMPeripheralClockGet(CONSOLE_UART_PERIPH),
CONSOLE_BAUD_RATE,
(UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE | UART_CONFIG_PAR_NONE));
MAP_UARTFIFOLevelSet(CONSOLE_UART, UART_FIFO_TX1_8, UART_FIFO_RX4_8);
MAP_UARTFIFOEnable(CONSOLE_UART);
setvbuf(stdout, NULL, _IOLBF, 0);
setvbuf(stderr, NULL, _IOLBF, 0);
cs_log_set_level(LL_INFO);
cs_log_set_file(stdout);
LOG(LL_INFO, ("Hello, world!"));
MAP_PinTypeI2C(PIN_01, PIN_MODE_1); /* SDA */
MAP_PinTypeI2C(PIN_02, PIN_MODE_1); /* SCL */
I2C_IF_Open(I2C_MASTER_MODE_FST);
/* Set up the red LED. Note that amber and green cannot be used as they share
* pins with I2C. */
MAP_PRCMPeripheralClkEnable(PRCM_GPIOA1, PRCM_RUN_MODE_CLK);
MAP_PinTypeGPIO(PIN_64, PIN_MODE_0, false);
MAP_GPIODirModeSet(GPIOA1_BASE, 0x2, GPIO_DIR_MODE_OUT);
GPIO_IF_LedConfigure(LED1);
GPIO_IF_LedOn(MCU_RED_LED_GPIO);
if (VStartSimpleLinkSpawnTask(8) != 0) {
LOG(LL_ERROR, ("Failed to create SL task"));
}
if (!mg_start_task(MG_TASK_PRIORITY, MG_TASK_STACK_SIZE, mg_init)) {
LOG(LL_ERROR, ("Failed to create MG task"));
}
osi_start();
return 0;
}
// assumes init parameters have been set up correctly
bool uart_init2(pyb_uart_obj_t *self) {
uint uartPerh;
switch (self->uart_id) {
case PYB_UART_0:
self->reg = UARTA0_BASE;
uartPerh = PRCM_UARTA0;
MAP_UARTIntRegister(UARTA0_BASE, UART0IntHandler);
MAP_IntPrioritySet(INT_UARTA0, INT_PRIORITY_LVL_3);
break;
case PYB_UART_1:
self->reg = UARTA1_BASE;
uartPerh = PRCM_UARTA1;
MAP_UARTIntRegister(UARTA1_BASE, UART1IntHandler);
MAP_IntPrioritySet(INT_UARTA1, INT_PRIORITY_LVL_3);
break;
default:
return false;
}
// Enable the peripheral clock
MAP_PRCMPeripheralClkEnable(uartPerh, PRCM_RUN_MODE_CLK | PRCM_SLP_MODE_CLK);
// Reset the uart
MAP_PRCMPeripheralReset(uartPerh);
// Initialize the UART
MAP_UARTConfigSetExpClk(self->reg, MAP_PRCMPeripheralClockGet(uartPerh),
self->baudrate, self->config);
// Enbale the FIFO
MAP_UARTFIFOEnable(self->reg);
// Configure the FIFO interrupt levels
MAP_UARTFIFOLevelSet(self->reg, UART_FIFO_TX4_8, UART_FIFO_RX4_8);
// Configure the flow control mode
UARTFlowControlSet(self->reg, self->flowcontrol);
// Enable the RX and RX timeout interrupts
MAP_UARTIntEnable(self->reg, UART_INT_RX | UART_INT_RT);
self->enabled = true;
return true;
}
bool mgos_uart_hal_configure(struct mgos_uart_state *us,
const struct mgos_uart_config *cfg) {
uint32_t base = cc32xx_uart_get_base(us->uart_no);
if (us->uart_no == 0 && (cfg->tx_fc_type == MGOS_UART_FC_HW ||
cfg->rx_fc_type == MGOS_UART_FC_HW)) {
/* No FC on UART0, according to the TRM. */
return false;
}
MAP_UARTIntDisable(base, ~0);
uint32_t periph = (us->uart_no == 0 ? PRCM_UARTA0 : PRCM_UARTA1);
uint32_t data_cfg = 0;
switch (cfg->num_data_bits) {
case 5:
data_cfg |= UART_CONFIG_WLEN_5;
break;
case 6:
data_cfg |= UART_CONFIG_WLEN_6;
break;
case 7:
data_cfg |= UART_CONFIG_WLEN_7;
break;
case 8:
data_cfg |= UART_CONFIG_WLEN_8;
break;
default:
return false;
}
switch (cfg->parity) {
case MGOS_UART_PARITY_NONE:
data_cfg |= UART_CONFIG_PAR_NONE;
break;
case MGOS_UART_PARITY_EVEN:
data_cfg |= UART_CONFIG_PAR_EVEN;
break;
case MGOS_UART_PARITY_ODD:
data_cfg |= UART_CONFIG_PAR_ODD;
break;
}
switch (cfg->stop_bits) {
case MGOS_UART_STOP_BITS_1:
data_cfg |= UART_CONFIG_STOP_ONE;
break;
case MGOS_UART_STOP_BITS_1_5:
return false; /* Not supported */
case MGOS_UART_STOP_BITS_2:
data_cfg |= UART_CONFIG_STOP_TWO;
break;
}
MAP_UARTConfigSetExpClk(base, MAP_PRCMPeripheralClockGet(periph),
cfg->baud_rate, data_cfg);
if (cfg->tx_fc_type == MGOS_UART_FC_HW ||
cfg->rx_fc_type == MGOS_UART_FC_HW) {
/* Note: only UART1 */
uint32_t ctl = HWREG(base + UART_O_CTL);
if (cfg->tx_fc_type == MGOS_UART_FC_HW) {
ctl |= UART_CTL_CTSEN;
MAP_PinTypeUART(PIN_61, PIN_MODE_3); /* UART1_CTS */
}
if (cfg->rx_fc_type == MGOS_UART_FC_HW) {
ctl |= UART_CTL_RTSEN;
MAP_PinTypeUART(PIN_62, PIN_MODE_3); /* UART1_RTS */
}
HWREG(base + UART_O_CTL) = ctl;
}
MAP_UARTFIFOLevelSet(base, UART_FIFO_TX1_8, UART_FIFO_RX4_8);
MAP_UARTFIFOEnable(base);
return true;
}