int
getncpus(void)
{
int n;
char *p;
Scu *scu;
if (navailcpus == 0) {
scu = (Scu *)soc.scu;
navailcpus = (scu->cfg & MASK(2)) + 1;
if (navailcpus > MAXMACH)
navailcpus = MAXMACH;
p = getconf("*ncpu");
if (p && *p) {
n = atoi(p);
if (n > 0 && n < navailcpus)
navailcpus = n;
}
}
return navailcpus;
}
void mcpPciDriver_unregisterInterrupt(struct mcpPciDriver_dev *devp) {
volatile unsigned int *oc_intcsr = (unsigned int *)
devp->pciBase[0] + OPENCORES_PCI_INTCR;
volatile unsigned int *intcsr = (unsigned int *)
devp->pciBase[1] + TEST_INTCSR;
unsigned int val;
if (!devp->irq_usage) {
// nothing to do
return;
}
if (--devp->irq_usage) {
// nothing to do, still in use
return;
}
// Disable master interrupt
val = readl(intcsr);
writel(MASK(val, TEST_INTCSR_MASTER), intcsr);
// That's all we need to do.
free_irq(devp->dev->irq, devp);
}
void ioapic_map_pin_to_vector(word_t ioapic, word_t pin, word_t level,
word_t polarity, word_t vector)
{
uint32_t ioredtbl_high = 0;
uint32_t index = 0;
index = ioapic * IOAPIC_IRQ_LINES + pin;
ioapic_write(ioapic, IOAPIC_REGSEL, IOREDTBL_HIGH(pin));
ioredtbl_high = ioapic_read(ioapic, IOAPIC_WINDOW) & MASK(IOREDTBL_HIGH_RESERVED_BITS);
/* delivery mode: physical mode only, using APIC ID */
ioredtbl_high |= (ioapic_target_cpu << IOREDTBL_HIGH_RESERVED_BITS);
ioapic_write(ioapic, IOAPIC_WINDOW, ioredtbl_high);
/* we do not need to add IRQ_INT_OFFSET to the vector here */
ioredtbl_state[index] = IOREDTBL_LOW_INTERRUPT_MASK |
(level << IOREDTBL_LOW_TRIGGER_MODE_SHIFT) |
(polarity << IOREDTBL_LOW_POLARITY_SHIFT) |
vector;
ioapic_write(ioapic, IOAPIC_REGSEL, IOREDTBL_LOW(pin));
/* the upper 16 bits are reserved */
ioredtbl_state[index] |= ioapic_read(ioapic, IOAPIC_WINDOW) & ~MASK(16);
ioapic_write(ioapic, IOAPIC_WINDOW, ioredtbl_state[index]);
}
static int
gm20b_clk_init(struct nvkm_clk *base)
{
struct gk20a_clk *clk = gk20a_clk(base);
struct nvkm_subdev *subdev = &clk->base.subdev;
struct nvkm_device *device = subdev->device;
int ret;
/* Set the global bypass control to VCO */
nvkm_mask(device, BYPASSCTRL_SYS,
MASK(BYPASSCTRL_SYS_GPCPLL_WIDTH) << BYPASSCTRL_SYS_GPCPLL_SHIFT,
0);
/* Start with lowest frequency */
base->func->calc(base, &base->func->pstates[0].base);
ret = base->func->prog(&clk->base);
if (ret) {
nvkm_error(subdev, "cannot initialize clock\n");
return ret;
}
return 0;
}
static struct dcache_block *
dcache_alloc (DCACHE *dcache, CORE_ADDR addr)
{
struct dcache_block *db;
/* Take something from the free list */
db = dcache->free_head;
if (db)
{
dcache->free_head = db->p;
}
else
{
/* Nothing left on free list, so grab one from the valid list */
db = dcache->valid_head;
if (!dcache_write_line (dcache, db))
return NULL;
dcache->valid_head = db->p;
}
db->addr = MASK(addr);
db->refs = 0;
db->anydirty = 0;
memset (db->state, ENTRY_BAD, sizeof (db->data));
/* append this line to end of valid list */
if (!dcache->valid_head)
dcache->valid_head = db;
else
dcache->valid_tail->p = db;
dcache->valid_tail = db;
db->p = 0;
return db;
}
word_t
Arch_setMRs_fault(tcb_t *sender, tcb_t* receiver, word_t *receiveIPCBuffer, word_t faultType)
{
switch (faultType) {
case seL4_Fault_VMFault: {
if (config_set(CONFIG_ARM_HYPERVISOR_SUPPORT)) {
word_t ipa, va;
va = getRestartPC(sender);
ipa = (addressTranslateS1CPR(va) & ~MASK(PAGE_BITS)) | (va & MASK(PAGE_BITS));
setMR(receiver, receiveIPCBuffer, seL4_VMFault_IP, ipa);
} else {
setMR(receiver, receiveIPCBuffer, seL4_VMFault_IP, getRestartPC(sender));
}
setMR(receiver, receiveIPCBuffer, seL4_VMFault_Addr,
seL4_Fault_VMFault_get_address(sender->tcbFault));
setMR(receiver, receiveIPCBuffer, seL4_VMFault_PrefetchFault,
seL4_Fault_VMFault_get_instructionFault(sender->tcbFault));
return setMR(receiver, receiveIPCBuffer, seL4_VMFault_FSR,
seL4_Fault_VMFault_get_FSR(sender->tcbFault));
}
#ifdef CONFIG_ARM_HYPERVISOR_SUPPORT
case seL4_Fault_VGICMaintenance:
if (seL4_Fault_VGICMaintenance_get_idxValid(sender->tcbFault)) {
return setMR(receiver, receiveIPCBuffer, seL4_VGICMaintenance_IDX,
seL4_Fault_VGICMaintenance_get_idx(sender->tcbFault));
} else {
return setMR(receiver, receiveIPCBuffer, seL4_VGICMaintenance_IDX, -1);
}
case seL4_Fault_VCPUFault:
return setMR(receiver, receiveIPCBuffer, seL4_VCPUFault_HSR, seL4_Fault_VCPUFault_get_hsr(sender->tcbFault));
#endif
default:
fail("Invalid fault");
}
}
static struct dcache_block *
dcache_alloc (DCACHE *dcache, CORE_ADDR addr)
{
struct dcache_block *db;
if (dcache->size >= dcache_size)
{
/* Evict the least recently allocated line. */
db = dcache->oldest;
remove_block (&dcache->oldest, db);
splay_tree_remove (dcache->tree, (splay_tree_key) db->addr);
}
else
{
db = dcache->freelist;
if (db)
remove_block (&dcache->freelist, db);
else
db = xmalloc (offsetof (struct dcache_block, data) +
dcache->line_size);
dcache->size++;
}
db->addr = MASK (dcache, addr);
db->refs = 0;
/* Put DB at the end of the list, it's the newest. */
append_block (&dcache->oldest, db);
splay_tree_insert (dcache->tree, (splay_tree_key) db->addr,
(splay_tree_value) db);
return db;
}
/*
* Initialize and return a bit extractor state variable for processing.
*/
bit_extractor* initialize_bit_extractor(unsigned int num_bits)
{
bit_extractor* be = (bit_extractor*)malloc(sizeof(bit_extractor));
//Sanity checking
if(num_bits > 32)
be->num2extract = 32;
else
be->num2extract = num_bits;
//Calculate the number of samples needed to fill 32-bits
if(32 % num_bits == 0)
be->samplesNeeded = 32 / be->num2extract;
else
be->samplesNeeded = 32 / be->num2extract + 1;
be->samples2use = be->samplesNeeded;
be->samplesUsed = 0;
be->numLeftoverBits = 0;
be->packedNum = 0;
be->mask = MASK(be->num2extract);
return be;
}
/** \brief manually set PWM output
\param index the heater we're setting the output for
\param value the PWM value to write
anything done by this function is overwritten by heater_tick above if the heater has an associated temp sensor
*/
void heater_set(heater_t index, uint8_t value) {
if (index >= NUM_HEATERS)
return;
heaters_runtime[index].heater_output = value;
if (heaters[index].heater_pwm) {
*(heaters[index].heater_pwm) = heaters[index].invert ?
(255 - value) : value;
if (DEBUG_PID && (debug_flags & DEBUG_PID))
sersendf_P(PSTR("PWM{%u = %u}\n"), index, *heaters[index].heater_pwm);
}
else {
if ((value >= HEATER_THRESHOLD && ! heaters[index].invert) ||
(value < HEATER_THRESHOLD && heaters[index].invert))
*(heaters[index].heater_port) |= MASK(heaters[index].heater_pin);
else
*(heaters[index].heater_port) &= ~MASK(heaters[index].heater_pin);
}
if (value)
power_on();
}
static size_t
put_utf8(unsigned char *buf, ICONV_CHAR c)
{
#define MASK(n) ((0xffffffffu << (n)) & 0xffffffffu)
size_t o_len;
unsigned mask;
if ((c & MASK(7)) == 0) {
*buf = (unsigned char) c;
return 1;
}
o_len = 2;
for (;;) {
if ((c & MASK(11)) == 0)
break;
++o_len;
if ((c & MASK(16)) == 0)
break;
++o_len;
if ((c & MASK(21)) == 0)
break;
++o_len;
if ((c & MASK(26)) == 0)
break;
++o_len;
if ((c & MASK(31)) != 0)
return -EINVAL;
}
buf += o_len;
mask = 0xff80;
for (;;) {
*--buf = 0x80 | (c & 0x3f);
c >>= 6;
mask >>= 1;
if (c < 0x40) {
*--buf = mask | c;
break;
}
}
return o_len;
}
static int
put_utf8(unsigned char *buf, size_t buf_len, ICONV_CHAR c)
{
#define MASK(n) ((0xffffffffu << (n)) & 0xffffffffu)
size_t o_len;
if ((c & MASK(7)) == 0) {
if (buf_len < 1)
return -E2BIG;
*buf = (unsigned char) c;
return 1;
}
o_len = 2;
for (;;) {
if ((c & MASK(11)) == 0)
break;
++o_len;
if ((c & MASK(16)) == 0)
break;
++o_len;
if ((c & MASK(21)) == 0)
break;
++o_len;
if ((c & MASK(26)) == 0)
break;
++o_len;
if ((c & MASK(31)) != 0)
return -EILSEQ;
}
if (buf_len < o_len)
return -E2BIG;
buf += o_len;
buf_len = o_len - 1;
do {
*--buf = 0x80 | (c & 0x3f);
c >>= 6;
} while (--buf_len);
*--buf = (0xff00u >> o_len) | c;
return o_len;
}
void analog_init() {
#if ANALOG_MASK > 0
#ifdef PRR
PRR &= ~MASK(PRADC);
#elif defined PRR0
PRR0 &= ~MASK(PRADC);
#endif
ADMUX = REFERENCE;
// ADC frequency must be less than 200khz or we lose precision. At 16MHz system clock, we must use the full prescale value of 128 to get an ADC clock of 125khz.
ADCSRA = MASK(ADEN) | MASK(ADPS2) | MASK(ADPS1) | MASK(ADPS0);
adc_counter = 0;
adc_running_mask = 1;
DIDR0 = ANALOG_MASK & 0x1F;
// now we start the first conversion and leave the rest to the interrupt
ADCSRA |= MASK(ADIE) | MASK(ADSC);
#endif
}
void Init_RGB_LEDs(void) {
// Enable clock to ports B and D
SIM->SCGC5 |= SIM_SCGC5_PORTB_MASK | SIM_SCGC5_PORTD_MASK;;
// Make 3 pins GPIO
PORTB->PCR[RED_LED_POS] &= ~PORT_PCR_MUX_MASK;
PORTB->PCR[RED_LED_POS] |= PORT_PCR_MUX(1);
PORTB->PCR[GREEN_LED_POS] &= ~PORT_PCR_MUX_MASK;
PORTB->PCR[GREEN_LED_POS] |= PORT_PCR_MUX(1);
PORTD->PCR[BLUE_LED_POS] &= ~PORT_PCR_MUX_MASK;
PORTD->PCR[BLUE_LED_POS] |= PORT_PCR_MUX(1);
// Initially off
PTB->PSOR = MASK(RED_LED_POS);
PTB->PSOR = MASK(GREEN_LED_POS);
PTD->PSOR = MASK(BLUE_LED_POS);
// Set ports to outputs
PTB->PDDR |= MASK(RED_LED_POS) | MASK(GREEN_LED_POS);
PTD->PDDR |= MASK(BLUE_LED_POS);
}
/***********************************************************************
* ADPLL Power On or Off
*
***********************************************************************/
int MT6620_ADPLL_Power_OnOff(int onoff, int ADPLL_clk)
{
int ret = 0;
FM_COM_ASSERT(op_cb->read);
FM_COM_ASSERT(op_cb->write);
FM_COM_ASSERT(op_cb->setbits);
switch(onoff){
case FM_ADPLL_ON:
if((ret = op_cb->write(0x25, 0x040F)))
goto out;
//Remove the Reset_N
if((ret = op_cb->write(0x20, 0x2720)))
goto out;
// change DLF loop gain
// Set FMCR_DLF_GAIN_A = "9"
// Set FMCR_DLF_GAIN_B = "9"
if((ret = op_cb->write(0x22, 0x9980)))
goto out;
//Configure initial I_CODE for calibration
if((ret = op_cb->write(0x25, 0x080F)))
goto out;
//Enable ADPLL DCO
//Set FMCR_DCO_ EN = "1¡±
if(ADPLL_clk == FM_ADPLL_16M){
if((ret = op_cb->write(0x1E, 0x0A63)))
goto out;
// wait 5ms
Delayms(5);
if((ret = op_cb->write(0x1E, 0x0A65)))
goto out;
// wait 5ms
Delayms(5);
if((ret = op_cb->write(0x1E, 0x0A71)))
goto out;
}else if(ADPLL_clk == FM_ADPLL_15M){
if((ret = op_cb->write(0x1E, 0x0863)))
goto out;
// wait 5ms
Delayms(5);
if((ret = op_cb->write(0x1E, 0x0865)))
goto out;
// wait 5ms
Delayms(5);
if((ret = op_cb->write(0x1E, 0x0871)))
goto out;
}else{
ret = -ERR_INVALID_PARA;
goto out;
}
// wait 100ms
Delayms(100);
if((ret = op_cb->write(0x2A, 0x1026)))
goto out;
break;
//ADPLL Power Off Sequence
case FM_ADPLL_OFF:
// Set rgfrf_top_ck = "0"
if((ret = op_cb->setbits(0x2A, 0, MASK(12))))//set 2A D12=0
goto out;
// Set FMCR_OPEN_LOOP_EN = "0"
// Set FMCR_PLL_EN = "0"
// Set FMCR_DCO_EN = "0"
if((ret = op_cb->setbits(0x1E, 0, MASK(7)&MASK(4)&MASK(0))))//set 1E D7 D4 D0=0
goto out;
// Set rgfrf_adpll_reset_n = "0"
if((ret = op_cb->setbits(0x20, 0, MASK(13))))//set 20 D13=0
goto out;
// Set rgfrf_adpll_reset_n = "1"
if((ret = op_cb->setbits(0x20, BITn(13), MASK(13))))//set 20 D13=1
goto out;
break;
default:
break;
}
out:
return ret;
}
/** Initialise the CPU.
This sets up the CPU the way we need it. It disables modules we don't use,
so they don't mess on the I/O pins they're connected to.
*/
void cpu_init() {
#ifdef PRR
#if defined I2C && defined SPI
PRR = MASK(PRADC);
#elif defined SPI
PRR = MASK(PRADC) | MASK(PRTWI);
#elif defined I2C
PRR = MASK(PRADC) | MASK(PRSPI);
#else
PRR = MASK(PRADC) | MASK(PRTWI) | MASK(PRSPI);
#endif
#elif defined PRR0
#if defined I2C && defined SPI
PRR0 = MASK(PRADC);
#elif defined SPI
PRR0 = MASK(PRADC) | MASK(PRTWI);
#elif defined I2C
PRR0 = MASK(PRADC) | MASK(PRSPI);
#else
PRR0 = MASK(PRADC) | MASK(PRTWI) | MASK(PRSPI);
#endif
#if defined(PRUSART3)
// Don't use USART2 or USART3. Leave USART1 for GEN3 and derivatives.
PRR1 |= MASK(PRUSART3) | MASK(PRUSART2);
#endif
#if defined(PRUSART2)
// Don't use USART2 or USART3. Leave USART1 for GEN3 and derivatives.
PRR1 |= MASK(PRUSART2);
#endif
#endif
ACSR = MASK(ACD);
}
/// called every 10ms from clock.c - check all temp sensors that are ready for checking
void temp_sensor_tick() {
temp_sensor_t i = 0;
for (; i < NUM_TEMP_SENSORS; i++) {
if (temp_sensors_runtime[i].next_read_time) {
temp_sensors_runtime[i].next_read_time--;
}
else {
uint16_t temp = 0;
//time to deal with this temp sensor
switch(temp_sensors[i].temp_type) {
#ifdef TEMP_MAX6675
case TT_MAX6675:
#ifdef PRR
PRR &= ~MASK(PRSPI);
#elif defined PRR0
PRR0 &= ~MASK(PRSPI);
#endif
#ifdef NAL_REPRAP
/* This section is compatible with the mendel original implementation of the MAX6675.
* Not using the SPI as the MISO line is used to control our heater.
*/
WRITE(MAX6675_CS, 0); // Enable device
// Read in 16 bits from the MAX6675
for (uint8_t i=0; i<16; i++){
WRITE(MAX6675_SCK,1); // Set Clock to HIGH
temp <<= 1; // shift left by one
// Read bit and add it to our variable
temp += (READ(MAX6675_SO) != 0 );
WRITE(MAX6675_SCK,0); // Set Clock to LOW
}
WRITE(MAX6675_CS, 1); //Disable Device
#else
SPCR = MASK(MSTR) | MASK(SPE) | MASK(SPR0);
// enable TT_MAX6675
WRITE(SS, 0);
// ensure 100ns delay - a bit extra is fine
delay(1);
// read MSB
SPDR = 0;
for (;(SPSR & MASK(SPIF)) == 0;);
temp = SPDR;
temp <<= 8;
// read LSB
SPDR = 0;
for (;(SPSR & MASK(SPIF)) == 0;);
temp |= SPDR;
// disable TT_MAX6675
WRITE(SS, 1);
#endif
temp_sensors_runtime[i].temp_flags = 0;
if ((temp & 0x8002) == 0) {
// got "device id"
temp_sensors_runtime[i].temp_flags |= PRESENT;
if (temp & 4) {
// thermocouple open
temp_sensors_runtime[i].temp_flags |= TCOPEN;
}
else {
temp = temp >> 3;
}
}
// this number depends on how frequently temp_sensor_tick is called. the MAX6675 can give a reading every 0.22s, so set this to about 250ms
temp_sensors_runtime[i].next_read_time = 25;
break;
#endif /* TEMP_MAX6675 */
#ifdef TEMP_THERMISTOR
case TT_THERMISTOR:
do {
uint8_t j, table_num;
//Read current temperature
temp = analog_read(temp_sensors[i].temp_pin);
// check for open circuit
if (temp ==1023){
temp = 0 ; // this should convert to max temperature and ensure the heaters are turned off
temp_sensors_runtime[i].temp_flags |= TCOPEN;
}
// for thermistors the thermistor table number is in the additional field
table_num = temp_sensors[i].additional;
//Calculate real temperature based on lookup table
for (j = 1; j < NUMTEMPS; j++) {
if (pgm_read_word(&(temptable[table_num][j][0])) > temp) {
// Thermistor table is already in 14.2 fixed point
#ifndef EXTRUDER
if (debug_flags & DEBUG_PID)
sersendf_P(PSTR("pin:%d Raw ADC:%d table entry: %d"),temp_sensors[i].temp_pin,temp,j);
#endif
// Linear interpolating temperature value
// y = ((x - x₀)y₁ + (x₁-x)y₀ ) / (x₁ - x₀)
// y = temp
// x = ADC reading
// x₀= temptable[j-1][0]
// x₁= temptable[j][0]
// y₀= temptable[j-1][1]
// y₁= temptable[j][1]
// y =
// Wikipedia's example linear interpolation formula.
temp = (
// ((x - x₀)y₁
((uint32_t)temp - pgm_read_word(&(temptable[table_num][j-1][0]))) * pgm_read_word(&(temptable[table_num][j][1]))
// +
+
// (x₁-x)
(pgm_read_word(&(temptable[table_num][j][0])) - (uint32_t)temp)
// y₀ )
* pgm_read_word(&(temptable[table_num][j-1][1])))
// /
/
// (x₁ - x₀)
(pgm_read_word(&(temptable[table_num][j][0])) - pgm_read_word(&(temptable[table_num][j-1][0])));
#ifndef EXTRUDER
if (debug_flags & DEBUG_PID)
sersendf_P(PSTR(" temp:%d.%d"),temp/4,(temp%4)*25);
#endif
break;
}
}
#ifndef EXTRUDER
if (debug_flags & DEBUG_PID)
sersendf_P(PSTR(" Sensor:%d\n"),i);
#endif
//Clamp for overflows
if (j == NUMTEMPS)
temp = temptable[table_num][NUMTEMPS-1][1];
temp_sensors_runtime[i].next_read_time = 0;
} while (0);
break;
#endif /* TEMP_THERMISTOR */
#ifdef TEMP_AD595
case TT_AD595:
temp = analog_read(temp_sensors[i].temp_pin);
// convert
// >>8 instead of >>10 because internal temp is stored as 14.2 fixed point
temp = (temp * 500L) >> 8;
temp_sensors_runtime[i].next_read_time = 0;
break;
#endif /* TEMP_AD595 */
#ifdef TEMP_PT100
case TT_PT100:
#warning TODO: PT100 code
break
#endif /* TEMP_PT100 */
#ifdef TEMP_INTERCOM
case TT_INTERCOM:
temp = read_temperature(temp_sensors[i].temp_pin);
temp_sensors_runtime[i].next_read_time = 25;
break;
#endif /* TEMP_INTERCOM */
#ifdef TEMP_DUMMY
case TT_DUMMY:
temp = temp_sensors_runtime[i].last_read_temp;
if (temp_sensors_runtime[i].target_temp > temp)
temp++;
else if (temp_sensors_runtime[i].target_temp < temp)
temp--;
temp_sensors_runtime[i].next_read_time = 0;
break;
#endif /* TEMP_DUMMY */
default: /* prevent compiler warning */
break;
}
temp_sensors_runtime[i].last_read_temp = temp;
if (labs((int16_t)(temp - temp_sensors_runtime[i].target_temp)) < (TEMP_HYSTERESIS*4)) {
if (temp_sensors_runtime[i].temp_residency < (TEMP_RESIDENCY_TIME*100))
temp_sensors_runtime[i].temp_residency++;
}
else {
temp_sensors_runtime[i].temp_residency = 0;
}
if (temp_sensors[i].heater < NUM_HEATERS) {
heater_tick(temp_sensors[i].heater, i, temp_sensors_runtime[i].last_read_temp, temp_sensors_runtime[i].target_temp);
}
}
}
static bool
transform_utf16_utf7 (RECODE_CONST_STEP step, RECODE_TASK task)
{
int character;
unsigned value;
if (!get_ucs2 (&value, step, task))
TASK_RETURN (task);
while (true)
if (IS_BODY_DIRECT (value))
{
/* Copy one direct character. */
put_byte (value, task);
if (!get_ucs2 (&value, step, task))
TASK_RETURN (task);
}
else
{
/* Copy a string of non-direct characters. */
put_byte ('+', task);
while (!IS_BODY_DIRECT (value))
{
unsigned split;
/* Process first UCS-2 value of a triplet. */
put_byte (base64_value_to_char[MASK (6) & value >> 10], task);
put_byte (base64_value_to_char[MASK (6) & value >> 4], task);
split = (value & MASK (4)) << 2;
if (!get_ucs2 (&value, step, task))
{
put_byte (base64_value_to_char[split], task);
TASK_RETURN (task);
}
/* Process second UCS-2 value of a triplet. */
if (IS_BODY_DIRECT (value))
{
put_byte (base64_value_to_char[split], task);
break;
}
put_byte (base64_value_to_char[split | (MASK (2) & value >> 14)],
task);
put_byte (base64_value_to_char[MASK (6) & value >> 8], task);
put_byte (base64_value_to_char[MASK (6) & value >> 2], task);
split = (value & MASK (2)) << 4;
if (!get_ucs2 (&value, step, task))
{
put_byte (base64_value_to_char[split], task);
TASK_RETURN (task);
}
/* Process third UCS-2 value of a triplet. */
if (IS_BODY_DIRECT (value))
{
put_byte (base64_value_to_char[split], task);
break;
}
put_byte (base64_value_to_char[split | (MASK (4) & value >> 12)],
task);
put_byte (base64_value_to_char[MASK (6) & value >> 6], task);
put_byte (base64_value_to_char[MASK (6) & value], task);
if (!get_ucs2 (&value, step, task))
TASK_RETURN (task);
}
if (IS_BASE64 (value))
put_byte ('-', task);
}
TASK_RETURN (task);
}
static bool
transform_utf7_utf16 (RECODE_CONST_STEP step, RECODE_TASK task)
{
int character;
unsigned value;
unsigned split;
character = get_byte (task);
if (character != EOF && task->byte_order_mark)
put_ucs2 (BYTE_ORDER_MARK, task);
while (character != EOF)
if (character == '+')
{
character = get_byte (task);
while (IS_BASE64 (character))
{
/* Process first byte of first quadruplet. */
value = base64_char_to_value[character] << 10;
character = get_byte (task);
/* Process second byte of first quadruplet. */
if (!IS_BASE64 (character))
{
RETURN_IF_NOGO (RECODE_INVALID_INPUT, step, task);
break;
}
value |= base64_char_to_value[character] << 4;
character = get_byte (task);
/* Process third byte of first quadruplet. */
if (!IS_BASE64 (character))
{
RETURN_IF_NOGO (RECODE_INVALID_INPUT, step, task);
break;
}
split = base64_char_to_value[character];
value |= split >> 2;
if (IS_BODY_DIRECT (value))
RETURN_IF_NOGO (RECODE_NOT_CANONICAL, step, task);
put_ucs2 (value, task);
character = get_byte (task);
/* Process fourth byte of first quadruplet. */
if (!IS_BASE64 (character))
{
if (MASK (2) & split)
RETURN_IF_NOGO (RECODE_INVALID_INPUT, step, task);
break;
}
value = ((MASK (2) & split) << 14
| base64_char_to_value[character] << 8);
character = get_byte (task);
/* Process first byte of second quadruplet. */
if (!IS_BASE64 (character))
{
RETURN_IF_NOGO (RECODE_INVALID_INPUT, step, task);
break;
}
value |= base64_char_to_value[character] << 2;
character = get_byte (task);
/* Process second byte of second quadruplet. */
if (!IS_BASE64 (character))
{
RETURN_IF_NOGO (RECODE_INVALID_INPUT, step, task);
break;
}
split = base64_char_to_value[character];
value |= split >> 4;
if (IS_BODY_DIRECT (value))
RETURN_IF_NOGO (RECODE_NOT_CANONICAL, step, task);
put_ucs2 (value, task);
character = get_byte (task);
/* Process third byte of second quadruplet. */
if (!IS_BASE64 (character))
{
if (MASK (4) & split)
RETURN_IF_NOGO (RECODE_INVALID_INPUT, step, task);
break;
}
value = ((MASK (4) & split) << 12
| base64_char_to_value[character] << 6);
character = get_byte (task);
/* Process fourth byte of second quadruplet. */
if (!IS_BASE64 (character))
{
RETURN_IF_NOGO (RECODE_INVALID_INPUT, step, task);
break;
}
value |= base64_char_to_value[character];
if (IS_BODY_DIRECT (value))
RETURN_IF_NOGO (RECODE_NOT_CANONICAL, step, task);
put_ucs2 (value, task);
character = get_byte (task);
}
if (character == '-')
{
character = get_byte (task);
if (!IS_BASE64 (character))
RETURN_IF_NOGO (RECODE_NOT_CANONICAL, step, task);
}
}
/// initialise all I/O - set pins as input or output, turn off unused subsystems, etc
void io_init(void) {
// disable modules we don't use
#ifdef PRR
PRR = MASK(PRTWI) | MASK(PRADC) | MASK(PRSPI);
#elif defined PRR0
PRR0 = MASK(PRTWI) | MASK(PRADC) | MASK(PRSPI);
#if defined(PRUSART3)
// don't use USART2 or USART3- leave USART1 for GEN3 and derivatives
PRR1 |= MASK(PRUSART3) | MASK(PRUSART2);
#endif
#if defined(PRUSART2)
// don't use USART2 or USART3- leave USART1 for GEN3 and derivatives
PRR1 |= MASK(PRUSART2);
#endif
#endif
ACSR = MASK(ACD);
// setup I/O pins
// X Stepper
//WRITE(X_STEP_PIN, 0); SET_OUTPUT(X_STEP_PIN);
//WRITE(X_DIR_PIN, 0); SET_OUTPUT(X_DIR_PIN);
#ifdef X_MIN_PIN
SET_INPUT(X_MIN_PIN);
WRITE(X_MIN_PIN, 0); // pullup resistors off
#endif
#ifdef X_MAX_PIN
SET_INPUT(X_MAX_PIN);
WRITE(X_MAX_PIN, 0); // pullup resistors off
#endif
// Y Stepper
//WRITE(Y_STEP_PIN, 0); SET_OUTPUT(Y_STEP_PIN);
//WRITE(Y_DIR_PIN, 0); SET_OUTPUT(Y_DIR_PIN);
#ifdef Y_MIN_PIN
SET_INPUT(Y_MIN_PIN);
WRITE(Y_MIN_PIN, 0); // pullup resistors off
#endif
#ifdef Y_MAX_PIN
SET_INPUT(Y_MAX_PIN);
WRITE(Y_MAX_PIN, 0); // pullup resistors off
#endif
// Z Stepper
#if defined Z_STEP_PIN && defined Z_DIR_PIN
WRITE(Z_STEP_PIN, 0); SET_OUTPUT(Z_STEP_PIN);
WRITE(Z_DIR_PIN, 0); SET_OUTPUT(Z_DIR_PIN);
#endif
#ifdef Z_MIN_PIN
SET_INPUT(Z_MIN_PIN);
WRITE(Z_MIN_PIN, 0); // pullup resistors off
#endif
#ifdef Z_MAX_PIN
SET_INPUT(Z_MAX_PIN);
WRITE(Z_MAX_PIN, 0); // pullup resistors off
#endif
#if defined E_STEP_PIN && defined E_DIR_PIN
WRITE(E_STEP_PIN, 0); SET_OUTPUT(E_STEP_PIN);
WRITE(E_DIR_PIN, 0); SET_OUTPUT(E_DIR_PIN);
#endif
// Common Stepper Enable
#ifdef STEPPER_ENABLE_PIN
#ifdef STEPPER_INVERT_ENABLE
WRITE(STEPPER_ENABLE_PIN, 0);
#else
WRITE(STEPPER_ENABLE_PIN, 1);
#endif
SET_OUTPUT(STEPPER_ENABLE_PIN);
#endif
// X Stepper Enable
#ifdef X_ENABLE_PIN
#ifdef X_INVERT_ENABLE
WRITE(X_ENABLE_PIN, 0);
#else
WRITE(X_ENABLE_PIN, 1);
#endif
SET_OUTPUT(X_ENABLE_PIN);
#endif
// Y Stepper Enable
#ifdef Y_ENABLE_PIN
#ifdef Y_INVERT_ENABLE
WRITE(Y_ENABLE_PIN, 0);
#else
WRITE(Y_ENABLE_PIN, 1);
#endif
SET_OUTPUT(Y_ENABLE_PIN);
#endif
// Z Stepper Enable
#ifdef Z_ENABLE_PIN
#ifdef Z_INVERT_ENABLE
WRITE(Z_ENABLE_PIN, 0);
#else
WRITE(Z_ENABLE_PIN, 1);
#endif
SET_OUTPUT(Z_ENABLE_PIN);
#endif
// E Stepper Enable
#ifdef E_ENABLE_PIN
#ifdef E_INVERT_ENABLE
WRITE(E_ENABLE_PIN, 0);
#else
WRITE(E_ENABLE_PIN, 1);
#endif
SET_OUTPUT(E_ENABLE_PIN);
#endif
#ifdef STEPPER_ENABLE_PIN
power_off();
#endif
#ifdef TEMP_MAX6675
// setup SPI
WRITE(SCK, 0); SET_OUTPUT(SCK);
WRITE(MOSI, 1); SET_OUTPUT(MOSI);
WRITE(MISO, 1); SET_INPUT(MISO);
WRITE(SS, 1); SET_OUTPUT(SS);
#endif
#ifdef TEMP_INTERCOM
// Enable the RS485 transceiver
SET_OUTPUT(RX_ENABLE_PIN);
SET_OUTPUT(TX_ENABLE_PIN);
WRITE(RX_ENABLE_PIN,0);
disable_transmit();
#endif
}
int pass_for_frame(void const *frame, uint32_t framelen, bool outgoing) {
int pass = DROP_FRAME;
if (framelen < ETH_HLEN) {
return pass;
}
// getting protocol type at byte 12
struct ip_meta pktipm;
uint16_t frametype = MASK(OFFSET(frame, ETHEROFF), 0xFFFF, 0);
uint8_t *curptr = OFFSET(frame, ETH_HLEN);
framelen -= ETH_HLEN;
//TODO handle more types of non-IP frames
switch (frametype) {
case 0x0800:
// regular IP, see below
pktipm = get_ip_metadata(curptr, framelen);
break;
case 0x0806:
// ARP
//pass = handle_arp(frame, curptr, framelen, outgoing);
if (outgoing) {
pass = FRAME_TO_TAP;
} else {
pass = FRAME_TO_ALL;
}
default:
return pass;
}
// handle IP
if (pktipm.ipm_hlen > 0) {
bool is_tcp = false;
curptr += pktipm.ipm_hlen;
framelen -= pktipm.ipm_hlen;
switch (pktipm.ipm_protocol) {
case 6:
is_tcp = true;
// fall through:
case 17:
{
struct conn_desc pktcd = get_conn_metadata(
curptr, framelen, is_tcp);
if (CMASK(&pktipm.ipm_receiver, 0xF0, 0) == 0xE0) {
/* multicast: */
if (outgoing) {
pass = FRAME_TO_ALL_AND_TAP;
} else {
pass = FRAME_TO_ALL;
}
} else if (EQIP(&pktipm.ipm_receiver, &ip_address)) {
/* own IP address, so the receiver is local */
/* Make sure packets are not re-sent:
* Either they come from outside,
* so we are the receiver, or they are loopback.
* Packets cannot be sent from the system
* to the outside world
* with another than the global system IP address. */
if (!outgoing ||
EQIP(&pktipm.ipm_sender, &ip_address)) {
pass = lookup_bus(
pktcd.cd_dest_port,
is_tcp);
}
} else {
/* for remote receivers */
if (outgoing &&
EQIP(&pktipm.ipm_sender, &ip_address)) {
// this is not for our realm -- send it out
int srcbus = lookup_bus(
pktcd.cd_source_port,
is_tcp);
if (srcbus >= 0) {
// source bus is valid, send frame
pass = FRAME_TO_TAP;
}
}
}
}
}
}
return pass;
}
static void set_resize_cursor(int wid)
{
static int resize_cursor = 0;
if (!resize_cursor) {
GR_BITMAP resize_fg[16];
GR_BITMAP resize_bg[16];
resize_fg[0] = MASK(_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_);
resize_fg[1] = MASK(_,X,X,X,X,X,_,_,_,_,_,_,_,_,_,_);
resize_fg[2] = MASK(_,X,X,X,X,_,_,_,_,_,_,_,_,_,_,_);
resize_fg[3] = MASK(_,X,X,X,_,_,_,_,_,_,_,_,_,_,_,_);
resize_fg[4] = MASK(_,X,X,_,X,_,_,_,_,_,_,_,_,_,_,_);
resize_fg[5] = MASK(_,X,_,_,_,X,_,_,_,_,_,_,_,_,_,_);
resize_fg[6] = MASK(_,_,_,_,_,_,X,_,_,_,_,_,_,_,_,_);
resize_fg[7] = MASK(_,_,_,_,_,_,_,X,_,_,_,_,_,_,_,_);
resize_fg[8] = MASK(_,_,_,_,_,_,_,_,X,_,_,_,_,_,_,_);
resize_fg[9] = MASK(_,_,_,_,_,_,_,_,_,X,_,_,_,_,_,_);
resize_fg[10] = MASK(_,_,_,_,_,_,_,_,_,_,X,_,_,_,X,_);
resize_fg[11] = MASK(_,_,_,_,_,_,_,_,_,_,_,X,_,X,X,_);
resize_fg[12] = MASK(_,_,_,_,_,_,_,_,_,_,_,_,X,X,X,_);
resize_fg[13] = MASK(_,_,_,_,_,_,_,_,_,_,_,X,X,X,X,_);
resize_fg[14] = MASK(_,_,_,_,_,_,_,_,_,_,X,X,X,X,X,_);
resize_fg[15] = MASK(_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_);
resize_bg[0] = MASK(X,X,X,X,X,X,X,_,_,_,_,_,_,_,_,_);
resize_bg[1] = MASK(X,X,X,X,X,X,X,_,_,_,_,_,_,_,_,_);
resize_bg[2] = MASK(X,X,X,X,X,X,_,_,_,_,_,_,_,_,_,_);
resize_bg[3] = MASK(X,X,X,X,X,_,_,_,_,_,_,_,_,_,_,_);
resize_bg[4] = MASK(X,X,X,X,X,X,_,_,_,_,_,_,_,_,_,_);
resize_bg[5] = MASK(X,X,X,_,X,X,X,_,_,_,_,_,_,_,_,_);
resize_bg[6] = MASK(X,X,_,_,_,X,X,X,_,_,_,_,_,_,_,_);
resize_bg[7] = MASK(_,_,_,_,_,_,X,X,X,_,_,_,_,_,_,_);
resize_bg[8] = MASK(_,_,_,_,_,_,_,X,X,X,_,_,_,_,_,_);
resize_bg[9] = MASK(_,_,_,_,_,_,_,_,X,X,X,_,_,_,X,X);
resize_bg[10] = MASK(_,_,_,_,_,_,_,_,_,X,X,X,_,X,X,X);
resize_bg[11] = MASK(_,_,_,_,_,_,_,_,_,_,X,X,X,X,X,X);
resize_bg[12] = MASK(_,_,_,_,_,_,_,_,_,_,_,X,X,X,X,X);
resize_bg[13] = MASK(_,_,_,_,_,_,_,_,_,_,X,X,X,X,X,X);
resize_bg[14] = MASK(_,_,_,_,_,_,_,_,_,X,X,X,X,X,X,X);
resize_bg[15] = MASK(_,_,_,_,_,_,_,_,_,X,X,X,X,X,X,X);
resize_cursor = GrNewCursor(16, 16, 8, 8, WHITE, BLACK,
(MWIMAGEBITS *)resize_fg, (MWIMAGEBITS *)resize_bg);
}
GrSetWindowCursor(wid, resize_cursor);
}
/* Neither return not error IP -- no chance to recover -> PANIC */ MCESEV( PANIC, "Neither restart nor error IP", EXCP, MCGMASK(MCG_STATUS_RIPV|MCG_STATUS_EIPV, 0) ), MCESEV( PANIC, "In kernel and no restart IP", EXCP, KERNEL, MCGMASK(MCG_STATUS_RIPV, 0) ), MCESEV( PANIC, "In kernel and no restart IP", EXCP, KERNEL_RECOV, MCGMASK(MCG_STATUS_RIPV, 0) ), MCESEV( DEFERRED, "Deferred error", NOSER, MASK(MCI_STATUS_UC|MCI_STATUS_DEFERRED|MCI_STATUS_POISON, MCI_STATUS_DEFERRED) ), MCESEV( KEEP, "Corrected error", NOSER, BITCLR(MCI_STATUS_UC) ), /* ignore OVER for UCNA */ MCESEV( UCNA, "Uncorrected no action required", SER, MASK(MCI_UC_SAR, MCI_STATUS_UC) ), MCESEV( PANIC, "Illegal combination (UCNA with AR=1)", SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR, MCI_STATUS_UC|MCI_STATUS_AR)
MUX8("clk72mhz", mux_pllp3_pllc_clkm, CLK_SOURCE_CLK72MHZ, 177, TEGRA_PERIPH_NO_RESET, tegra_clk_clk72Mhz),
MUX8_NOGATE_LOCK("sor0_lvds", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_SOR0, tegra_clk_sor0_lvds, &sor0_lock),
MUX_FLAGS("csite", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_CSITE, 73, TEGRA_PERIPH_ON_APB, tegra_clk_csite, CLK_IGNORE_UNUSED),
NODIV("disp1", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_DISP1, 29, 7, 27, 0, tegra_clk_disp1, NULL),
NODIV("disp2", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_DISP2, 29, 7, 26, 0, tegra_clk_disp2, NULL),
NODIV("sor0", mux_clkm_plldp_sor0lvds, CLK_SOURCE_SOR0, 14, 3, 182, 0, tegra_clk_sor0, &sor0_lock),
UART("uarta", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTA, 6, tegra_clk_uarta),
UART("uartb", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTB, 7, tegra_clk_uartb),
UART("uartc", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTC, 55, tegra_clk_uartc),
UART("uartd", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTD, 65, tegra_clk_uartd),
UART("uarte", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTE, 66, tegra_clk_uarte),
XUSB("xusb_host_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_HOST_SRC, 143, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_host_src),
XUSB("xusb_falcon_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_FALCON_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_falcon_src),
XUSB("xusb_fs_src", mux_clkm_48M_pllp_480M, CLK_SOURCE_XUSB_FS_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_fs_src),
XUSB("xusb_ss_src", mux_clkm_pllre_clk32_480M_pllc_ref, CLK_SOURCE_XUSB_SS_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_ss_src),
NODIV("xusb_hs_src", mux_ss_60M, CLK_SOURCE_XUSB_SS_SRC, 25, MASK(1), 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_hs_src, NULL),
XUSB("xusb_dev_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_DEV_SRC, 95, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_dev_src),
};
static struct tegra_periph_init_data gate_clks[] = {
GATE("rtc", "clk_32k", 4, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_rtc, 0),
GATE("timer", "clk_m", 5, 0, tegra_clk_timer, 0),
GATE("isp", "clk_m", 23, 0, tegra_clk_isp, 0),
GATE("vcp", "clk_m", 29, 0, tegra_clk_vcp, 0),
GATE("apbdma", "clk_m", 34, 0, tegra_clk_apbdma, 0),
GATE("kbc", "clk_32k", 36, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_kbc, 0),
GATE("fuse", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse, 0),
GATE("fuse_burn", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse_burn, 0),
GATE("kfuse", "clk_m", 40, TEGRA_PERIPH_ON_APB, tegra_clk_kfuse, 0),
GATE("apbif", "clk_m", 107, TEGRA_PERIPH_ON_APB, tegra_clk_apbif, 0),
GATE("hda2hdmi", "clk_m", 128, TEGRA_PERIPH_ON_APB, tegra_clk_hda2hdmi, 0),
/***********************************************************************
* Frequency Avoidance
*
***********************************************************************/
int MT6620_ADPLL_Freq_Avoid(uint16_t freq, int *freqavoid)
{
int ret = 0;
int ADPLL_clk = FM_ADPLL_15M;
uint16_t dataRead = 0;
uint16_t indx = 0;
static uint16_t Avoid_Channels[] ={
767, 768, 769, 770, 806, 807, 808, 844, 845, 846, 872, 883, 884, 920,
921, 922, 923, 936, 949, 960, 961, 998, 999, 1000, 1013, 1036, 1037, 1038, 1074,
1075, 1076, 1077};
FM_LOG_DBG(D_MAIN,"+%s, [freq=%d]\n", __func__, (int)freq);
FM_COM_ASSERT(op_cb->read);
FM_COM_ASSERT(op_cb->write);
*freqavoid = 0;
dataRead = sizeof(Avoid_Channels)/sizeof(Avoid_Channels[0]);
indx = 0;
while((indx < dataRead) && (ADPLL_clk != FM_ADPLL_16M)){
if(Avoid_Channels[indx] == freq){
ADPLL_clk = FM_ADPLL_16M;
*freqavoid = 1;
}
indx++;
}
//isADPLL_16M = 1;
if((ret = op_cb->read(0x1E, &dataRead)))
goto out;
if(((dataRead&BITn(9))&&(ADPLL_clk == FM_ADPLL_16M))||(!(dataRead&BITn(9))&&(ADPLL_clk == FM_ADPLL_15M)))//1EH, D9
goto out; //we need not do freq avoid at these caes
if(ADPLL_clk == FM_ADPLL_16M){
//Set rgf_f16mode_en = X
if((ret = op_cb->setbits(0x61, BITn(0), MASK(0))))//set 61H D0=1, 16.384MHZ
goto out;
}else if(ADPLL_clk == FM_ADPLL_15M){
//Set rgf_f16mode_en = X
if((ret = op_cb->setbits(0x61, 0, MASK(0))))//set 61H D0=0, 15.36MHZ
goto out;
}else{
ret = -ERR_INVALID_PARA;
goto out;
}
// Disable ADPLL
ret = MT6620_ADPLL_Power_OnOff(FM_ADPLL_OFF, ADPLL_clk);
if(ret){
FM_LOG_NTC(D_MAIN,"%s, ADPLL OFF failed, [ret=%d]n", __func__, ret);
goto out;
}
//Set FMCR_DCO_CK_SEL = ? (default = 0, 15.36)
if(ADPLL_clk == FM_ADPLL_16M){
if((ret = op_cb->setbits(0x1E, BITn(9), MASK(9))))//set 1EH D9=1, 16.384MHZ
goto out;
}else if(ADPLL_clk == FM_ADPLL_15M){
if((ret = op_cb->setbits(0x1E, 0, MASK(9))))//set 1EH D9=0, 15.36MHZ
goto out;
}else{
ret = -ERR_INVALID_PARA;
goto out;
}
// Ensable ADPLL
ret = MT6620_ADPLL_Power_OnOff(FM_ADPLL_ON, ADPLL_clk);
if(ret){
FM_LOG_NTC(D_MAIN,"%s, ADPLL ON failed, [ret=%d]\n", __func__, ret);
goto out;
}
//Set rgfrf_cnt_resync_b = 0
if((ret = op_cb->setbits(0x2A, 0, MASK(1))))//set 2AH D1=0
goto out;
//Set rgfrf_cnt_resync_b = 1
if((ret = op_cb->setbits(0x2A, BITn(1), MASK(1))))//set 2AH D1=1
goto out;
out:
FM_LOG_NTC(D_MAIN,"-%s, [ADPLL_clk=%d][ret=%d]\n", __func__, (int)ADPLL_clk, ret);
return ret;
}
/***********************************************************************
* TX RTC PWR CTRL
*
***********************************************************************/
int MT6620_RTC_Drift_CTRL(uint16_t freq, int *ctr)
{
int ret = 0;
uint16_t reg = 0;
int chanel_resolution = 1;
int16_t compensation_int16 = 0;
int tmp = 0;
int drift = *ctr;
FM_LOG_DBG(D_MAIN,"+%s, [freq=%d]\n", __func__, (int)freq);
FM_COM_ASSERT(op_cb->read);
FM_COM_ASSERT(op_cb->write);
FM_COM_ASSERT(op_cb->setbits);
FM_COM_ASSERT(ctr);
//turn off VCO tracking
if((ret = op_cb->setbits(0x48, 0, MASK(15))))//set 48 D15=0
goto out;
//get channel resolution
if((ret = op_cb->read(0x46, ®)))
goto out;
reg &= 0xC000;
switch(reg >> 14){
case 0:
chanel_resolution = 1024;
break;
case 1:
chanel_resolution = 512;
break;
case 2:
chanel_resolution = 256;
break;
case 3:
chanel_resolution = 128;
break;
default:
FM_LOG_ERR(D_MAIN,"chanel_resolution error[%d]\n", (int)(reg >> 14));
break;
}
//caculate and applye compensation
FM_LOG_DBG(D_MAIN,"[resolution=%d][freq=%d][drift=%d]\n", chanel_resolution, (int)(freq/10), (*ctr));
tmp = (2*drift*(freq/10))/chanel_resolution;
compensation_int16 = (int16_t)tmp;
if(compensation_int16 >= 511){
compensation_int16 = 511;
}else if(compensation_int16 <= -512){
compensation_int16 = -512;
}
if((ret = op_cb->read(0x47, ®)))
goto out;
reg &= 0x003F;
reg |= (compensation_int16 << 6);
if((ret = op_cb->write(0x47, reg)))
goto out;
/*
//turn on VCO tracking
if((ret = op_cb->setbits(0x48, BITn(15), MASK(15))))//set 48 D15=1
goto out;
*/
out:
FM_LOG_NTC(D_MAIN,"-%s, [compensation=%d][ret=%d]\n", __func__, (int)(compensation_int16), ret);
return ret;
}
/// \brief initialise heater subsystem
/// Set directions, initialise PWM timers, read PID factors from eeprom, etc
void heater_init() {
heater_t i;
// setup PWM timers: fast PWM
// Warning 2012-01-11: these are not consistent across all AVRs
TCCR0A = MASK(WGM01) | MASK(WGM00);
// PWM frequencies in TCCR0B, see page 108 of the ATmega644 reference.
TCCR0B = MASK(CS00); // F_CPU / 256 (about 78(62.5) kHz on a 20(16) MHz chip)
#ifndef FAST_PWM
TCCR0B = MASK(CS00) | MASK(CS02); // F_CPU / 256 / 1024 (about 76(61) Hz)
#endif
TIMSK0 = 0;
OCR0A = 0;
OCR0B = 0;
// timer 1 is used for stepping
#ifdef TCCR2A
TCCR2A = MASK(WGM21) | MASK(WGM20);
// PWM frequencies in TCCR2B, see page 156 of the ATmega644 reference.
TCCR2B = MASK(CS20); // F_CPU / 256 (about 78(62.5) kHz on a 20(16) MHz chip)
#ifndef FAST_PWM
TCCR2B = MASK(CS20) | MASK(CS21) | MASK(CS22); // F_CPU / 256 / 1024
#endif
TIMSK2 = 0;
OCR2A = 0;
OCR2B = 0;
#endif
#ifdef TCCR3A
TCCR3A = MASK(WGM30);
TCCR3B = MASK(WGM32) | MASK(CS30);
TIMSK3 = 0;
OCR3A = 0;
OCR3B = 0;
#endif
#ifdef TCCR4A
#ifdef TIMER4_IS_10_BIT
// ATmega16/32U4 fourth timer is a special 10 bit timer
TCCR4A = MASK(PWM4A) | MASK(PWM4B) ; // enable A and B
TCCR4C = MASK(PWM4D); // and D
TCCR4D = MASK(WGM40); // Phase correct
TCCR4B = MASK(CS40); // no prescaler
#ifndef FAST_PWM
TCCR4B = MASK(CS40) | MASK(CS42) | MASK(CS43); // 16 MHz / 1024 / 256
//TCCR4B = MASK(CS40) | MASK(CS41) | MASK(CS43); // 16 MHz / 4096 / 256
#endif
TC4H = 0; // clear high bits
OCR4C = 0xff; // 8 bit max count at top before reset
#else
TCCR4A = MASK(WGM40);
TCCR4B = MASK(WGM42) | MASK(CS40);
#endif
TIMSK4 = 0;
OCR4A = 0;
OCR4B = 0;
#ifdef OCR4D
OCR4D = 0;
#endif
#endif
#ifdef TCCR5A
TCCR5A = MASK(WGM50);
TCCR5B = MASK(WGM52) | MASK(CS50);
TIMSK5 = 0;
OCR5A = 0;
OCR5B = 0;
#endif
/**
- - TODO - - - TODO - - - TODO - - - TODO - -
This produces a lot of initialisation code for setting up just 2 or 3
pins. Can't be optimized out, because heaters[] could have been changed
since initialisation.
A much better strategy for this is the one found in heaters-arm.c: use
the config_wrapper.h magic to initialise only what's needed. The needed
values are likely already in arduino_xxx.h.
*/
// setup pins
for (i = 0; i < NUM_HEATERS; i++) {
if (heaters[i].heater_pwm) {
*heaters[i].heater_pwm = heaters[i].invert ? 255 : 0;
// this is somewhat ugly too, but switch() won't accept pointers for reasons unknown
switch((uint16_t) heaters[i].heater_pwm) {
case (uint16_t) &OCR0A:
TCCR0A |= MASK(COM0A1);
break;
case (uint16_t) &OCR0B:
TCCR0A |= MASK(COM0B1);
break;
#ifdef TCCR2A
case (uint16_t) &OCR2A:
TCCR2A |= MASK(COM2A1);
break;
case (uint16_t) &OCR2B:
TCCR2A |= MASK(COM2B1);
break;
#endif
#ifdef TCCR3A
case (uint16_t) &OCR3AL:
TCCR3A |= MASK(COM3A1);
break;
case (uint16_t) &OCR3BL:
TCCR3A |= MASK(COM3B1);
break;
#ifdef COM3C1
case (uint16_t) &OCR3CL:
TCCR3A |= MASK(COM3C1);
break;
#endif
#endif
#ifdef TCCR4A
#if defined (OCR4AL)
case (uint16_t) &OCR4AL:
TCCR4A |= MASK(COM4A1);
break;
case (uint16_t) &OCR4BL:
TCCR4A |= MASK(COM4B1);
break;
case (uint16_t) &OCR4CL:
TCCR4A |= MASK(COM4C1);
break;
#else
// 10 bit timer
case (uint16_t) &OCR4A:
TCCR4A |= MASK(COM4A1);
break;
case (uint16_t) &OCR4B:
TCCR4A |= MASK(COM4B1);
break;
#ifdef OCR4D
case (uint16_t) &OCR4D:
TCCR4C |= MASK(COM4D1);
break;
#endif
#endif
#endif
#ifdef TCCR5A
case (uint16_t) &OCR5AL:
TCCR5A |= MASK(COM5A1);
break;
case (uint16_t) &OCR5BL:
TCCR5A |= MASK(COM5B1);
break;
case (uint16_t) &OCR5CL:
TCCR5A |= MASK(COM5C1);
break;
#endif
}
}
}
// set all heater pins to output
#undef DEFINE_HEATER
#define DEFINE_HEATER(name, pin, invert, pwm) \
SET_OUTPUT(pin); \
WRITE(pin, invert ? 1 : 0);
#include "config_wrapper.h"
#undef DEFINE_HEATER
pid_init();
}
void RGB(uint16_t Red,uint16_t Green,uint16_t Blue){
(void)(Red ? (FPTB->PCOR |= MASK(LED_R)) : (FPTB->PSOR |= MASK(LED_R)));
(void)(Green ? (FPTB->PCOR |= MASK(LED_G)) : (FPTB->PSOR |= MASK(LED_G)));
(void)(Blue ? (FPTD->PCOR |= MASK(LED_B)) : (FPTD->PSOR |= MASK(LED_B)));
}
VIDEO_START_MEMBER(harddriv_state,harddriv)
{
UINT32 *destmask, mask;
int i;
/* fill in the mask table */
destmask = m_mask_table;
for (i = 0; i < 65536; i++)
if (m_gsp_multisync)
{
mask = 0;
if (i & 0x0001) mask |= MASK(0);
if (i & 0x0004) mask |= MASK(1);
if (i & 0x0010) mask |= MASK(2);
if (i & 0x0040) mask |= MASK(3);
*destmask++ = mask;
mask = 0;
if (i & 0x0100) mask |= MASK(0);
if (i & 0x0400) mask |= MASK(1);
if (i & 0x1000) mask |= MASK(2);
if (i & 0x4000) mask |= MASK(3);
*destmask++ = mask;
}
else
{
mask = 0;
if (i & 0x0001) mask |= MASK(0);
if (i & 0x0002) mask |= MASK(1);
if (i & 0x0004) mask |= MASK(2);
if (i & 0x0008) mask |= MASK(3);
*destmask++ = mask;
mask = 0;
if (i & 0x0010) mask |= MASK(0);
if (i & 0x0020) mask |= MASK(1);
if (i & 0x0040) mask |= MASK(2);
if (i & 0x0080) mask |= MASK(3);
*destmask++ = mask;
mask = 0;
if (i & 0x0100) mask |= MASK(0);
if (i & 0x0200) mask |= MASK(1);
if (i & 0x0400) mask |= MASK(2);
if (i & 0x0800) mask |= MASK(3);
*destmask++ = mask;
mask = 0;
if (i & 0x1000) mask |= MASK(0);
if (i & 0x2000) mask |= MASK(1);
if (i & 0x4000) mask |= MASK(2);
if (i & 0x8000) mask |= MASK(3);
*destmask++ = mask;
}
/* init VRAM pointers */
m_vram_mask = m_gsp_vram.bytes() - 1;
}
void setTimerResolution(uint8_t r)
{
// assuming CS10,CS11,CS12 are adjacent bits in platform endian order,
TCCR1B = (TCCR1B & ~(MASK(CS12) | MASK(CS11) | MASK(CS10))) | (r << CS10);
}
void harddriv_state::init_video()
{
uint32_t *destmask, mask;
int i;
/* fill in the mask table */
destmask = m_mask_table;
for (i = 0; i < 65536; i++)
if (m_gsp_multisync)
{
mask = 0;
if (i & 0x0001) mask |= MASK(0);
if (i & 0x0004) mask |= MASK(1);
if (i & 0x0010) mask |= MASK(2);
if (i & 0x0040) mask |= MASK(3);
*destmask++ = mask;
mask = 0;
if (i & 0x0100) mask |= MASK(0);
if (i & 0x0400) mask |= MASK(1);
if (i & 0x1000) mask |= MASK(2);
if (i & 0x4000) mask |= MASK(3);
*destmask++ = mask;
}
else
{
mask = 0;
if (i & 0x0001) mask |= MASK(0);
if (i & 0x0002) mask |= MASK(1);
if (i & 0x0004) mask |= MASK(2);
if (i & 0x0008) mask |= MASK(3);
*destmask++ = mask;
mask = 0;
if (i & 0x0010) mask |= MASK(0);
if (i & 0x0020) mask |= MASK(1);
if (i & 0x0040) mask |= MASK(2);
if (i & 0x0080) mask |= MASK(3);
*destmask++ = mask;
mask = 0;
if (i & 0x0100) mask |= MASK(0);
if (i & 0x0200) mask |= MASK(1);
if (i & 0x0400) mask |= MASK(2);
if (i & 0x0800) mask |= MASK(3);
*destmask++ = mask;
mask = 0;
if (i & 0x1000) mask |= MASK(0);
if (i & 0x2000) mask |= MASK(1);
if (i & 0x4000) mask |= MASK(2);
if (i & 0x8000) mask |= MASK(3);
*destmask++ = mask;
}
/* init VRAM pointers */
m_vram_mask = m_gsp_vram.bytes() - 1;
}
